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11#include <common.h>
12#include <cpu_func.h>
13#include <init.h>
14#include <net.h>
15#include <netdev.h>
16#include <asm/cache.h>
17#include <asm/io.h>
18#include <u-boot/md5.h>
19#include <asm/arch/cpu.h>
20
21#define BUFLEN 16
22
23void reset_cpu(void)
24{
25 struct orion5x_cpu_registers *cpureg =
26 (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
27
28 writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
29 &cpureg->rstoutn_mask);
30 writel(readl(&cpureg->sys_soft_rst) | 1,
31 &cpureg->sys_soft_rst);
32 while (1)
33 ;
34}
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45
46unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
47{
48
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52
53 sizeval = (sizeval - 1) >> 16;
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59 sizeval |= sizeval >> 1;
60 sizeval |= sizeval >> 2;
61 sizeval |= sizeval >> 4;
62 sizeval |= sizeval >> 8;
63
64 return sizeval;
65}
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91int orion5x_config_adr_windows(void)
92{
93 struct orion5x_win_registers *winregs =
94 (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
95
96
97 writel(0, &winregs[0].ctrl);
98 writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
99 writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
100 writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
101 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
102 ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
103 ORION5X_WIN_ENABLE), &winregs[0].ctrl);
104
105 writel(0, &winregs[1].ctrl);
106 writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
107 writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
108 writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
109 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
110 ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
111 ORION5X_WIN_ENABLE), &winregs[1].ctrl);
112
113 writel(0, &winregs[2].ctrl);
114 writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
115 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
116 ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
117 ORION5X_WIN_ENABLE), &winregs[2].ctrl);
118
119 writel(0, &winregs[3].ctrl);
120 writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
121 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
122 ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
123 ORION5X_WIN_ENABLE), &winregs[3].ctrl);
124
125 writel(0, &winregs[4].ctrl);
126 writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
127 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
128 ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
129 ORION5X_WIN_ENABLE), &winregs[4].ctrl);
130
131 writel(0, &winregs[5].ctrl);
132 writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
133 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
134 ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
135 ORION5X_WIN_ENABLE), &winregs[5].ctrl);
136
137 writel(0, &winregs[6].ctrl);
138 writel(ORION5X_ADR_BOOTROM, &winregs[6].base);
139 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
140 ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
141 ORION5X_WIN_ENABLE), &winregs[6].ctrl);
142
143 writel(0, &winregs[7].ctrl);
144 writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
145 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
146 ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
147 ORION5X_WIN_ENABLE), &winregs[7].ctrl);
148
149 writel(0, &winregs[6].ctrl);
150 writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
151 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
152 ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
153 ORION5X_WIN_ENABLE), &winregs[6].ctrl);
154
155 return 0;
156}
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162u32 orion5x_device_id(void)
163{
164 return readl(PCIE_DEV_ID_OFF) >> 16;
165}
166
167u32 orion5x_device_rev(void)
168{
169 return readl(PCIE_DEV_REV_OFF) & 0xff;
170}
171
172#if defined(CONFIG_DISPLAY_CPUINFO)
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179
180int print_cpuinfo(void)
181{
182 char dev_str[7];
183 char rev_str[5];
184 char *dev_name = NULL;
185 char *rev_name = NULL;
186
187 u32 dev = orion5x_device_id();
188 u32 rev = orion5x_device_rev();
189
190 if (dev == MV88F5181_DEV_ID) {
191 dev_name = "MV88F5181";
192 if (rev == MV88F5181_REV_B1)
193 rev_name = "B1";
194 else if (rev == MV88F5181L_REV_A1) {
195 dev_name = "MV88F5181L";
196 rev_name = "A1";
197 } else if (rev == MV88F5181L_REV_A0) {
198 dev_name = "MV88F5181L";
199 rev_name = "A0";
200 }
201 } else if (dev == MV88F5182_DEV_ID) {
202 dev_name = "MV88F5182";
203 if (rev == MV88F5182_REV_A2)
204 rev_name = "A2";
205 } else if (dev == MV88F5281_DEV_ID) {
206 dev_name = "MV88F5281";
207 if (rev == MV88F5281_REV_D2)
208 rev_name = "D2";
209 else if (rev == MV88F5281_REV_D1)
210 rev_name = "D1";
211 else if (rev == MV88F5281_REV_D0)
212 rev_name = "D0";
213 } else if (dev == MV88F6183_DEV_ID) {
214 dev_name = "MV88F6183";
215 if (rev == MV88F6183_REV_B0)
216 rev_name = "B0";
217 }
218 if (dev_name == NULL) {
219 sprintf(dev_str, "0x%04x", dev);
220 dev_name = dev_str;
221 }
222 if (rev_name == NULL) {
223 sprintf(rev_str, "0x%02x", rev);
224 rev_name = rev_str;
225 }
226
227 printf("SoC: Orion5x %s-%s\n", dev_name, rev_name);
228
229 return 0;
230}
231#endif
232
233#ifdef CONFIG_ARCH_CPU_INIT
234int arch_cpu_init(void)
235{
236
237 invalidate_l2_cache();
238
239#ifdef CONFIG_SPL_BUILD
240 orion5x_config_adr_windows();
241#endif
242
243 return 0;
244}
245#endif
246
247
248
249
250#if defined(CONFIG_ARCH_MISC_INIT)
251int arch_misc_init(void)
252{
253 u32 temp;
254
255
256 temp = readfr_extra_feature_reg();
257 temp &= ~(1 << 28);
258 writefr_extra_feature_reg(temp);
259
260 temp = readfr_extra_feature_reg();
261 temp &= ~(1 << 29);
262 writefr_extra_feature_reg(temp);
263
264
265 temp = readfr_extra_feature_reg();
266
267 temp |= (1 << 24);
268
269 temp |= (1 << 22);
270 writefr_extra_feature_reg(temp);
271
272 icache_enable();
273
274 temp = get_cr();
275 set_cr(temp & ~CR_V);
276
277
278
279 writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
280 writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
281 writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
282 writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00);
283 writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
284 writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c);
285
286
287 timer_init_r();
288 return 0;
289}
290#endif
291
292#ifdef CONFIG_MVGBE
293int cpu_eth_init(struct bd_info *bis)
294{
295 mvgbe_initialize(bis);
296 return 0;
297}
298#endif
299