1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> 4 * 5 */ 6 7#ifndef _FIREWALL_H_ 8#define _FIREWALL_H_ 9 10#include <linux/bitops.h> 11 12struct socfpga_firwall_l4_per { 13 u32 nand; /* 0x00 */ 14 u32 nand_data; 15 u32 _pad_0x8; 16 u32 usb0; 17 u32 usb1; /* 0x10 */ 18 u32 _pad_0x14; 19 u32 _pad_0x18; 20 u32 spim0; 21 u32 spim1; /* 0x20 */ 22 u32 spis0; 23 u32 spis1; 24 u32 emac0; 25 u32 emac1; /* 0x30 */ 26 u32 emac2; 27 u32 _pad_0x38; 28 u32 _pad_0x3c; 29 u32 sdmmc; /* 0x40 */ 30 u32 gpio0; 31 u32 gpio1; 32 u32 _pad_0x4c; 33 u32 i2c0; /* 0x50 */ 34 u32 i2c1; 35 u32 i2c2; 36 u32 i2c3; 37 u32 i2c4; /* 0x60 */ 38 u32 timer0; 39 u32 timer1; 40 u32 uart0; 41 u32 uart1; /* 0x70 */ 42}; 43 44struct socfpga_firwall_l4_sys { 45 u32 _pad_0x00; /* 0x00 */ 46 u32 _pad_0x04; 47 u32 dma_ecc; 48 u32 emac0rx_ecc; 49 u32 emac0tx_ecc; /* 0x10 */ 50 u32 emac1rx_ecc; 51 u32 emac1tx_ecc; 52 u32 emac2rx_ecc; 53 u32 emac2tx_ecc; /* 0x20 */ 54 u32 _pad_0x24; 55 u32 _pad_0x28; 56 u32 nand_ecc; 57 u32 nand_read_ecc; /* 0x30 */ 58 u32 nand_write_ecc; 59 u32 ocram_ecc; 60 u32 _pad_0x3c; 61 u32 sdmmc_ecc; /* 0x40 */ 62 u32 usb0_ecc; 63 u32 usb1_ecc; 64 u32 clock_manager; 65 u32 _pad_0x50; /* 0x50 */ 66 u32 io_manager; 67 u32 reset_manager; 68 u32 system_manager; 69 u32 osc0_timer; /* 0x60 */ 70 u32 osc1_timer; 71 u32 watchdog0; 72 u32 watchdog1; 73 u32 watchdog2; /* 0x70 */ 74 u32 watchdog3; 75}; 76 77#define FIREWALL_L4_DISABLE_ALL (BIT(0) | BIT(24) | BIT(16)) 78#define FIREWALL_BRIDGE_DISABLE_ALL (~0) 79 80/* Cache coherency unit (CCU) registers */ 81#define CCU_CPU0_MPRT_ADBASE_DDRREG 0x4400 82#define CCU_CPU0_MPRT_ADBASE_MEMSPACE0 0x45c0 83#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A 0x45e0 84#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B 0x4600 85#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C 0x4620 86#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D 0x4640 87#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E 0x4660 88 89#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0 0x4688 90 91#define CCU_IOM_MPRT_ADBASE_MEMSPACE0 0x18560 92#define CCU_IOM_MPRT_ADBASE_MEMSPACE1A 0x18580 93#define CCU_IOM_MPRT_ADBASE_MEMSPACE1B 0x185a0 94#define CCU_IOM_MPRT_ADBASE_MEMSPACE1C 0x185c0 95#define CCU_IOM_MPRT_ADBASE_MEMSPACE1D 0x185e0 96#define CCU_IOM_MPRT_ADBASE_MEMSPACE1E 0x18600 97 98#define CCU_IOM_MPRT_ADMASK_MEM_RAM0 0x18628 99 100#define CCU_TCU_MPRT_ADBASE_MEMSPACE0 0x2c520 101#define CCU_TCU_MPRT_ADBASE_MEMSPACE1A 0x2c540 102#define CCU_TCU_MPRT_ADBASE_MEMSPACE1B 0x2c560 103#define CCU_TCU_MPRT_ADBASE_MEMSPACE1C 0x2c580 104#define CCU_TCU_MPRT_ADBASE_MEMSPACE1D 0x2c5a0 105#define CCU_TCU_MPRT_ADBASE_MEMSPACE1E 0x2c5c0 106 107#define CCU_ADMASK_P_MASK BIT(0) 108#define CCU_ADMASK_NS_MASK BIT(1) 109 110#define CCU_ADBASE_DI_MASK BIT(4) 111 112#define CCU_REG_ADDR(reg) \ 113 (SOCFPGA_CCU_ADDRESS + (reg)) 114 115/* Firewall MPU DDR SCR registers */ 116#define FW_MPU_DDR_SCR_EN 0x00 117#define FW_MPU_DDR_SCR_EN_SET 0x04 118#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT 0x18 119#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0x1c 120#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98 121#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c 122 123#define MPUREGION0_ENABLE BIT(0) 124#define NONMPUREGION0_ENABLE BIT(8) 125 126#define FW_MPU_DDR_SCR_WRITEL(data, reg) \ 127 writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg)) 128 129void firewall_setup(void); 130 131#endif /* _FIREWALL_H_ */ 132