LXR uboot/arch/arm/mach-uniphier/arm32/psci.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2016 Socionext Inc.
   4 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   5 */
   6
   7#include <cpu_func.h>
   8#include <linux/bitops.h>
   9#include <linux/delay.h>
  10#include <linux/io.h>
  11#include <linux/kernel.h>
  12#include <linux/printk.h>
  13#include <linux/psci.h>
  14#include <linux/sizes.h>
  15#include <asm/processor.h>
  16#include <asm/psci.h>
  17#include <asm/secure.h>
  18#include <asm/system.h>
  19
  20#include "../debug.h"
  21#include "../soc-info.h"
  22#include "arm-mpcore.h"
  23#include "cache-uniphier.h"
  24
  25#define UNIPHIER_SMPCTRL_ROM_RSV2       0x59801208
  26
  27void uniphier_smp_trampoline(void);
  28void uniphier_smp_trampoline_end(void);
  29u32 uniphier_smp_booted[CONFIG_ARMV7_PSCI_NR_CPUS];
  30
  31static int uniphier_get_nr_cpus(void)
  32{
  33        switch (uniphier_get_soc_id()) {
  34        case UNIPHIER_PRO4_ID:
  35        case UNIPHIER_PRO5_ID:
  36                return 2;
  37        case UNIPHIER_PXS2_ID:
  38        case UNIPHIER_LD6B_ID:
  39                return 4;
  40        default:
  41                return 1;
  42        }
  43}
  44
  45static void uniphier_smp_kick_all_cpus(void)
  46{
  47        const u32 target_ways = BIT(0);
  48        size_t trmp_size;
  49        u32 trmp_src = (unsigned long)uniphier_smp_trampoline;
  50        u32 trmp_src_end = (unsigned long)uniphier_smp_trampoline_end;
  51        u32 trmp_dest, trmp_dest_end;
  52        int nr_cpus, i;
  53        int timeout = 1000;
  54
  55        nr_cpus = uniphier_get_nr_cpus();
  56        if (nr_cpus == 1)
  57                return;
  58
  59        for (i = 0; i < nr_cpus; i++)   /* lock ways for all CPUs */
  60                uniphier_cache_set_active_ways(i, 0);
  61        uniphier_cache_inv_way(target_ways);
  62        uniphier_cache_enable();
  63
  64        /* copy trampoline code */
  65        uniphier_cache_prefetch_range(trmp_src, trmp_src_end, target_ways);
  66
  67        trmp_size = trmp_src_end - trmp_src;
  68
  69        trmp_dest = trmp_src & (SZ_64K - 1);
  70        trmp_dest += SZ_1M - SZ_64K * 2;
  71
  72        trmp_dest_end = trmp_dest + trmp_size;
  73
  74        uniphier_cache_touch_range(trmp_dest, trmp_dest_end, target_ways);
  75
  76        writel(trmp_dest, UNIPHIER_SMPCTRL_ROM_RSV2);
  77
  78        asm("dsb        ishst\n" /* Ensure the write to ROM_RSV2 is visible */
  79            "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
  80
  81        while (--timeout) {
  82                int all_booted = 1;
  83
  84                for (i = 1; i < nr_cpus; i++)
  85                        if (!uniphier_smp_booted[i])
  86                                all_booted = 0;
  87                if (all_booted)
  88                        break;
  89                udelay(1);
  90
  91                /* barrier here because uniphier_smp_booted[] may be updated */
  92                cpu_relax();
  93        }
  94
  95        if (!timeout)
  96                pr_warn("warning: some of secondary CPUs may not boot\n");
  97
  98        uniphier_cache_disable();
  99}
 100
 101void psci_board_init(void)
 102{
 103        unsigned long scu_base;
 104        u32 scu_ctrl, tmp;
 105
 106        asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (scu_base));
 107
 108        scu_ctrl = readl(scu_base + 0x30);
 109        if (!(scu_ctrl & 1))
 110                writel(scu_ctrl | 0x1, scu_base + 0x30);
 111
 112        scu_ctrl = readl(scu_base + SCU_CTRL);
 113        scu_ctrl |= SCU_ENABLE | SCU_STANDBY_ENABLE;
 114        writel(scu_ctrl, scu_base + SCU_CTRL);
 115
 116        tmp = readl(scu_base + SCU_SNSAC);
 117        tmp |= 0xfff;
 118        writel(tmp, scu_base + SCU_SNSAC);
 119
 120        uniphier_smp_kick_all_cpus();
 121}
 122
 123void psci_arch_init(void)
 124{
 125        u32 actlr;
 126
 127        asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
 128        actlr |= 0x41;          /* set SMP and FW bits */
 129        asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
 130}
 131
 132u32 uniphier_psci_holding_pen_release __secure_data = 0xffffffff;
 133
 134s32 __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point,
 135                         u32 context_id)
 136{
 137        u32 cpu = cpuid & 0xff;
 138
 139        debug_puts("[U-Boot PSCI]  psci_cpu_on: cpuid=");
 140        debug_puth(cpuid);
 141        debug_puts(", entry_point=");
 142        debug_puth(entry_point);
 143        debug_puts(", context_id=");
 144        debug_puth(context_id);
 145        debug_puts("\n");
 146
 147        psci_save(cpu, entry_point, context_id);
 148
 149        /* We assume D-cache is off, so do not call flush_dcache() here */
 150        uniphier_psci_holding_pen_release = cpu;
 151
 152        /* Send an event to wake up the secondary CPU. */
 153        asm("dsb        ishst\n"
 154            "sev");
 155
 156        return PSCI_RET_SUCCESS;
 157}
 158
 159void __secure psci_system_reset(void)
 160{
 161        reset_cpu();
 162}
 163