uboot/arch/powerpc/cpu/mpc86xx/cpu.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
   4 * Jeff Brown
   5 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   6 */
   7
   8#include <common.h>
   9#include <cpu_func.h>
  10#include <log.h>
  11#include <time.h>
  12#include <vsprintf.h>
  13#include <watchdog.h>
  14#include <command.h>
  15#include <asm/cache.h>
  16#include <asm/global_data.h>
  17#include <asm/mmu.h>
  18#include <mpc86xx.h>
  19#include <asm/fsl_law.h>
  20#include <asm/ppc.h>
  21
  22DECLARE_GLOBAL_DATA_PTR;
  23
  24/*
  25 * Default board reset function
  26 */
  27static void
  28__board_reset(void)
  29{
  30        /* Do nothing */
  31}
  32void board_reset(void) __attribute__((weak, alias("__board_reset")));
  33
  34
  35int
  36checkcpu(void)
  37{
  38        sys_info_t sysinfo;
  39        uint pvr, svr;
  40        uint major, minor;
  41        char buf1[32], buf2[32];
  42        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  43        volatile ccsr_gur_t *gur = &immap->im_gur;
  44        struct cpu_type *cpu;
  45        uint msscr0 = mfspr(MSSCR0);
  46
  47        svr = get_svr();
  48        major = SVR_MAJ(svr);
  49        minor = SVR_MIN(svr);
  50
  51        if (cpu_numcores() > 1) {
  52#ifndef CONFIG_MP
  53                puts("Unicore software on multiprocessor system!!\n"
  54                     "To enable mutlticore build define CONFIG_MP\n");
  55#endif
  56        }
  57        puts("CPU:   ");
  58
  59        cpu = gd->arch.cpu;
  60
  61        puts(cpu->name);
  62
  63        printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  64        puts("Core:  ");
  65
  66        pvr = get_pvr();
  67        major = PVR_E600_MAJ(pvr);
  68        minor = PVR_E600_MIN(pvr);
  69
  70        printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0);
  71        if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
  72                puts("\n    Core1Translation Enabled");
  73        debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
  74
  75        printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
  76
  77        get_sys_info(&sysinfo);
  78
  79        puts("Clock Configuration:\n");
  80        printf("       CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freq_processor));
  81        printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
  82        printf("       DDR:%-4s MHz (%s MT/s data rate), ",
  83                strmhz(buf1, sysinfo.freq_systembus / 2),
  84                strmhz(buf2, sysinfo.freq_systembus));
  85
  86        if (sysinfo.freq_localbus > LCRR_CLKDIV) {
  87                printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
  88        } else {
  89                printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
  90                       sysinfo.freq_localbus);
  91        }
  92
  93        puts("L1:    D-cache 32 KiB enabled\n");
  94        puts("       I-cache 32 KiB enabled\n");
  95
  96        puts("L2:    ");
  97        if (get_l2cr() & 0x80000000) {
  98#if defined(CONFIG_ARCH_MPC8610)
  99                puts("256");
 100#elif defined(CONFIG_ARCH_MPC8641)
 101                puts("512");
 102#endif
 103                puts(" KiB enabled\n");
 104        } else {
 105                puts("Disabled\n");
 106        }
 107
 108        return 0;
 109}
 110
 111
 112int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 113{
 114        volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 115        volatile ccsr_gur_t *gur = &immap->im_gur;
 116
 117        /* Attempt board-specific reset */
 118        board_reset();
 119
 120        /* Next try asserting HRESET_REQ */
 121        out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
 122
 123        while (1)
 124                ;
 125
 126        return 1;
 127}
 128
 129
 130/*
 131 * Get timebase clock frequency
 132 */
 133unsigned long
 134get_tbclk(void)
 135{
 136        sys_info_t sys_info;
 137
 138        get_sys_info(&sys_info);
 139        return (sys_info.freq_systembus + 3L) / 4L;
 140}
 141
 142
 143#if defined(CONFIG_WATCHDOG)
 144void
 145watchdog_reset(void)
 146{
 147#if defined(CONFIG_ARCH_MPC8610)
 148        /*
 149         * This actually feed the hard enabled watchdog.
 150         */
 151        volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 152        volatile ccsr_wdt_t *wdt = &immap->im_wdt;
 153        volatile ccsr_gur_t *gur = &immap->im_gur;
 154        u32 tmp = gur->pordevsr;
 155
 156        if (tmp & 0x4000) {
 157                wdt->swsrr = 0x556c;
 158                wdt->swsrr = 0xaa39;
 159        }
 160#endif
 161}
 162#endif  /* CONFIG_WATCHDOG */
 163
 164/*
 165 * Print out the state of various machine registers.
 166 * Currently prints out LAWs, BR0/OR0, and BATs
 167 */
 168void print_reginfo(void)
 169{
 170        print_bats();
 171        print_laws();
 172        print_lbc_regs();
 173}
 174
 175/*
 176 * Set the DDR BATs to reflect the actual size of DDR.
 177 *
 178 * dram_size is the actual size of DDR, in bytes
 179 *
 180 * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
 181 * are using a single BAT to cover DDR.
 182 *
 183 * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
 184 * is not defined) then we might have a situation where U-Boot will attempt
 185 * to relocated itself outside of the region mapped by DBAT0.
 186 * This will cause a machine check.
 187 *
 188 * Currently we are limited to power of two sized DDR since we only use a
 189 * single bat.  If a non-power of two size is used that is less than
 190 * CONFIG_MAX_MEM_MAPPED u-boot will crash.
 191 *
 192 */
 193void setup_ddr_bat(phys_addr_t dram_size)
 194{
 195        unsigned long batu, bl;
 196
 197        bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
 198
 199        if (BATU_SIZE(bl) != dram_size) {
 200                u64 sz = (u64)dram_size - BATU_SIZE(bl);
 201                print_size(sz, " left unmapped\n");
 202        }
 203
 204        batu = bl | BATU_VS | BATU_VP;
 205        write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
 206        write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
 207}
 208