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7#include <common.h>
8#include <i2c.h>
9#include <fdt_support.h>
10#include <fsl_ddr_sdram.h>
11#include <init.h>
12#include <asm/global_data.h>
13#include <asm/io.h>
14#include <asm/arch/clock.h>
15#include <asm/arch/fsl_serdes.h>
16#include <asm/arch/ppa.h>
17#include <asm/arch/fdt.h>
18#include <asm/arch/mmu.h>
19#include <asm/arch/cpu.h>
20#include <asm/arch/soc.h>
21#include <asm/arch-fsl-layerscape/fsl_icid.h>
22#include <ahci.h>
23#include <hwconfig.h>
24#include <mmc.h>
25#include <scsi.h>
26#include <fm_eth.h>
27#include <fsl_csu.h>
28#include <fsl_esdhc.h>
29#include <fsl_ifc.h>
30#include <fsl_sec.h>
31#include <spl.h>
32
33#include "../common/vid.h"
34#include "../common/qixis.h"
35#include "ls1046aqds_qixis.h"
36
37DECLARE_GLOBAL_DATA_PTR;
38
39#ifdef CONFIG_SYS_I2C_EARLY_INIT
40void i2c_early_init_f(void);
41#endif
42
43#ifdef CONFIG_TFABOOT
44struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
45 {
46 "nor0",
47 CONFIG_SYS_NOR0_CSPR,
48 CONFIG_SYS_NOR0_CSPR_EXT,
49 CONFIG_SYS_NOR_AMASK,
50 CONFIG_SYS_NOR_CSOR,
51 {
52 CONFIG_SYS_NOR_FTIM0,
53 CONFIG_SYS_NOR_FTIM1,
54 CONFIG_SYS_NOR_FTIM2,
55 CONFIG_SYS_NOR_FTIM3
56 },
57
58 },
59 {
60 "nor1",
61 CONFIG_SYS_NOR1_CSPR,
62 CONFIG_SYS_NOR1_CSPR_EXT,
63 CONFIG_SYS_NOR_AMASK,
64 CONFIG_SYS_NOR_CSOR,
65 {
66 CONFIG_SYS_NOR_FTIM0,
67 CONFIG_SYS_NOR_FTIM1,
68 CONFIG_SYS_NOR_FTIM2,
69 CONFIG_SYS_NOR_FTIM3
70 },
71 },
72 {
73 "nand",
74 CONFIG_SYS_NAND_CSPR,
75 CONFIG_SYS_NAND_CSPR_EXT,
76 CONFIG_SYS_NAND_AMASK,
77 CONFIG_SYS_NAND_CSOR,
78 {
79 CONFIG_SYS_NAND_FTIM0,
80 CONFIG_SYS_NAND_FTIM1,
81 CONFIG_SYS_NAND_FTIM2,
82 CONFIG_SYS_NAND_FTIM3
83 },
84 },
85 {
86 "fpga",
87 CONFIG_SYS_FPGA_CSPR,
88 CONFIG_SYS_FPGA_CSPR_EXT,
89 CONFIG_SYS_FPGA_AMASK,
90 CONFIG_SYS_FPGA_CSOR,
91 {
92 CONFIG_SYS_FPGA_FTIM0,
93 CONFIG_SYS_FPGA_FTIM1,
94 CONFIG_SYS_FPGA_FTIM2,
95 CONFIG_SYS_FPGA_FTIM3
96 },
97 }
98};
99
100struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
101 {
102 "nand",
103 CONFIG_SYS_NAND_CSPR,
104 CONFIG_SYS_NAND_CSPR_EXT,
105 CONFIG_SYS_NAND_AMASK,
106 CONFIG_SYS_NAND_CSOR,
107 {
108 CONFIG_SYS_NAND_FTIM0,
109 CONFIG_SYS_NAND_FTIM1,
110 CONFIG_SYS_NAND_FTIM2,
111 CONFIG_SYS_NAND_FTIM3
112 },
113 },
114 {
115 "nor0",
116 CONFIG_SYS_NOR0_CSPR,
117 CONFIG_SYS_NOR0_CSPR_EXT,
118 CONFIG_SYS_NOR_AMASK,
119 CONFIG_SYS_NOR_CSOR,
120 {
121 CONFIG_SYS_NOR_FTIM0,
122 CONFIG_SYS_NOR_FTIM1,
123 CONFIG_SYS_NOR_FTIM2,
124 CONFIG_SYS_NOR_FTIM3
125 },
126 },
127 {
128 "nor1",
129 CONFIG_SYS_NOR1_CSPR,
130 CONFIG_SYS_NOR1_CSPR_EXT,
131 CONFIG_SYS_NOR_AMASK,
132 CONFIG_SYS_NOR_CSOR,
133 {
134 CONFIG_SYS_NOR_FTIM0,
135 CONFIG_SYS_NOR_FTIM1,
136 CONFIG_SYS_NOR_FTIM2,
137 CONFIG_SYS_NOR_FTIM3
138 },
139 },
140 {
141 "fpga",
142 CONFIG_SYS_FPGA_CSPR,
143 CONFIG_SYS_FPGA_CSPR_EXT,
144 CONFIG_SYS_FPGA_AMASK,
145 CONFIG_SYS_FPGA_CSOR,
146 {
147 CONFIG_SYS_FPGA_FTIM0,
148 CONFIG_SYS_FPGA_FTIM1,
149 CONFIG_SYS_FPGA_FTIM2,
150 CONFIG_SYS_FPGA_FTIM3
151 },
152 }
153};
154
155void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
156{
157 enum boot_src src = get_boot_src();
158
159 if (src == BOOT_SOURCE_IFC_NAND)
160 regs_info->regs = ifc_cfg_nand_boot;
161 else
162 regs_info->regs = ifc_cfg_nor_boot;
163 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
164}
165
166#endif
167
168enum {
169 MUX_TYPE_GPIO,
170};
171
172int checkboard(void)
173{
174#ifdef CONFIG_TFABOOT
175 enum boot_src src = get_boot_src();
176#endif
177 char buf[64];
178#ifndef CONFIG_SD_BOOT
179 u8 sw;
180#endif
181
182 puts("Board: LS1046AQDS, boot from ");
183
184#ifdef CONFIG_TFABOOT
185 if (src == BOOT_SOURCE_SD_MMC)
186 puts("SD\n");
187 else {
188#endif
189
190#ifdef CONFIG_SD_BOOT
191 puts("SD\n");
192#else
193 sw = QIXIS_READ(brdcfg[0]);
194 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
195
196 if (sw < 0x8)
197 printf("vBank: %d\n", sw);
198 else if (sw == 0x8)
199 puts("PromJet\n");
200 else if (sw == 0x9)
201 puts("NAND\n");
202 else if (sw == 0xF)
203 printf("QSPI\n");
204 else
205 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
206#endif
207
208#ifdef CONFIG_TFABOOT
209 }
210#endif
211 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
212 QIXIS_READ(id), QIXIS_READ(arch));
213
214 printf("FPGA: v%d (%s), build %d\n",
215 (int)QIXIS_READ(scver), qixis_read_tag(buf),
216 (int)qixis_read_minor());
217
218 return 0;
219}
220
221bool if_board_diff_clk(void)
222{
223 u8 diff_conf = QIXIS_READ(brdcfg[11]);
224
225 return diff_conf & 0x40;
226}
227
228unsigned long get_board_sys_clk(void)
229{
230 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
231
232 switch (sysclk_conf & 0x0f) {
233 case QIXIS_SYSCLK_64:
234 return 64000000;
235 case QIXIS_SYSCLK_83:
236 return 83333333;
237 case QIXIS_SYSCLK_100:
238 return 100000000;
239 case QIXIS_SYSCLK_125:
240 return 125000000;
241 case QIXIS_SYSCLK_133:
242 return 133333333;
243 case QIXIS_SYSCLK_150:
244 return 150000000;
245 case QIXIS_SYSCLK_160:
246 return 160000000;
247 case QIXIS_SYSCLK_166:
248 return 166666666;
249 }
250
251 return 66666666;
252}
253
254unsigned long get_board_ddr_clk(void)
255{
256 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
257
258 if (if_board_diff_clk())
259 return get_board_sys_clk();
260 switch ((ddrclk_conf & 0x30) >> 4) {
261 case QIXIS_DDRCLK_100:
262 return 100000000;
263 case QIXIS_DDRCLK_125:
264 return 125000000;
265 case QIXIS_DDRCLK_133:
266 return 133333333;
267 }
268
269 return 66666666;
270}
271
272#ifdef CONFIG_LPUART
273u32 get_lpuart_clk(void)
274{
275 return gd->bus_clk;
276}
277#endif
278
279int select_i2c_ch_pca9547(u8 ch, int bus_num)
280{
281 int ret;
282#if CONFIG_IS_ENABLED(DM_I2C)
283 struct udevice *dev;
284
285 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
286 1, &dev);
287 if (ret) {
288 printf("%s: Cannot find udev for a bus %d\n", __func__,
289 bus_num);
290 return ret;
291 }
292 ret = dm_i2c_write(dev, 0, &ch, 1);
293#else
294 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
295#endif
296 if (ret) {
297 puts("PCA: failed to select proper channel\n");
298 return ret;
299 }
300
301 return 0;
302}
303
304int dram_init(void)
305{
306
307
308
309
310
311
312
313 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
314 fsl_initdram();
315#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
316 defined(CONFIG_SPL_BUILD)
317
318 update_early_mmu_table();
319#endif
320
321 return 0;
322}
323
324int i2c_multiplexer_select_vid_channel(u8 channel)
325{
326 return select_i2c_ch_pca9547(channel, 0);
327}
328
329int board_early_init_f(void)
330{
331 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
332#ifdef CONFIG_HAS_FSL_XHCI_USB
333 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
334 u32 usb_pwrfault;
335#endif
336#ifdef CONFIG_LPUART
337 u8 uart;
338#endif
339
340
341
342
343 out_le32(cntcr, 0x1);
344
345#ifdef CONFIG_SYS_I2C_EARLY_INIT
346 i2c_early_init_f();
347#endif
348 fsl_lsch2_early_init_f();
349
350#ifdef CONFIG_HAS_FSL_XHCI_USB
351 out_be32(&scfg->rcwpmuxcr0, 0x3333);
352 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
353 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
354 SCFG_USBPWRFAULT_USB3_SHIFT) |
355 (SCFG_USBPWRFAULT_DEDICATED <<
356 SCFG_USBPWRFAULT_USB2_SHIFT) |
357 (SCFG_USBPWRFAULT_SHARED <<
358 SCFG_USBPWRFAULT_USB1_SHIFT);
359 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
360#endif
361
362#ifdef CONFIG_LPUART
363
364 uart = QIXIS_READ(brdcfg[14]);
365 uart &= ~CFG_UART_MUX_MASK;
366 uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
367 QIXIS_WRITE(brdcfg[14], uart);
368#endif
369
370 return 0;
371}
372
373#ifdef CONFIG_FSL_DEEP_SLEEP
374
375bool is_warm_boot(void)
376{
377#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
378 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
379
380 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
381 return 1;
382
383 return 0;
384}
385#endif
386
387int config_board_mux(int ctrl_type)
388{
389 u8 reg14;
390
391 reg14 = QIXIS_READ(brdcfg[14]);
392
393 switch (ctrl_type) {
394 case MUX_TYPE_GPIO:
395 reg14 = (reg14 & (~0x6)) | 0x2;
396 break;
397 default:
398 puts("Unsupported mux interface type\n");
399 return -1;
400 }
401
402 QIXIS_WRITE(brdcfg[14], reg14);
403
404 return 0;
405}
406
407int config_serdes_mux(void)
408{
409 return 0;
410}
411
412#ifdef CONFIG_MISC_INIT_R
413int misc_init_r(void)
414{
415 if (hwconfig("gpio"))
416 config_board_mux(MUX_TYPE_GPIO);
417
418 return 0;
419}
420#endif
421
422int board_init(void)
423{
424 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
425
426#ifdef CONFIG_SYS_FSL_SERDES
427 config_serdes_mux();
428#endif
429
430 if (adjust_vdd(0))
431 printf("Warning: Adjusting core voltage failed.\n");
432
433#ifdef CONFIG_FSL_LS_PPA
434 ppa_init();
435#endif
436
437#ifdef CONFIG_NXP_ESBC
438
439
440
441
442
443
444 u32 val;
445 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
446 out_le32(SMMU_SCR0, val);
447 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
448 out_le32(SMMU_NSCR0, val);
449#endif
450
451#ifdef CONFIG_FSL_CAAM
452 sec_init();
453#endif
454
455 return 0;
456}
457
458#ifdef CONFIG_OF_BOARD_SETUP
459int ft_board_setup(void *blob, struct bd_info *bd)
460{
461 u64 base[CONFIG_NR_DRAM_BANKS];
462 u64 size[CONFIG_NR_DRAM_BANKS];
463 u8 reg;
464
465
466 base[0] = gd->bd->bi_dram[0].start;
467 size[0] = gd->bd->bi_dram[0].size;
468 base[1] = gd->bd->bi_dram[1].start;
469 size[1] = gd->bd->bi_dram[1].size;
470
471 fdt_fixup_memory_banks(blob, base, size, 2);
472 ft_cpu_setup(blob, bd);
473
474#ifdef CONFIG_SYS_DPAA_FMAN
475#ifndef CONFIG_DM_ETH
476 fdt_fixup_fman_ethernet(blob);
477#endif
478 fdt_fixup_board_enet(blob);
479#endif
480
481 fdt_fixup_icid(blob);
482
483 reg = QIXIS_READ(brdcfg[0]);
484 reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
485
486
487 if (reg == 0xF)
488 do_fixup_by_compat(blob, "fsl,ifc",
489 "status", "disabled", 8 + 1, 1);
490
491 return 0;
492}
493#endif
494
495u8 flash_read8(void *addr)
496{
497 return __raw_readb(addr + 1);
498}
499
500void flash_write16(u16 val, void *addr)
501{
502 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
503
504 __raw_writew(shftval, addr);
505}
506
507u16 flash_read16(void *addr)
508{
509 u16 val = __raw_readw(addr);
510
511 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
512}
513
514#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
515void *env_sf_get_env_addr(void)
516{
517 return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
518}
519#endif
520
