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5
6#include <common.h>
7#include <i2c.h>
8#include <asm/io.h>
9#include <asm/arch/immap_ls102xa.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/fsl_serdes.h>
12#include <asm/arch/ls102xa_devdis.h>
13#include <asm/arch/ls102xa_soc.h>
14#include <hwconfig.h>
15#include <mmc.h>
16#include <fsl_csu.h>
17#include <fsl_esdhc.h>
18#include <fsl_ifc.h>
19#include <fsl_immap.h>
20#include <netdev.h>
21#include <fsl_mdio.h>
22#include <tsec.h>
23#include <fsl_sec.h>
24#include <fsl_devdis.h>
25#include <fsl_ddr.h>
26#include <spl.h>
27#include <fdt_support.h>
28#include <fsl_qe.h>
29#include <fsl_validate.h>
30
31#include "../common/common.h"
32#include "../common/qrio.h"
33
34DECLARE_GLOBAL_DATA_PTR;
35
36static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
37
38int checkboard(void)
39{
40 show_qrio();
41
42 return 0;
43}
44
45int dram_init(void)
46{
47 return fsl_initdram();
48}
49
50int board_early_init_f(void)
51{
52 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
53 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
54 struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
55
56
57 setbits_be32(&gur->ddrclkdr, 2);
58
59
60 setbits_be32(&ifc.gregs->ifc_gcr, 12 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
61 setbits_be32(&ifc.gregs->ifc_ccr, IFC_CCR_CLK_DIV(3) |
62 IFC_CCR_INV_CLK_EN);
63
64
65 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
66 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
67
68 init_early_memctl_regs();
69
70
71 qrio_uprstreq(UPREQ_CORE_RST);
72
73#if CONFIG_IS_ENABLED(TARGET_PG_WCOM_SELI8)
74 qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST);
75 qrio_wdmask(KM_LIU_RST, true);
76
77 qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST);
78 qrio_wdmask(KM_PAXK_RST, true);
79#endif
80
81#if CONFIG_IS_ENABLED(TARGET_PG_WCOM_EXPU1)
82 qrio_prstcfg(WCOM_TMG_RST, PRSTCFG_POWUP_UNIT_RST);
83 qrio_wdmask(WCOM_TMG_RST, true);
84
85 qrio_prstcfg(WCOM_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
86 qrio_prst(WCOM_PHY_RST, false, false);
87
88 qrio_prstcfg(WCOM_QSFP_RST, PRSTCFG_POWUP_UNIT_RST);
89 qrio_wdmask(WCOM_QSFP_RST, true);
90
91 qrio_prstcfg(WCOM_CLIPS_RST, PRSTCFG_POWUP_UNIT_RST);
92 qrio_prst(WCOM_CLIPS_RST, false, false);
93#endif
94 qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
95 qrio_prst(KM_DBG_ETH_RST, false, false);
96
97 i2c_deblock_gpio_cfg();
98
99
100 qrio_set_leds();
101
102
103 qrio_enable_app_buffer();
104
105 arch_soc_init();
106
107 return 0;
108}
109
110int board_init(void)
111{
112 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A010315))
113 erratum_a010315();
114
115 fsl_serdes_init();
116
117 ls102xa_smmu_stream_id_init();
118
119 u_qe_init();
120
121 return 0;
122}
123
124int board_late_init(void)
125{
126 return 0;
127}
128
129int misc_init_r(void)
130{
131 if (IS_ENABLED(CONFIG_FSL_DEVICE_DISABLE))
132 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
133
134 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
135 CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
136
137 return 0;
138}
139
140int ft_board_setup(void *blob, struct bd_info *bd)
141{
142 ft_cpu_setup(blob, bd);
143
144 if (IS_ENABLED(CONFIG_PCI))
145 ft_pci_setup(blob, bd);
146
147 return 0;
148}
149
150#if defined(CONFIG_POST)
151int post_hotkeys_pressed(void)
152{
153
154 qrio_gpio_direction_input(QRIO_GPIO_A, 0);
155 return qrio_get_gpio(QRIO_GPIO_A, 0);
156}
157
158ulong post_word_load(void)
159{
160
161 void *addr = (void *)(CONFIG_SYS_SDRAM_BASE +
162 gd->ram_size - CONFIG_KM_RESERVED_PRAM + 8);
163 return in_le32(addr);
164}
165
166void post_word_store(ulong value)
167{
168
169 void *addr = (void *)(CONFIG_SYS_SDRAM_BASE +
170 gd->ram_size - CONFIG_KM_RESERVED_PRAM + 8);
171 out_le32(addr, value);
172}
173
174int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
175{
176
177
178 *vstart = CONFIG_SYS_SDRAM_BASE + (gd->ram_size >> 1);
179 *size = 1 << 20;
180 return 0;
181}
182#endif
183
184u8 flash_read8(void *addr)
185{
186 return __raw_readb(addr + 1);
187}
188
189void flash_write16(u16 val, void *addr)
190{
191 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
192
193 __raw_writew(shftval, addr);
194}
195
196u16 flash_read16(void *addr)
197{
198 u16 val = __raw_readw(addr);
199
200 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
201}
202
203int hush_init_var(void)
204{
205 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
206 return 0;
207}
208
209int last_stage_init(void)
210{
211 set_km_env();
212 return 0;
213}
214