LXR uboot/board/phytec/phycore

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
   4 * Author: Teresa Remmet <t.remmet@phytec.de>
   5 */
   6
   7#include <common.h>
   8#include <asm/arch/clock.h>
   9#include <asm/arch/ddr.h>
  10#include <asm/arch/imx8mp_pins.h>
  11#include <asm/arch/sys_proto.h>
  12#include <asm/global_data.h>
  13#include <asm/mach-imx/boot_mode.h>
  14#include <asm/mach-imx/gpio.h>
  15#include <asm/mach-imx/mxc_i2c.h>
  16#include <asm/mach-imx/iomux-v3.h>
  17#include <hang.h>
  18#include <init.h>
  19#include <log.h>
  20#include <power/pmic.h>
  21#include <power/pca9450.h>
  22#include <spl.h>
  23
  24DECLARE_GLOBAL_DATA_PTR;
  25
  26int spl_board_boot_device(enum boot_device boot_dev_spl)
  27{
  28        return BOOT_DEVICE_BOOTROM;
  29}
  30
  31void spl_dram_init(void)
  32{
  33        ddr_init(&dram_timing);
  34}
  35
  36#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
  37#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  38struct i2c_pads_info i2c_pad_info1 = {
  39        .scl = {
  40                .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
  41                .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
  42                .gp = IMX_GPIO_NR(5, 14),
  43        },
  44        .sda = {
  45                .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
  46                .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
  47                .gp = IMX_GPIO_NR(5, 15),
  48        },
  49};
  50
  51int power_init_board(void)
  52{
  53        struct pmic *p;
  54        int ret;
  55
  56        ret = power_pca9450_init(0, 0x25);
  57        if (ret)
  58                printf("power init failed");
  59        p = pmic_get("PCA9450");
  60        pmic_probe(p);
  61
  62        /* BUCKxOUT_DVS0/1 control BUCK123 output */
  63        pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
  64
  65        /* increase VDD_SOC to typical value 0.95V */
  66        pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
  67
  68        /* set WDOG_B_CFG to cold reset */
  69        pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
  70
  71        return 0;
  72}
  73
  74int board_fit_config_name_match(const char *name)
  75{
  76        return 0;
  77}
  78
  79#define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  80#define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  81
  82static iomux_v3_cfg_t const uart_pads[] = {
  83        MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  84        MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  85};
  86
  87static iomux_v3_cfg_t const wdog_pads[] = {
  88        MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  89};
  90
  91int board_early_init_f(void)
  92{
  93        struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  94
  95        imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  96
  97        set_wdog_reset(wdog);
  98
  99        imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 100
 101        return 0;
 102}
 103
 104void board_init_f(ulong dummy)
 105{
 106        int ret;
 107
 108        arch_cpu_init();
 109
 110        init_uart_clk(1);
 111
 112        board_early_init_f();
 113
 114        ret = spl_early_init();
 115        if (ret) {
 116                debug("spl_early_init() failed: %d\n", ret);
 117                hang();
 118        }
 119
 120        preloader_console_init();
 121
 122        enable_tzc380();
 123
 124        setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 125
 126        power_init_board();
 127
 128        /* DDR initialization */
 129        spl_dram_init();
 130}
 131