LXR uboot/board/renesas/lager/lager.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * board/renesas/lager/lager.c
   4 *     This file is lager board support.
   5 *
   6 * Copyright (C) 2013 Renesas Electronics Corporation
   7 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   8 */
   9
  10#include <common.h>
  11#include <cpu_func.h>
  12#include <env.h>
  13#include <env_internal.h>
  14#include <hang.h>
  15#include <init.h>
  16#include <malloc.h>
  17#include <netdev.h>
  18#include <dm.h>
  19#include <asm/global_data.h>
  20#include <dm/platform_data/serial_sh.h>
  21#include <asm/processor.h>
  22#include <asm/mach-types.h>
  23#include <asm/io.h>
  24#include <linux/bitops.h>
  25#include <linux/delay.h>
  26#include <linux/errno.h>
  27#include <asm/arch/sys_proto.h>
  28#include <asm/gpio.h>
  29#include <asm/arch/rmobile.h>
  30#include <asm/arch/rcar-mstp.h>
  31#include <asm/arch/mmc.h>
  32#include <asm/arch/sh_sdhi.h>
  33#include <miiphy.h>
  34#include <i2c.h>
  35#include <mmc.h>
  36#include "qos.h"
  37
  38DECLARE_GLOBAL_DATA_PTR;
  39
  40#define CLK2MHZ(clk)    (clk / 1000 / 1000)
  41void s_init(void)
  42{
  43        struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  44        struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  45
  46        /* Watchdog init */
  47        writel(0xA5A5A500, &rwdt->rwtcsra);
  48        writel(0xA5A5A500, &swdt->swtcsra);
  49
  50        /* CPU frequency setting. Set to 1.4GHz */
  51        if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
  52                u32 stat = 0;
  53                u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
  54                        << PLL0_STC_BIT;
  55                clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
  56
  57                do {
  58                        stat = readl(PLLECR) & PLL0ST;
  59                } while (stat == 0x0);
  60        }
  61
  62        /* QoS(Quality-of-Service) Init */
  63        qos_init();
  64}
  65
  66#define TMU0_MSTP125    BIT(25)
  67
  68#define SD1CKCR         0xE6150078
  69#define SD2CKCR         0xE615026C
  70#define SD_97500KHZ     0x7
  71
  72int board_early_init_f(void)
  73{
  74        mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  75
  76        /*
  77         * SD0 clock is set to 97.5MHz by default.
  78         * Set SD1 and SD2 to the 97.5MHz as well.
  79         */
  80        writel(SD_97500KHZ, SD1CKCR);
  81        writel(SD_97500KHZ, SD2CKCR);
  82
  83        return 0;
  84}
  85
  86#define ETHERNET_PHY_RESET      185     /* GPIO 5 31 */
  87
  88int board_init(void)
  89{
  90        /* adress of boot parameters */
  91        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  92
  93        /* Force ethernet PHY out of reset */
  94        gpio_request(ETHERNET_PHY_RESET, "phy_reset");
  95        gpio_direction_output(ETHERNET_PHY_RESET, 0);
  96        mdelay(10);
  97        gpio_direction_output(ETHERNET_PHY_RESET, 1);
  98
  99        return 0;
 100}
 101
 102int dram_init(void)
 103{
 104        if (fdtdec_setup_mem_size_base() != 0)
 105                return -EINVAL;
 106
 107        return 0;
 108}
 109
 110int dram_init_banksize(void)
 111{
 112        fdtdec_setup_memory_banksize();
 113
 114        return 0;
 115}
 116
 117/* KSZ8041NL/RNL */
 118#define PHY_CONTROL1            0x1E
 119#define PHY_LED_MODE            0xC000
 120#define PHY_LED_MODE_ACK        0x4000
 121int board_phy_config(struct phy_device *phydev)
 122{
 123        int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
 124        ret &= ~PHY_LED_MODE;
 125        ret |= PHY_LED_MODE_ACK;
 126        ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
 127
 128        return 0;
 129}
 130
 131void reset_cpu(void)
 132{
 133        struct udevice *dev;
 134        const u8 pmic_bus = 2;
 135        const u8 pmic_addr = 0x58;
 136        u8 data;
 137        int ret;
 138
 139        ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
 140        if (ret)
 141                hang();
 142
 143        ret = dm_i2c_read(dev, 0x13, &data, 1);
 144        if (ret)
 145                hang();
 146
 147        data |= BIT(1);
 148
 149        ret = dm_i2c_write(dev, 0x13, &data, 1);
 150        if (ret)
 151                hang();
 152}
 153
 154enum env_location env_get_location(enum env_operation op, int prio)
 155{
 156        const u32 load_magic = 0xb33fc0de;
 157
 158        /* Block environment access if loaded using JTAG */
 159        if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
 160            (op != ENVOP_INIT))
 161                return ENVL_UNKNOWN;
 162
 163        if (prio)
 164                return ENVL_UNKNOWN;
 165
 166        return ENVL_SPI_FLASH;
 167}
 168