LXR uboot/drivers/crypto/fsl/jr.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
   4 *
   5 */
   6
   7#ifndef __JR_H
   8#define __JR_H
   9
  10#include <linux/compiler.h>
  11#include "type.h"
  12
  13#define JR_SIZE 4
  14/* Timeout currently defined as 10 sec */
  15#define CONFIG_USEC_DEQ_TIMEOUT 10000000U
  16
  17#define DEFAULT_JR_ID           0
  18#define DEFAULT_JR_LIODN        0
  19#define DEFAULT_IRQ             0       /* Interrupts not to be configured */
  20
  21#define MCFGR_SWRST       ((uint32_t)(1)<<31) /* Software Reset */
  22#define MCFGR_DMA_RST     ((uint32_t)(1)<<28) /* DMA Reset */
  23#define MCFGR_PS_SHIFT          16
  24#define MCFGR_AWCACHE_SHIFT     8
  25#define MCFGR_AWCACHE_MASK      (0xf << MCFGR_AWCACHE_SHIFT)
  26#define MCFGR_ARCACHE_SHIFT     12
  27#define MCFGR_ARCACHE_MASK      (0xf << MCFGR_ARCACHE_SHIFT)
  28
  29#define JR_INTMASK        0x00000001
  30#define JRCR_RESET                  0x01
  31#define JRINT_ERR_HALT_INPROGRESS   0x4
  32#define JRINT_ERR_HALT_MASK         0xc
  33#define JRNSLIODN_SHIFT         16
  34#define JRNSLIODN_MASK          0x0fff0000
  35#define JRSLIODN_SHIFT          0
  36#define JRSLIODN_MASK           0x00000fff
  37
  38#define JQ_DEQ_ERR              -1
  39#define JQ_DEQ_TO_ERR           -2
  40#define JQ_ENQ_ERR              -3
  41
  42#define RNG4_MAX_HANDLES        2
  43
  44struct op_ring {
  45        caam_dma_addr_t desc;
  46        uint32_t status;
  47} __packed;
  48
  49struct jr_info {
  50        void (*callback)(uint32_t status, void *arg);
  51        caam_dma_addr_t desc_phys_addr;
  52        uint32_t desc_len;
  53        uint32_t op_done;
  54        void *arg;
  55};
  56
  57struct jobring {
  58        int jq_id;
  59        int irq;
  60        int liodn;
  61        /* Head is the index where software would enq the descriptor in
  62         * the i/p ring
  63         */
  64        int head;
  65        /* Tail index would be used by s/w ehile enqueuing to determine if
  66         * there is any space left in the s/w maintained i/p rings
  67         */
  68        /* Also in case of deq tail will be incremented only in case of
  69         * in-order job completion
  70         */
  71        int tail;
  72        /* Read index of the output ring. It may not match with tail in case
  73         * of out of order completetion
  74         */
  75        int read_idx;
  76        /* Write index to input ring. Would be always equal to head */
  77        int write_idx;
  78        /* Size of the rings. */
  79        int size;
  80        /* Op ring size aligned to cache line size */
  81        int op_size;
  82        /* The ip and output rings have to be accessed by SEC. So the
  83         * pointers will ahve to point to the housekeeping region provided
  84         * by SEC
  85         */
  86        /*Circular  Ring of i/p descriptors */
  87        caam_dma_addr_t *input_ring;
  88        /* Circular Ring of o/p descriptors */
  89        /* Circula Ring containing info regarding descriptors in i/p
  90         * and o/p ring
  91         */
  92        /* This ring can be on the stack */
  93        struct jr_info info[JR_SIZE];
  94        struct op_ring *output_ring;
  95        /* Offset in CCSR to the SEC engine to which this JR belongs */
  96        uint32_t sec_offset;
  97
  98};
  99
 100struct result {
 101        int done;
 102        uint32_t status;
 103};
 104
 105void caam_jr_strstatus(u32 status);
 106int run_descriptor_jr(uint32_t *desc);
 107
 108#endif
 109