uboot/drivers/net/e1000.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/**************************************************************************
   3Intel Pro 1000 for ppcboot/das-u-boot
   4Drivers are port from Intel's Linux driver e1000-4.3.15
   5and from Etherboot pro 1000 driver by mrakes at vivato dot net
   6tested on both gig copper and gig fiber boards
   7***************************************************************************/
   8/*******************************************************************************
   9
  10
  11  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  12
  13
  14  Contact Information:
  15  Linux NICS <linux.nics@intel.com>
  16  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  17
  18*******************************************************************************/
  19/*
  20 *  Copyright (C) Archway Digital Solutions.
  21 *
  22 *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  23 *  2/9/2002
  24 *
  25 *  Copyright (C) Linux Networx.
  26 *  Massive upgrade to work with the new intel gigabit NICs.
  27 *  <ebiederman at lnxi dot com>
  28 *
  29 *  Copyright 2011 Freescale Semiconductor, Inc.
  30 */
  31
  32#include <common.h>
  33#include <command.h>
  34#include <cpu_func.h>
  35#include <dm.h>
  36#include <errno.h>
  37#include <log.h>
  38#include <malloc.h>
  39#include <memalign.h>
  40#include <net.h>
  41#include <pci.h>
  42#include <linux/delay.h>
  43#include "e1000.h"
  44#include <asm/cache.h>
  45
  46#define TOUT_LOOP   100000
  47
  48#define E1000_DEFAULT_PCI_PBA   0x00000030
  49#define E1000_DEFAULT_PCIE_PBA  0x000a0026
  50
  51/* NIC specific static variables go here */
  52
  53/* Intel i210 needs the DMA descriptor rings aligned to 128b */
  54#define E1000_BUFFER_ALIGN      128
  55
  56/*
  57 * TODO(sjg@chromium.org): Even with driver model we share these buffers.
  58 * Concurrent receiving on multiple active Ethernet devices will not work.
  59 * Normally U-Boot does not support this anyway. To fix it in this driver,
  60 * move these buffers and the tx/rx pointers to struct e1000_hw.
  61 */
  62DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
  63DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
  64DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
  65
  66static int tx_tail;
  67static int rx_tail, rx_last;
  68#ifdef CONFIG_DM_ETH
  69static int num_cards;   /* Number of E1000 devices seen so far */
  70#endif
  71
  72static struct pci_device_id e1000_supported[] = {
  73        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
  74        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) },
  75        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) },
  76        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) },
  77        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) },
  78        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) },
  79        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) },
  80        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) },
  81        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) },
  82        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) },
  83        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) },
  84        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) },
  85        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) },
  86        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) },
  87        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) },
  88        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) },
  89        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) },
  90        /* E1000 PCIe card */
  91        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) },
  92        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) },
  93        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) },
  94        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) },
  95        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) },
  96        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) },
  97        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) },
  98        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) },
  99        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) },
 100        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) },
 101        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) },
 102        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) },
 103        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) },
 104        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) },
 105        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) },
 106        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) },
 107        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) },
 108        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) },
 109        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) },
 110        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
 111        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
 112        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
 113        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
 114        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
 115        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
 116        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) },
 117        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) },
 118        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
 119        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
 120        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
 121
 122        {}
 123};
 124
 125/* Function forward declarations */
 126static int e1000_setup_link(struct e1000_hw *hw);
 127static int e1000_setup_fiber_link(struct e1000_hw *hw);
 128static int e1000_setup_copper_link(struct e1000_hw *hw);
 129static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
 130static void e1000_config_collision_dist(struct e1000_hw *hw);
 131static int e1000_config_mac_to_phy(struct e1000_hw *hw);
 132static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
 133static int e1000_check_for_link(struct e1000_hw *hw);
 134static int e1000_wait_autoneg(struct e1000_hw *hw);
 135static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
 136                                       uint16_t * duplex);
 137static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 138                              uint16_t * phy_data);
 139static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 140                               uint16_t phy_data);
 141static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
 142static int e1000_phy_reset(struct e1000_hw *hw);
 143static int e1000_detect_gig_phy(struct e1000_hw *hw);
 144static void e1000_set_media_type(struct e1000_hw *hw);
 145
 146static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
 147static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
 148static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
 149
 150#ifndef CONFIG_E1000_NO_NVM
 151static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
 152static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
 153static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 154                uint16_t words,
 155                uint16_t *data);
 156/******************************************************************************
 157 * Raises the EEPROM's clock input.
 158 *
 159 * hw - Struct containing variables accessed by shared code
 160 * eecd - EECD's current value
 161 *****************************************************************************/
 162void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 163{
 164        /* Raise the clock input to the EEPROM (by setting the SK bit), and then
 165         * wait 50 microseconds.
 166         */
 167        *eecd = *eecd | E1000_EECD_SK;
 168        E1000_WRITE_REG(hw, EECD, *eecd);
 169        E1000_WRITE_FLUSH(hw);
 170        udelay(50);
 171}
 172
 173/******************************************************************************
 174 * Lowers the EEPROM's clock input.
 175 *
 176 * hw - Struct containing variables accessed by shared code
 177 * eecd - EECD's current value
 178 *****************************************************************************/
 179void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 180{
 181        /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
 182         * wait 50 microseconds.
 183         */
 184        *eecd = *eecd & ~E1000_EECD_SK;
 185        E1000_WRITE_REG(hw, EECD, *eecd);
 186        E1000_WRITE_FLUSH(hw);
 187        udelay(50);
 188}
 189
 190/******************************************************************************
 191 * Shift data bits out to the EEPROM.
 192 *
 193 * hw - Struct containing variables accessed by shared code
 194 * data - data to send to the EEPROM
 195 * count - number of bits to shift out
 196 *****************************************************************************/
 197static void
 198e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
 199{
 200        uint32_t eecd;
 201        uint32_t mask;
 202
 203        /* We need to shift "count" bits out to the EEPROM. So, value in the
 204         * "data" parameter will be shifted out to the EEPROM one bit at a time.
 205         * In order to do this, "data" must be broken down into bits.
 206         */
 207        mask = 0x01 << (count - 1);
 208        eecd = E1000_READ_REG(hw, EECD);
 209        eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 210        do {
 211                /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
 212                 * and then raising and then lowering the clock (the SK bit controls
 213                 * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
 214                 * by setting "DI" to "0" and then raising and then lowering the clock.
 215                 */
 216                eecd &= ~E1000_EECD_DI;
 217
 218                if (data & mask)
 219                        eecd |= E1000_EECD_DI;
 220
 221                E1000_WRITE_REG(hw, EECD, eecd);
 222                E1000_WRITE_FLUSH(hw);
 223
 224                udelay(50);
 225
 226                e1000_raise_ee_clk(hw, &eecd);
 227                e1000_lower_ee_clk(hw, &eecd);
 228
 229                mask = mask >> 1;
 230
 231        } while (mask);
 232
 233        /* We leave the "DI" bit set to "0" when we leave this routine. */
 234        eecd &= ~E1000_EECD_DI;
 235        E1000_WRITE_REG(hw, EECD, eecd);
 236}
 237
 238/******************************************************************************
 239 * Shift data bits in from the EEPROM
 240 *
 241 * hw - Struct containing variables accessed by shared code
 242 *****************************************************************************/
 243static uint16_t
 244e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
 245{
 246        uint32_t eecd;
 247        uint32_t i;
 248        uint16_t data;
 249
 250        /* In order to read a register from the EEPROM, we need to shift 'count'
 251         * bits in from the EEPROM. Bits are "shifted in" by raising the clock
 252         * input to the EEPROM (setting the SK bit), and then reading the
 253         * value of the "DO" bit.  During this "shifting in" process the
 254         * "DI" bit should always be clear.
 255         */
 256
 257        eecd = E1000_READ_REG(hw, EECD);
 258
 259        eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 260        data = 0;
 261
 262        for (i = 0; i < count; i++) {
 263                data = data << 1;
 264                e1000_raise_ee_clk(hw, &eecd);
 265
 266                eecd = E1000_READ_REG(hw, EECD);
 267
 268                eecd &= ~(E1000_EECD_DI);
 269                if (eecd & E1000_EECD_DO)
 270                        data |= 1;
 271
 272                e1000_lower_ee_clk(hw, &eecd);
 273        }
 274
 275        return data;
 276}
 277
 278/******************************************************************************
 279 * Returns EEPROM to a "standby" state
 280 *
 281 * hw - Struct containing variables accessed by shared code
 282 *****************************************************************************/
 283void e1000_standby_eeprom(struct e1000_hw *hw)
 284{
 285        struct e1000_eeprom_info *eeprom = &hw->eeprom;
 286        uint32_t eecd;
 287
 288        eecd = E1000_READ_REG(hw, EECD);
 289
 290        if (eeprom->type == e1000_eeprom_microwire) {
 291                eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 292                E1000_WRITE_REG(hw, EECD, eecd);
 293                E1000_WRITE_FLUSH(hw);
 294                udelay(eeprom->delay_usec);
 295
 296                /* Clock high */
 297                eecd |= E1000_EECD_SK;
 298                E1000_WRITE_REG(hw, EECD, eecd);
 299                E1000_WRITE_FLUSH(hw);
 300                udelay(eeprom->delay_usec);
 301
 302                /* Select EEPROM */
 303                eecd |= E1000_EECD_CS;
 304                E1000_WRITE_REG(hw, EECD, eecd);
 305                E1000_WRITE_FLUSH(hw);
 306                udelay(eeprom->delay_usec);
 307
 308                /* Clock low */
 309                eecd &= ~E1000_EECD_SK;
 310                E1000_WRITE_REG(hw, EECD, eecd);
 311                E1000_WRITE_FLUSH(hw);
 312                udelay(eeprom->delay_usec);
 313        } else if (eeprom->type == e1000_eeprom_spi) {
 314                /* Toggle CS to flush commands */
 315                eecd |= E1000_EECD_CS;
 316                E1000_WRITE_REG(hw, EECD, eecd);
 317                E1000_WRITE_FLUSH(hw);
 318                udelay(eeprom->delay_usec);
 319                eecd &= ~E1000_EECD_CS;
 320                E1000_WRITE_REG(hw, EECD, eecd);
 321                E1000_WRITE_FLUSH(hw);
 322                udelay(eeprom->delay_usec);
 323        }
 324}
 325
 326/***************************************************************************
 327* Description:     Determines if the onboard NVM is FLASH or EEPROM.
 328*
 329* hw - Struct containing variables accessed by shared code
 330****************************************************************************/
 331static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
 332{
 333        uint32_t eecd = 0;
 334
 335        DEBUGFUNC();
 336
 337        if (hw->mac_type == e1000_ich8lan)
 338                return false;
 339
 340        if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
 341                eecd = E1000_READ_REG(hw, EECD);
 342
 343                /* Isolate bits 15 & 16 */
 344                eecd = ((eecd >> 15) & 0x03);
 345
 346                /* If both bits are set, device is Flash type */
 347                if (eecd == 0x03)
 348                        return false;
 349        }
 350        return true;
 351}
 352
 353/******************************************************************************
 354 * Prepares EEPROM for access
 355 *
 356 * hw - Struct containing variables accessed by shared code
 357 *
 358 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
 359 * function should be called before issuing a command to the EEPROM.
 360 *****************************************************************************/
 361int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
 362{
 363        struct e1000_eeprom_info *eeprom = &hw->eeprom;
 364        uint32_t eecd, i = 0;
 365
 366        DEBUGFUNC();
 367
 368        if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
 369                return -E1000_ERR_SWFW_SYNC;
 370        eecd = E1000_READ_REG(hw, EECD);
 371
 372        if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
 373                /* Request EEPROM Access */
 374                if (hw->mac_type > e1000_82544) {
 375                        eecd |= E1000_EECD_REQ;
 376                        E1000_WRITE_REG(hw, EECD, eecd);
 377                        eecd = E1000_READ_REG(hw, EECD);
 378                        while ((!(eecd & E1000_EECD_GNT)) &&
 379                                (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
 380                                i++;
 381                                udelay(5);
 382                                eecd = E1000_READ_REG(hw, EECD);
 383                        }
 384                        if (!(eecd & E1000_EECD_GNT)) {
 385                                eecd &= ~E1000_EECD_REQ;
 386                                E1000_WRITE_REG(hw, EECD, eecd);
 387                                DEBUGOUT("Could not acquire EEPROM grant\n");
 388                                return -E1000_ERR_EEPROM;
 389                        }
 390                }
 391        }
 392
 393        /* Setup EEPROM for Read/Write */
 394
 395        if (eeprom->type == e1000_eeprom_microwire) {
 396                /* Clear SK and DI */
 397                eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 398                E1000_WRITE_REG(hw, EECD, eecd);
 399
 400                /* Set CS */
 401                eecd |= E1000_EECD_CS;
 402                E1000_WRITE_REG(hw, EECD, eecd);
 403        } else if (eeprom->type == e1000_eeprom_spi) {
 404                /* Clear SK and CS */
 405                eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 406                E1000_WRITE_REG(hw, EECD, eecd);
 407                udelay(1);
 408        }
 409
 410        return E1000_SUCCESS;
 411}
 412
 413/******************************************************************************
 414 * Sets up eeprom variables in the hw struct.  Must be called after mac_type
 415 * is configured.  Additionally, if this is ICH8, the flash controller GbE
 416 * registers must be mapped, or this will crash.
 417 *
 418 * hw - Struct containing variables accessed by shared code
 419 *****************************************************************************/
 420static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 421{
 422        struct e1000_eeprom_info *eeprom = &hw->eeprom;
 423        uint32_t eecd;
 424        int32_t ret_val = E1000_SUCCESS;
 425        uint16_t eeprom_size;
 426
 427        if (hw->mac_type == e1000_igb)
 428                eecd = E1000_READ_REG(hw, I210_EECD);
 429        else
 430                eecd = E1000_READ_REG(hw, EECD);
 431
 432        DEBUGFUNC();
 433
 434        switch (hw->mac_type) {
 435        case e1000_82542_rev2_0:
 436        case e1000_82542_rev2_1:
 437        case e1000_82543:
 438        case e1000_82544:
 439                eeprom->type = e1000_eeprom_microwire;
 440                eeprom->word_size = 64;
 441                eeprom->opcode_bits = 3;
 442                eeprom->address_bits = 6;
 443                eeprom->delay_usec = 50;
 444                eeprom->use_eerd = false;
 445                eeprom->use_eewr = false;
 446        break;
 447        case e1000_82540:
 448        case e1000_82545:
 449        case e1000_82545_rev_3:
 450        case e1000_82546:
 451        case e1000_82546_rev_3:
 452                eeprom->type = e1000_eeprom_microwire;
 453                eeprom->opcode_bits = 3;
 454                eeprom->delay_usec = 50;
 455                if (eecd & E1000_EECD_SIZE) {
 456                        eeprom->word_size = 256;
 457                        eeprom->address_bits = 8;
 458                } else {
 459                        eeprom->word_size = 64;
 460                        eeprom->address_bits = 6;
 461                }
 462                eeprom->use_eerd = false;
 463                eeprom->use_eewr = false;
 464                break;
 465        case e1000_82541:
 466        case e1000_82541_rev_2:
 467        case e1000_82547:
 468        case e1000_82547_rev_2:
 469                if (eecd & E1000_EECD_TYPE) {
 470                        eeprom->type = e1000_eeprom_spi;
 471                        eeprom->opcode_bits = 8;
 472                        eeprom->delay_usec = 1;
 473                        if (eecd & E1000_EECD_ADDR_BITS) {
 474                                eeprom->page_size = 32;
 475                                eeprom->address_bits = 16;
 476                        } else {
 477                                eeprom->page_size = 8;
 478                                eeprom->address_bits = 8;
 479                        }
 480                } else {
 481                        eeprom->type = e1000_eeprom_microwire;
 482                        eeprom->opcode_bits = 3;
 483                        eeprom->delay_usec = 50;
 484                        if (eecd & E1000_EECD_ADDR_BITS) {
 485                                eeprom->word_size = 256;
 486                                eeprom->address_bits = 8;
 487                        } else {
 488                                eeprom->word_size = 64;
 489                                eeprom->address_bits = 6;
 490                        }
 491                }
 492                eeprom->use_eerd = false;
 493                eeprom->use_eewr = false;
 494                break;
 495        case e1000_82571:
 496        case e1000_82572:
 497                eeprom->type = e1000_eeprom_spi;
 498                eeprom->opcode_bits = 8;
 499                eeprom->delay_usec = 1;
 500                if (eecd & E1000_EECD_ADDR_BITS) {
 501                        eeprom->page_size = 32;
 502                        eeprom->address_bits = 16;
 503                } else {
 504                        eeprom->page_size = 8;
 505                        eeprom->address_bits = 8;
 506                }
 507                eeprom->use_eerd = false;
 508                eeprom->use_eewr = false;
 509                break;
 510        case e1000_82573:
 511        case e1000_82574:
 512                eeprom->type = e1000_eeprom_spi;
 513                eeprom->opcode_bits = 8;
 514                eeprom->delay_usec = 1;
 515                if (eecd & E1000_EECD_ADDR_BITS) {
 516                        eeprom->page_size = 32;
 517                        eeprom->address_bits = 16;
 518                } else {
 519                        eeprom->page_size = 8;
 520                        eeprom->address_bits = 8;
 521                }
 522                if (e1000_is_onboard_nvm_eeprom(hw) == false) {
 523                        eeprom->use_eerd = true;
 524                        eeprom->use_eewr = true;
 525
 526                        eeprom->type = e1000_eeprom_flash;
 527                        eeprom->word_size = 2048;
 528
 529                /* Ensure that the Autonomous FLASH update bit is cleared due to
 530                 * Flash update issue on parts which use a FLASH for NVM. */
 531                        eecd &= ~E1000_EECD_AUPDEN;
 532                        E1000_WRITE_REG(hw, EECD, eecd);
 533                }
 534                break;
 535        case e1000_80003es2lan:
 536                eeprom->type = e1000_eeprom_spi;
 537                eeprom->opcode_bits = 8;
 538                eeprom->delay_usec = 1;
 539                if (eecd & E1000_EECD_ADDR_BITS) {
 540                        eeprom->page_size = 32;
 541                        eeprom->address_bits = 16;
 542                } else {
 543                        eeprom->page_size = 8;
 544                        eeprom->address_bits = 8;
 545                }
 546                eeprom->use_eerd = true;
 547                eeprom->use_eewr = false;
 548                break;
 549        case e1000_igb:
 550                /* i210 has 4k of iNVM mapped as EEPROM */
 551                eeprom->type = e1000_eeprom_invm;
 552                eeprom->opcode_bits = 8;
 553                eeprom->delay_usec = 1;
 554                eeprom->page_size = 32;
 555                eeprom->address_bits = 16;
 556                eeprom->use_eerd = true;
 557                eeprom->use_eewr = false;
 558                break;
 559        default:
 560                break;
 561        }
 562
 563        if (eeprom->type == e1000_eeprom_spi ||
 564            eeprom->type == e1000_eeprom_invm) {
 565                /* eeprom_size will be an enum [0..8] that maps
 566                 * to eeprom sizes 128B to
 567                 * 32KB (incremented by powers of 2).
 568                 */
 569                if (hw->mac_type <= e1000_82547_rev_2) {
 570                        /* Set to default value for initial eeprom read. */
 571                        eeprom->word_size = 64;
 572                        ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
 573                                        &eeprom_size);
 574                        if (ret_val)
 575                                return ret_val;
 576                        eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
 577                                >> EEPROM_SIZE_SHIFT;
 578                        /* 256B eeprom size was not supported in earlier
 579                         * hardware, so we bump eeprom_size up one to
 580                         * ensure that "1" (which maps to 256B) is never
 581                         * the result used in the shifting logic below. */
 582                        if (eeprom_size)
 583                                eeprom_size++;
 584                } else {
 585                        eeprom_size = (uint16_t)((eecd &
 586                                E1000_EECD_SIZE_EX_MASK) >>
 587                                E1000_EECD_SIZE_EX_SHIFT);
 588                }
 589
 590                eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
 591        }
 592        return ret_val;
 593}
 594
 595/******************************************************************************
 596 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
 597 *
 598 * hw - Struct containing variables accessed by shared code
 599 *****************************************************************************/
 600static int32_t
 601e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
 602{
 603        uint32_t attempts = 100000;
 604        uint32_t i, reg = 0;
 605        int32_t done = E1000_ERR_EEPROM;
 606
 607        for (i = 0; i < attempts; i++) {
 608                if (eerd == E1000_EEPROM_POLL_READ) {
 609                        if (hw->mac_type == e1000_igb)
 610                                reg = E1000_READ_REG(hw, I210_EERD);
 611                        else
 612                                reg = E1000_READ_REG(hw, EERD);
 613                } else {
 614                        if (hw->mac_type == e1000_igb)
 615                                reg = E1000_READ_REG(hw, I210_EEWR);
 616                        else
 617                                reg = E1000_READ_REG(hw, EEWR);
 618                }
 619
 620                if (reg & E1000_EEPROM_RW_REG_DONE) {
 621                        done = E1000_SUCCESS;
 622                        break;
 623                }
 624                udelay(5);
 625        }
 626
 627        return done;
 628}
 629
 630/******************************************************************************
 631 * Reads a 16 bit word from the EEPROM using the EERD register.
 632 *
 633 * hw - Struct containing variables accessed by shared code
 634 * offset - offset of  word in the EEPROM to read
 635 * data - word read from the EEPROM
 636 * words - number of words to read
 637 *****************************************************************************/
 638static int32_t
 639e1000_read_eeprom_eerd(struct e1000_hw *hw,
 640                        uint16_t offset,
 641                        uint16_t words,
 642                        uint16_t *data)
 643{
 644        uint32_t i, eerd = 0;
 645        int32_t error = 0;
 646
 647        for (i = 0; i < words; i++) {
 648                eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
 649                        E1000_EEPROM_RW_REG_START;
 650
 651                if (hw->mac_type == e1000_igb)
 652                        E1000_WRITE_REG(hw, I210_EERD, eerd);
 653                else
 654                        E1000_WRITE_REG(hw, EERD, eerd);
 655
 656                error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
 657
 658                if (error)
 659                        break;
 660
 661                if (hw->mac_type == e1000_igb) {
 662                        data[i] = (E1000_READ_REG(hw, I210_EERD) >>
 663                                E1000_EEPROM_RW_REG_DATA);
 664                } else {
 665                        data[i] = (E1000_READ_REG(hw, EERD) >>
 666                                E1000_EEPROM_RW_REG_DATA);
 667                }
 668
 669        }
 670
 671        return error;
 672}
 673
 674void e1000_release_eeprom(struct e1000_hw *hw)
 675{
 676        uint32_t eecd;
 677
 678        DEBUGFUNC();
 679
 680        eecd = E1000_READ_REG(hw, EECD);
 681
 682        if (hw->eeprom.type == e1000_eeprom_spi) {
 683                eecd |= E1000_EECD_CS;  /* Pull CS high */
 684                eecd &= ~E1000_EECD_SK; /* Lower SCK */
 685
 686                E1000_WRITE_REG(hw, EECD, eecd);
 687
 688                udelay(hw->eeprom.delay_usec);
 689        } else if (hw->eeprom.type == e1000_eeprom_microwire) {
 690                /* cleanup eeprom */
 691
 692                /* CS on Microwire is active-high */
 693                eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 694
 695                E1000_WRITE_REG(hw, EECD, eecd);
 696
 697                /* Rising edge of clock */
 698                eecd |= E1000_EECD_SK;
 699                E1000_WRITE_REG(hw, EECD, eecd);
 700                E1000_WRITE_FLUSH(hw);
 701                udelay(hw->eeprom.delay_usec);
 702
 703                /* Falling edge of clock */
 704                eecd &= ~E1000_EECD_SK;
 705                E1000_WRITE_REG(hw, EECD, eecd);
 706                E1000_WRITE_FLUSH(hw);
 707                udelay(hw->eeprom.delay_usec);
 708        }
 709
 710        /* Stop requesting EEPROM access */
 711        if (hw->mac_type > e1000_82544) {
 712                eecd &= ~E1000_EECD_REQ;
 713                E1000_WRITE_REG(hw, EECD, eecd);
 714        }
 715
 716        e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
 717}
 718
 719/******************************************************************************
 720 * Reads a 16 bit word from the EEPROM.
 721 *
 722 * hw - Struct containing variables accessed by shared code
 723 *****************************************************************************/
 724static int32_t
 725e1000_spi_eeprom_ready(struct e1000_hw *hw)
 726{
 727        uint16_t retry_count = 0;
 728        uint8_t spi_stat_reg;
 729
 730        DEBUGFUNC();
 731
 732        /* Read "Status Register" repeatedly until the LSB is cleared.  The
 733         * EEPROM will signal that the command has been completed by clearing
 734         * bit 0 of the internal status register.  If it's not cleared within
 735         * 5 milliseconds, then error out.
 736         */
 737        retry_count = 0;
 738        do {
 739                e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
 740                        hw->eeprom.opcode_bits);
 741                spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
 742                if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
 743                        break;
 744
 745                udelay(5);
 746                retry_count += 5;
 747
 748                e1000_standby_eeprom(hw);
 749        } while (retry_count < EEPROM_MAX_RETRY_SPI);
 750
 751        /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
 752         * only 0-5mSec on 5V devices)
 753         */
 754        if (retry_count >= EEPROM_MAX_RETRY_SPI) {
 755                DEBUGOUT("SPI EEPROM Status error\n");
 756                return -E1000_ERR_EEPROM;
 757        }
 758
 759        return E1000_SUCCESS;
 760}
 761
 762/******************************************************************************
 763 * Reads a 16 bit word from the EEPROM.
 764 *
 765 * hw - Struct containing variables accessed by shared code
 766 * offset - offset of  word in the EEPROM to read
 767 * data - word read from the EEPROM
 768 *****************************************************************************/
 769static int32_t
 770e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 771                uint16_t words, uint16_t *data)
 772{
 773        struct e1000_eeprom_info *eeprom = &hw->eeprom;
 774        uint32_t i = 0;
 775
 776        DEBUGFUNC();
 777
 778        /* If eeprom is not yet detected, do so now */
 779        if (eeprom->word_size == 0)
 780                e1000_init_eeprom_params(hw);
 781
 782        /* A check for invalid values:  offset too large, too many words,
 783         * and not enough words.
 784         */
 785        if ((offset >= eeprom->word_size) ||
 786                (words > eeprom->word_size - offset) ||
 787                (words == 0)) {
 788                DEBUGOUT("\"words\" parameter out of bounds."
 789                        "Words = %d, size = %d\n", offset, eeprom->word_size);
 790                return -E1000_ERR_EEPROM;
 791        }
 792
 793        /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
 794         * directly. In this case, we need to acquire the EEPROM so that
 795         * FW or other port software does not interrupt.
 796         */
 797        if (e1000_is_onboard_nvm_eeprom(hw) == true &&
 798                hw->eeprom.use_eerd == false) {
 799
 800                /* Prepare the EEPROM for bit-bang reading */
 801                if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
 802                        return -E1000_ERR_EEPROM;
 803        }
 804
 805        /* Eerd register EEPROM access requires no eeprom aquire/release */
 806        if (eeprom->use_eerd == true)
 807                return e1000_read_eeprom_eerd(hw, offset, words, data);
 808
 809        /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
 810         * acquired the EEPROM at this point, so any returns should relase it */
 811        if (eeprom->type == e1000_eeprom_spi) {
 812                uint16_t word_in;
 813                uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
 814
 815                if (e1000_spi_eeprom_ready(hw)) {
 816                        e1000_release_eeprom(hw);
 817                        return -E1000_ERR_EEPROM;
 818                }
 819
 820                e1000_standby_eeprom(hw);
 821
 822                /* Some SPI eeproms use the 8th address bit embedded in
 823                 * the opcode */
 824                if ((eeprom->address_bits == 8) && (offset >= 128))
 825                        read_opcode |= EEPROM_A8_OPCODE_SPI;
 826
 827                /* Send the READ command (opcode + addr)  */
 828                e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
 829                e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
 830                                eeprom->address_bits);
 831
 832                /* Read the data.  The address of the eeprom internally
 833                 * increments with each byte (spi) being read, saving on the
 834                 * overhead of eeprom setup and tear-down.  The address
 835                 * counter will roll over if reading beyond the size of
 836                 * the eeprom, thus allowing the entire memory to be read
 837                 * starting from any offset. */
 838                for (i = 0; i < words; i++) {
 839                        word_in = e1000_shift_in_ee_bits(hw, 16);
 840                        data[i] = (word_in >> 8) | (word_in << 8);
 841                }
 842        } else if (eeprom->type == e1000_eeprom_microwire) {
 843                for (i = 0; i < words; i++) {
 844                        /* Send the READ command (opcode + addr)  */
 845                        e1000_shift_out_ee_bits(hw,
 846                                EEPROM_READ_OPCODE_MICROWIRE,
 847                                eeprom->opcode_bits);
 848                        e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
 849                                eeprom->address_bits);
 850
 851                        /* Read the data.  For microwire, each word requires
 852                         * the overhead of eeprom setup and tear-down. */
 853                        data[i] = e1000_shift_in_ee_bits(hw, 16);
 854                        e1000_standby_eeprom(hw);
 855                }
 856        }
 857
 858        /* End this read operation */
 859        e1000_release_eeprom(hw);
 860
 861        return E1000_SUCCESS;
 862}
 863
 864/******************************************************************************
 865 *  e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR
 866 *  @hw: pointer to the HW structure
 867 *  @offset: offset within the Shadow Ram to be written to
 868 *  @words: number of words to write
 869 *  @data: 16 bit word(s) to be written to the Shadow Ram
 870 *
 871 *  Writes data to Shadow Ram at offset using EEWR register.
 872 *
 873 *  If e1000_update_eeprom_checksum_i210 is not called after this function, the
 874 *  Shadow Ram will most likely contain an invalid checksum.
 875 *****************************************************************************/
 876static int32_t e1000_write_eeprom_srwr(struct e1000_hw *hw, uint16_t offset,
 877                                       uint16_t words, uint16_t *data)
 878{
 879        struct e1000_eeprom_info *eeprom = &hw->eeprom;
 880        uint32_t i, k, eewr = 0;
 881        uint32_t attempts = 100000;
 882        int32_t ret_val = 0;
 883
 884        /* A check for invalid values:  offset too large, too many words,
 885         * too many words for the offset, and not enough words.
 886         */
 887        if ((offset >= eeprom->word_size) ||
 888            (words > (eeprom->word_size - offset)) || (words == 0)) {
 889                DEBUGOUT("nvm parameter(s) out of bounds\n");
 890                ret_val = -E1000_ERR_EEPROM;
 891                goto out;
 892        }
 893
 894        for (i = 0; i < words; i++) {
 895                eewr = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT)
 896                                | (data[i] << E1000_EEPROM_RW_REG_DATA) |
 897                                E1000_EEPROM_RW_REG_START;
 898
 899                E1000_WRITE_REG(hw, I210_EEWR, eewr);
 900
 901                for (k = 0; k < attempts; k++) {
 902                        if (E1000_EEPROM_RW_REG_DONE &
 903                            E1000_READ_REG(hw, I210_EEWR)) {
 904                                ret_val = 0;
 905                                break;
 906                        }
 907                        udelay(5);
 908                }
 909
 910                if (ret_val) {
 911                        DEBUGOUT("Shadow RAM write EEWR timed out\n");
 912                        break;
 913                }
 914        }
 915
 916out:
 917        return ret_val;
 918}
 919
 920/******************************************************************************
 921 *  e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
 922 *  @hw: pointer to the HW structure
 923 *
 924 *****************************************************************************/
 925static int32_t e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
 926{
 927        int32_t ret_val = -E1000_ERR_EEPROM;
 928        uint32_t i, reg;
 929
 930        for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
 931                reg = E1000_READ_REG(hw, EECD);
 932                if (reg & E1000_EECD_FLUDONE_I210) {
 933                        ret_val = 0;
 934                        break;
 935                }
 936                udelay(5);
 937        }
 938
 939        return ret_val;
 940}
 941
 942/******************************************************************************
 943 *  e1000_update_flash_i210 - Commit EEPROM to the flash
 944 *  @hw: pointer to the HW structure
 945 *
 946 *****************************************************************************/
 947static int32_t e1000_update_flash_i210(struct e1000_hw *hw)
 948{
 949        int32_t ret_val = 0;
 950        uint32_t flup;
 951
 952        ret_val = e1000_pool_flash_update_done_i210(hw);
 953        if (ret_val == -E1000_ERR_EEPROM) {
 954                DEBUGOUT("Flash update time out\n");
 955                goto out;
 956        }
 957
 958        flup = E1000_READ_REG(hw, EECD) | E1000_EECD_FLUPD_I210;
 959        E1000_WRITE_REG(hw, EECD, flup);
 960
 961        ret_val = e1000_pool_flash_update_done_i210(hw);
 962        if (ret_val)
 963                DEBUGOUT("Flash update time out\n");
 964        else
 965                DEBUGOUT("Flash update complete\n");
 966
 967out:
 968        return ret_val;
 969}
 970
 971/******************************************************************************
 972 *  e1000_update_eeprom_checksum_i210 - Update EEPROM checksum
 973 *  @hw: pointer to the HW structure
 974 *
 975 *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 976 *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 977 *  value to the EEPROM. Next commit EEPROM data onto the Flash.
 978 *****************************************************************************/
 979static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw)
 980{
 981        int32_t ret_val = 0;
 982        uint16_t checksum = 0;
 983        uint16_t i, nvm_data;
 984
 985        /* Read the first word from the EEPROM. If this times out or fails, do
 986         * not continue or we could be in for a very long wait while every
 987         * EEPROM read fails
 988         */
 989        ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data);
 990        if (ret_val) {
 991                DEBUGOUT("EEPROM read failed\n");
 992                goto out;
 993        }
 994
 995        if (!(e1000_get_hw_eeprom_semaphore(hw))) {
 996                /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
 997                 * because we do not want to take the synchronization
 998                 * semaphores twice here.
 999                 */
1000
1001                for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
1002                        ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data);
1003                        if (ret_val) {
1004                                e1000_put_hw_eeprom_semaphore(hw);
1005                                DEBUGOUT("EEPROM Read Error while updating checksum.\n");
1006                                goto out;
1007                        }
1008                        checksum += nvm_data;
1009                }
1010                checksum = (uint16_t)EEPROM_SUM - checksum;
1011                ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1,
1012                                                  &checksum);
1013                if (ret_val) {
1014                        e1000_put_hw_eeprom_semaphore(hw);
1015                        DEBUGOUT("EEPROM Write Error while updating checksum.\n");
1016                        goto out;
1017                }
1018
1019                e1000_put_hw_eeprom_semaphore(hw);
1020
1021                ret_val = e1000_update_flash_i210(hw);
1022        } else {
1023                ret_val = -E1000_ERR_SWFW_SYNC;
1024        }
1025
1026out:
1027        return ret_val;
1028}
1029
1030/******************************************************************************
1031 * Verifies that the EEPROM has a valid checksum
1032 *
1033 * hw - Struct containing variables accessed by shared code
1034 *
1035 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
1036 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
1037 * valid.
1038 *****************************************************************************/
1039static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
1040{
1041        uint16_t i, checksum, checksum_reg, *buf;
1042
1043        DEBUGFUNC();
1044
1045        /* Allocate a temporary buffer */
1046        buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
1047        if (!buf) {
1048                E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n");
1049                return -E1000_ERR_EEPROM;
1050        }
1051
1052        /* Read the EEPROM */
1053        if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
1054                E1000_ERR(hw, "Unable to read EEPROM!\n");
1055                return -E1000_ERR_EEPROM;
1056        }
1057
1058        /* Compute the checksum */
1059        checksum = 0;
1060        for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1061                checksum += buf[i];
1062        checksum = ((uint16_t)EEPROM_SUM) - checksum;
1063        checksum_reg = buf[i];
1064
1065        /* Verify it! */
1066        if (checksum == checksum_reg)
1067                return 0;
1068
1069        /* Hrm, verification failed, print an error */
1070        E1000_ERR(hw, "EEPROM checksum is incorrect!\n");
1071        E1000_ERR(hw, "  ...register was 0x%04hx, calculated 0x%04hx\n",
1072                  checksum_reg, checksum);
1073
1074        return -E1000_ERR_EEPROM;
1075}
1076#endif /* CONFIG_E1000_NO_NVM */
1077
1078/*****************************************************************************
1079 * Set PHY to class A mode
1080 * Assumes the following operations will follow to enable the new class mode.
1081 *  1. Do a PHY soft reset
1082 *  2. Restart auto-negotiation or force link.
1083 *
1084 * hw - Struct containing variables accessed by shared code
1085 ****************************************************************************/
1086static int32_t
1087e1000_set_phy_mode(struct e1000_hw *hw)
1088{
1089#ifndef CONFIG_E1000_NO_NVM
1090        int32_t ret_val;
1091        uint16_t eeprom_data;
1092
1093        DEBUGFUNC();
1094
1095        if ((hw->mac_type == e1000_82545_rev_3) &&
1096                (hw->media_type == e1000_media_type_copper)) {
1097                ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
1098                                1, &eeprom_data);
1099                if (ret_val)
1100                        return ret_val;
1101
1102                if ((eeprom_data != EEPROM_RESERVED_WORD) &&
1103                        (eeprom_data & EEPROM_PHY_CLASS_A)) {
1104                        ret_val = e1000_write_phy_reg(hw,
1105                                        M88E1000_PHY_PAGE_SELECT, 0x000B);
1106                        if (ret_val)
1107                                return ret_val;
1108                        ret_val = e1000_write_phy_reg(hw,
1109                                        M88E1000_PHY_GEN_CONTROL, 0x8104);
1110                        if (ret_val)
1111                                return ret_val;
1112
1113                        hw->phy_reset_disable = false;
1114                }
1115        }
1116#endif
1117        return E1000_SUCCESS;
1118}
1119
1120#ifndef CONFIG_E1000_NO_NVM
1121/***************************************************************************
1122 *
1123 * Obtaining software semaphore bit (SMBI) before resetting PHY.
1124 *
1125 * hw: Struct containing variables accessed by shared code
1126 *
1127 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
1128 *            E1000_SUCCESS at any other case.
1129 *
1130 ***************************************************************************/
1131static int32_t
1132e1000_get_software_semaphore(struct e1000_hw *hw)
1133{
1134         int32_t timeout = hw->eeprom.word_size + 1;
1135         uint32_t swsm;
1136
1137        DEBUGFUNC();
1138
1139        if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb)
1140                return E1000_SUCCESS;
1141
1142        while (timeout) {
1143                swsm = E1000_READ_REG(hw, SWSM);
1144                /* If SMBI bit cleared, it is now set and we hold
1145                 * the semaphore */
1146                if (!(swsm & E1000_SWSM_SMBI))
1147                        break;
1148                mdelay(1);
1149                timeout--;
1150        }
1151
1152        if (!timeout) {
1153                DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1154                return -E1000_ERR_RESET;
1155        }
1156
1157        return E1000_SUCCESS;
1158}
1159#endif
1160
1161/***************************************************************************
1162 * This function clears HW semaphore bits.
1163 *
1164 * hw: Struct containing variables accessed by shared code
1165 *
1166 * returns: - None.
1167 *
1168 ***************************************************************************/
1169static void
1170e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1171{
1172#ifndef CONFIG_E1000_NO_NVM
1173         uint32_t swsm;
1174
1175        DEBUGFUNC();
1176
1177        if (!hw->eeprom_semaphore_present)
1178                return;
1179
1180        swsm = E1000_READ_REG(hw, SWSM);
1181        if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
1182                /* Release both semaphores. */
1183                swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1184        } else
1185                swsm &= ~(E1000_SWSM_SWESMBI);
1186        E1000_WRITE_REG(hw, SWSM, swsm);
1187#endif
1188}
1189
1190/***************************************************************************
1191 *
1192 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1193 * adapter or Eeprom access.
1194 *
1195 * hw: Struct containing variables accessed by shared code
1196 *
1197 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1198 *            E1000_SUCCESS at any other case.
1199 *
1200 ***************************************************************************/
1201static int32_t
1202e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1203{
1204#ifndef CONFIG_E1000_NO_NVM
1205        int32_t timeout;
1206        uint32_t swsm;
1207
1208        DEBUGFUNC();
1209
1210        if (!hw->eeprom_semaphore_present)
1211                return E1000_SUCCESS;
1212
1213        if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
1214                /* Get the SW semaphore. */
1215                if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1216                        return -E1000_ERR_EEPROM;
1217        }
1218
1219        /* Get the FW semaphore. */
1220        timeout = hw->eeprom.word_size + 1;
1221        while (timeout) {
1222                swsm = E1000_READ_REG(hw, SWSM);
1223                swsm |= E1000_SWSM_SWESMBI;
1224                E1000_WRITE_REG(hw, SWSM, swsm);
1225                /* if we managed to set the bit we got the semaphore. */
1226                swsm = E1000_READ_REG(hw, SWSM);
1227                if (swsm & E1000_SWSM_SWESMBI)
1228                        break;
1229
1230                udelay(50);
1231                timeout--;
1232        }
1233
1234        if (!timeout) {
1235                /* Release semaphores */
1236                e1000_put_hw_eeprom_semaphore(hw);
1237                DEBUGOUT("Driver can't access the Eeprom - "
1238                                "SWESMBI bit is set.\n");
1239                return -E1000_ERR_EEPROM;
1240        }
1241#endif
1242        return E1000_SUCCESS;
1243}
1244
1245/* Take ownership of the PHY */
1246static int32_t
1247e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1248{
1249        uint32_t swfw_sync = 0;
1250        uint32_t swmask = mask;
1251        uint32_t fwmask = mask << 16;
1252        int32_t timeout = 200;
1253
1254        DEBUGFUNC();
1255        while (timeout) {
1256                if (e1000_get_hw_eeprom_semaphore(hw))
1257                        return -E1000_ERR_SWFW_SYNC;
1258
1259                swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1260                if (!(swfw_sync & (fwmask | swmask)))
1261                        break;
1262
1263                /* firmware currently using resource (fwmask) */
1264                /* or other software thread currently using resource (swmask) */
1265                e1000_put_hw_eeprom_semaphore(hw);
1266                mdelay(5);
1267                timeout--;
1268        }
1269
1270        if (!timeout) {
1271                DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1272                return -E1000_ERR_SWFW_SYNC;
1273        }
1274
1275        swfw_sync |= swmask;
1276        E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1277
1278        e1000_put_hw_eeprom_semaphore(hw);
1279        return E1000_SUCCESS;
1280}
1281
1282static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
1283{
1284        uint32_t swfw_sync = 0;
1285
1286        DEBUGFUNC();
1287        while (e1000_get_hw_eeprom_semaphore(hw))
1288                ; /* Empty */
1289
1290        swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1291        swfw_sync &= ~mask;
1292        E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1293
1294        e1000_put_hw_eeprom_semaphore(hw);
1295}
1296
1297static bool e1000_is_second_port(struct e1000_hw *hw)
1298{
1299        switch (hw->mac_type) {
1300        case e1000_80003es2lan:
1301        case e1000_82546:
1302        case e1000_82571:
1303                if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1304                        return true;
1305                /* Fallthrough */
1306        default:
1307                return false;
1308        }
1309}
1310
1311#ifndef CONFIG_E1000_NO_NVM
1312/******************************************************************************
1313 * Reads the adapter's MAC address from the EEPROM
1314 *
1315 * hw - Struct containing variables accessed by shared code
1316 * enetaddr - buffering where the MAC address will be stored
1317 *****************************************************************************/
1318static int e1000_read_mac_addr_from_eeprom(struct e1000_hw *hw,
1319                                           unsigned char enetaddr[6])
1320{
1321        uint16_t offset;
1322        uint16_t eeprom_data;
1323        int i;
1324
1325        for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1326                offset = i >> 1;
1327                if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1328                        DEBUGOUT("EEPROM Read Error\n");
1329                        return -E1000_ERR_EEPROM;
1330                }
1331                enetaddr[i] = eeprom_data & 0xff;
1332                enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1333        }
1334
1335        return 0;
1336}
1337
1338/******************************************************************************
1339 * Reads the adapter's MAC address from the RAL/RAH registers
1340 *
1341 * hw - Struct containing variables accessed by shared code
1342 * enetaddr - buffering where the MAC address will be stored
1343 *****************************************************************************/
1344static int e1000_read_mac_addr_from_regs(struct e1000_hw *hw,
1345                                         unsigned char enetaddr[6])
1346{
1347        uint16_t offset, tmp;
1348        uint32_t reg_data = 0;
1349        int i;
1350
1351        if (hw->mac_type != e1000_igb)
1352                return -E1000_ERR_MAC_TYPE;
1353
1354        for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1355                offset = i >> 1;
1356
1357                if (offset == 0)
1358                        reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
1359                else if (offset == 1)
1360                        reg_data >>= 16;
1361                else if (offset == 2)
1362                        reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
1363                tmp = reg_data & 0xffff;
1364
1365                enetaddr[i] = tmp & 0xff;
1366                enetaddr[i + 1] = (tmp >> 8) & 0xff;
1367        }
1368
1369        return 0;
1370}
1371
1372/******************************************************************************
1373 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1374 * second function of dual function devices
1375 *
1376 * hw - Struct containing variables accessed by shared code
1377 * enetaddr - buffering where the MAC address will be stored
1378 *****************************************************************************/
1379static int e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
1380{
1381        int ret_val;
1382
1383        if (hw->mac_type == e1000_igb) {
1384                /* i210 preloads MAC address into RAL/RAH registers */
1385                ret_val = e1000_read_mac_addr_from_regs(hw, enetaddr);
1386        } else {
1387                ret_val = e1000_read_mac_addr_from_eeprom(hw, enetaddr);
1388        }
1389        if (ret_val)
1390                return ret_val;
1391
1392        /* Invert the last bit if this is the second device */
1393        if (e1000_is_second_port(hw))
1394                enetaddr[5] ^= 1;
1395
1396        return 0;
1397}
1398#endif
1399
1400/******************************************************************************
1401 * Initializes receive address filters.
1402 *
1403 * hw - Struct containing variables accessed by shared code
1404 *
1405 * Places the MAC address in receive address register 0 and clears the rest
1406 * of the receive addresss registers. Clears the multicast table. Assumes
1407 * the receiver is in reset when the routine is called.
1408 *****************************************************************************/
1409static void
1410e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6])
1411{
1412        uint32_t i;
1413        uint32_t addr_low;
1414        uint32_t addr_high;
1415
1416        DEBUGFUNC();
1417
1418        /* Setup the receive address. */
1419        DEBUGOUT("Programming MAC Address into RAR[0]\n");
1420        addr_low = (enetaddr[0] |
1421                    (enetaddr[1] << 8) |
1422                    (enetaddr[2] << 16) | (enetaddr[3] << 24));
1423
1424        addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV);
1425
1426        E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1427        E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1428
1429        /* Zero out the other 15 receive addresses. */
1430        DEBUGOUT("Clearing RAR[1-15]\n");
1431        for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1432                E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1433                E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1434        }
1435}
1436
1437/******************************************************************************
1438 * Clears the VLAN filer table
1439 *
1440 * hw - Struct containing variables accessed by shared code
1441 *****************************************************************************/
1442static void
1443e1000_clear_vfta(struct e1000_hw *hw)
1444{
1445        uint32_t offset;
1446
1447        for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1448                E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1449}
1450
1451/******************************************************************************
1452 * Set the mac type member in the hw struct.
1453 *
1454 * hw - Struct containing variables accessed by shared code
1455 *****************************************************************************/
1456int32_t
1457e1000_set_mac_type(struct e1000_hw *hw)
1458{
1459        DEBUGFUNC();
1460
1461        switch (hw->device_id) {
1462        case E1000_DEV_ID_82542:
1463                switch (hw->revision_id) {
1464                case E1000_82542_2_0_REV_ID:
1465                        hw->mac_type = e1000_82542_rev2_0;
1466                        break;
1467                case E1000_82542_2_1_REV_ID:
1468                        hw->mac_type = e1000_82542_rev2_1;
1469                        break;
1470                default:
1471                        /* Invalid 82542 revision ID */
1472                        return -E1000_ERR_MAC_TYPE;
1473                }
1474                break;
1475        case E1000_DEV_ID_82543GC_FIBER:
1476        case E1000_DEV_ID_82543GC_COPPER:
1477                hw->mac_type = e1000_82543;
1478                break;
1479        case E1000_DEV_ID_82544EI_COPPER:
1480        case E1000_DEV_ID_82544EI_FIBER:
1481        case E1000_DEV_ID_82544GC_COPPER:
1482        case E1000_DEV_ID_82544GC_LOM:
1483                hw->mac_type = e1000_82544;
1484                break;
1485        case E1000_DEV_ID_82540EM:
1486        case E1000_DEV_ID_82540EM_LOM:
1487        case E1000_DEV_ID_82540EP:
1488        case E1000_DEV_ID_82540EP_LOM:
1489        case E1000_DEV_ID_82540EP_LP:
1490                hw->mac_type = e1000_82540;
1491                break;
1492        case E1000_DEV_ID_82545EM_COPPER:
1493        case E1000_DEV_ID_82545EM_FIBER:
1494                hw->mac_type = e1000_82545;
1495                break;
1496        case E1000_DEV_ID_82545GM_COPPER:
1497        case E1000_DEV_ID_82545GM_FIBER:
1498        case E1000_DEV_ID_82545GM_SERDES:
1499                hw->mac_type = e1000_82545_rev_3;
1500                break;
1501        case E1000_DEV_ID_82546EB_COPPER:
1502        case E1000_DEV_ID_82546EB_FIBER:
1503        case E1000_DEV_ID_82546EB_QUAD_COPPER:
1504                hw->mac_type = e1000_82546;
1505                break;
1506        case E1000_DEV_ID_82546GB_COPPER:
1507        case E1000_DEV_ID_82546GB_FIBER:
1508        case E1000_DEV_ID_82546GB_SERDES:
1509        case E1000_DEV_ID_82546GB_PCIE:
1510        case E1000_DEV_ID_82546GB_QUAD_COPPER:
1511        case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1512                hw->mac_type = e1000_82546_rev_3;
1513                break;
1514        case E1000_DEV_ID_82541EI:
1515        case E1000_DEV_ID_82541EI_MOBILE:
1516        case E1000_DEV_ID_82541ER_LOM:
1517                hw->mac_type = e1000_82541;
1518                break;
1519        case E1000_DEV_ID_82541ER:
1520        case E1000_DEV_ID_82541GI:
1521        case E1000_DEV_ID_82541GI_LF:
1522        case E1000_DEV_ID_82541GI_MOBILE:
1523                hw->mac_type = e1000_82541_rev_2;
1524                break;
1525        case E1000_DEV_ID_82547EI:
1526        case E1000_DEV_ID_82547EI_MOBILE:
1527                hw->mac_type = e1000_82547;
1528                break;
1529        case E1000_DEV_ID_82547GI:
1530                hw->mac_type = e1000_82547_rev_2;
1531                break;
1532        case E1000_DEV_ID_82571EB_COPPER:
1533        case E1000_DEV_ID_82571EB_FIBER:
1534        case E1000_DEV_ID_82571EB_SERDES:
1535        case E1000_DEV_ID_82571EB_SERDES_DUAL:
1536        case E1000_DEV_ID_82571EB_SERDES_QUAD:
1537        case E1000_DEV_ID_82571EB_QUAD_COPPER:
1538        case E1000_DEV_ID_82571PT_QUAD_COPPER:
1539        case E1000_DEV_ID_82571EB_QUAD_FIBER:
1540        case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1541                hw->mac_type = e1000_82571;
1542                break;
1543        case E1000_DEV_ID_82572EI_COPPER:
1544        case E1000_DEV_ID_82572EI_FIBER:
1545        case E1000_DEV_ID_82572EI_SERDES:
1546        case E1000_DEV_ID_82572EI:
1547                hw->mac_type = e1000_82572;
1548                break;
1549        case E1000_DEV_ID_82573E:
1550        case E1000_DEV_ID_82573E_IAMT:
1551        case E1000_DEV_ID_82573L:
1552                hw->mac_type = e1000_82573;
1553                break;
1554        case E1000_DEV_ID_82574L:
1555                hw->mac_type = e1000_82574;
1556                break;
1557        case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1558        case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1559        case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1560        case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1561                hw->mac_type = e1000_80003es2lan;
1562                break;
1563        case E1000_DEV_ID_ICH8_IGP_M_AMT:
1564        case E1000_DEV_ID_ICH8_IGP_AMT:
1565        case E1000_DEV_ID_ICH8_IGP_C:
1566        case E1000_DEV_ID_ICH8_IFE:
1567        case E1000_DEV_ID_ICH8_IFE_GT:
1568        case E1000_DEV_ID_ICH8_IFE_G:
1569        case E1000_DEV_ID_ICH8_IGP_M:
1570                hw->mac_type = e1000_ich8lan;
1571                break;
1572        case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
1573        case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
1574        case PCI_DEVICE_ID_INTEL_I210_COPPER:
1575        case PCI_DEVICE_ID_INTEL_I211_COPPER:
1576        case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
1577        case PCI_DEVICE_ID_INTEL_I210_SERDES:
1578        case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
1579        case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
1580                hw->mac_type = e1000_igb;
1581                break;
1582        default:
1583                /* Should never have loaded on this device */
1584                return -E1000_ERR_MAC_TYPE;
1585        }
1586        return E1000_SUCCESS;
1587}
1588
1589/******************************************************************************
1590 * Reset the transmit and receive units; mask and clear all interrupts.
1591 *
1592 * hw - Struct containing variables accessed by shared code
1593 *****************************************************************************/
1594void
1595e1000_reset_hw(struct e1000_hw *hw)
1596{
1597        uint32_t ctrl;
1598        uint32_t ctrl_ext;
1599        uint32_t manc;
1600        uint32_t pba = 0;
1601        uint32_t reg;
1602
1603        DEBUGFUNC();
1604
1605        /* get the correct pba value for both PCI and PCIe*/
1606        if (hw->mac_type <  e1000_82571)
1607                pba = E1000_DEFAULT_PCI_PBA;
1608        else
1609                pba = E1000_DEFAULT_PCIE_PBA;
1610
1611        /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1612        if (hw->mac_type == e1000_82542_rev2_0) {
1613                DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1614#ifdef CONFIG_DM_ETH
1615                dm_pci_write_config16(hw->pdev, PCI_COMMAND,
1616                                hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1617#else
1618                pci_write_config_word(hw->pdev, PCI_COMMAND,
1619                                hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1620#endif
1621        }
1622
1623        /* Clear interrupt mask to stop board from generating interrupts */
1624        DEBUGOUT("Masking off all interrupts\n");
1625        if (hw->mac_type == e1000_igb)
1626                E1000_WRITE_REG(hw, I210_IAM, 0);
1627        E1000_WRITE_REG(hw, IMC, 0xffffffff);
1628
1629        /* Disable the Transmit and Receive units.  Then delay to allow
1630         * any pending transactions to complete before we hit the MAC with
1631         * the global reset.
1632         */
1633        E1000_WRITE_REG(hw, RCTL, 0);
1634        E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1635        E1000_WRITE_FLUSH(hw);
1636
1637        if (hw->mac_type == e1000_igb) {
1638                E1000_WRITE_REG(hw, RXPBS, I210_RXPBSIZE_DEFAULT);
1639                E1000_WRITE_REG(hw, TXPBS, I210_TXPBSIZE_DEFAULT);
1640        }
1641
1642        /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1643        hw->tbi_compatibility_on = false;
1644
1645        /* Delay to allow any outstanding PCI transactions to complete before
1646         * resetting the device
1647         */
1648        mdelay(10);
1649
1650        /* Issue a global reset to the MAC.  This will reset the chip's
1651         * transmit, receive, DMA, and link units.  It will not effect
1652         * the current PCI configuration.  The global reset bit is self-
1653         * clearing, and should clear within a microsecond.
1654         */
1655        DEBUGOUT("Issuing a global reset to MAC\n");
1656        ctrl = E1000_READ_REG(hw, CTRL);
1657
1658        E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1659
1660        /* Force a reload from the EEPROM if necessary */
1661        if (hw->mac_type == e1000_igb) {
1662                mdelay(20);
1663                reg = E1000_READ_REG(hw, STATUS);
1664                if (reg & E1000_STATUS_PF_RST_DONE)
1665                        DEBUGOUT("PF OK\n");
1666                reg = E1000_READ_REG(hw, I210_EECD);
1667                if (reg & E1000_EECD_AUTO_RD)
1668                        DEBUGOUT("EEC OK\n");
1669        } else if (hw->mac_type < e1000_82540) {
1670                /* Wait for reset to complete */
1671                udelay(10);
1672                ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1673                ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1674                E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1675                E1000_WRITE_FLUSH(hw);
1676                /* Wait for EEPROM reload */
1677                mdelay(2);
1678        } else {
1679                /* Wait for EEPROM reload (it happens automatically) */
1680                mdelay(4);
1681                /* Dissable HW ARPs on ASF enabled adapters */
1682                manc = E1000_READ_REG(hw, MANC);
1683                manc &= ~(E1000_MANC_ARP_EN);
1684                E1000_WRITE_REG(hw, MANC, manc);
1685        }
1686
1687        /* Clear interrupt mask to stop board from generating interrupts */
1688        DEBUGOUT("Masking off all interrupts\n");
1689        if (hw->mac_type == e1000_igb)
1690                E1000_WRITE_REG(hw, I210_IAM, 0);
1691        E1000_WRITE_REG(hw, IMC, 0xffffffff);
1692
1693        /* Clear any pending interrupt events. */
1694        E1000_READ_REG(hw, ICR);
1695
1696        /* If MWI was previously enabled, reenable it. */
1697        if (hw->mac_type == e1000_82542_rev2_0) {
1698#ifdef CONFIG_DM_ETH
1699                dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1700#else
1701                pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1702#endif
1703        }
1704        if (hw->mac_type != e1000_igb)
1705                E1000_WRITE_REG(hw, PBA, pba);
1706}
1707
1708/******************************************************************************
1709 *
1710 * Initialize a number of hardware-dependent bits
1711 *
1712 * hw: Struct containing variables accessed by shared code
1713 *
1714 * This function contains hardware limitation workarounds for PCI-E adapters
1715 *
1716 *****************************************************************************/
1717static void
1718e1000_initialize_hardware_bits(struct e1000_hw *hw)
1719{
1720        if ((hw->mac_type >= e1000_82571) &&
1721                        (!hw->initialize_hw_bits_disable)) {
1722                /* Settings common to all PCI-express silicon */
1723                uint32_t reg_ctrl, reg_ctrl_ext;
1724                uint32_t reg_tarc0, reg_tarc1;
1725                uint32_t reg_tctl;
1726                uint32_t reg_txdctl, reg_txdctl1;
1727
1728                /* link autonegotiation/sync workarounds */
1729                reg_tarc0 = E1000_READ_REG(hw, TARC0);
1730                reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1731
1732                /* Enable not-done TX descriptor counting */
1733                reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1734                reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1735                E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1736
1737                reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1738                reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1739                E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1740
1741
1742                switch (hw->mac_type) {
1743                case e1000_igb:                 /* IGB is cool */
1744                        return;
1745                case e1000_82571:
1746                case e1000_82572:
1747                        /* Clear PHY TX compatible mode bits */
1748                        reg_tarc1 = E1000_READ_REG(hw, TARC1);
1749                        reg_tarc1 &= ~((1 << 30)|(1 << 29));
1750
1751                        /* link autonegotiation/sync workarounds */
1752                        reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1753
1754                        /* TX ring control fixes */
1755                        reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1756
1757                        /* Multiple read bit is reversed polarity */
1758                        reg_tctl = E1000_READ_REG(hw, TCTL);
1759                        if (reg_tctl & E1000_TCTL_MULR)
1760                                reg_tarc1 &= ~(1 << 28);
1761                        else
1762                                reg_tarc1 |= (1 << 28);
1763
1764                        E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1765                        break;
1766                case e1000_82573:
1767                case e1000_82574:
1768                        reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1769                        reg_ctrl_ext &= ~(1 << 23);
1770                        reg_ctrl_ext |= (1 << 22);
1771
1772                        /* TX byte count fix */
1773                        reg_ctrl = E1000_READ_REG(hw, CTRL);
1774                        reg_ctrl &= ~(1 << 29);
1775
1776                        E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1777                        E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1778                        break;
1779                case e1000_80003es2lan:
1780        /* improve small packet performace for fiber/serdes */
1781                        if ((hw->media_type == e1000_media_type_fiber)
1782                        || (hw->media_type ==
1783                                e1000_media_type_internal_serdes)) {
1784                                reg_tarc0 &= ~(1 << 20);
1785                        }
1786
1787                /* Multiple read bit is reversed polarity */
1788                        reg_tctl = E1000_READ_REG(hw, TCTL);
1789                        reg_tarc1 = E1000_READ_REG(hw, TARC1);
1790                        if (reg_tctl & E1000_TCTL_MULR)
1791                                reg_tarc1 &= ~(1 << 28);
1792                        else
1793                                reg_tarc1 |= (1 << 28);
1794
1795                        E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1796                        break;
1797                case e1000_ich8lan:
1798                        /* Reduce concurrent DMA requests to 3 from 4 */
1799                        if ((hw->revision_id < 3) ||
1800                        ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1801                                (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1802                                reg_tarc0 |= ((1 << 29)|(1 << 28));
1803
1804                        reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1805                        reg_ctrl_ext |= (1 << 22);
1806                        E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1807
1808                        /* workaround TX hang with TSO=on */
1809                        reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1810
1811                        /* Multiple read bit is reversed polarity */
1812                        reg_tctl = E1000_READ_REG(hw, TCTL);
1813                        reg_tarc1 = E1000_READ_REG(hw, TARC1);
1814                        if (reg_tctl & E1000_TCTL_MULR)
1815                                reg_tarc1 &= ~(1 << 28);
1816                        else
1817                                reg_tarc1 |= (1 << 28);
1818
1819                        /* workaround TX hang with TSO=on */
1820                        reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1821
1822                        E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1823                        break;
1824                default:
1825                        break;
1826                }
1827
1828                E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1829        }
1830}
1831
1832/******************************************************************************
1833 * Performs basic configuration of the adapter.
1834 *
1835 * hw - Struct containing variables accessed by shared code
1836 *
1837 * Assumes that the controller has previously been reset and is in a
1838 * post-reset uninitialized state. Initializes the receive address registers,
1839 * multicast table, and VLAN filter table. Calls routines to setup link
1840 * configuration and flow control settings. Clears all on-chip counters. Leaves
1841 * the transmit and receive units disabled and uninitialized.
1842 *****************************************************************************/
1843static int
1844e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
1845{
1846        uint32_t ctrl;
1847        uint32_t i;
1848        int32_t ret_val;
1849        uint16_t pcix_cmd_word;
1850        uint16_t pcix_stat_hi_word;
1851        uint16_t cmd_mmrbc;
1852        uint16_t stat_mmrbc;
1853        uint32_t mta_size;
1854        uint32_t reg_data;
1855        uint32_t ctrl_ext;
1856        DEBUGFUNC();
1857        /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1858        if ((hw->mac_type == e1000_ich8lan) &&
1859                ((hw->revision_id < 3) ||
1860                ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1861                (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1862                        reg_data = E1000_READ_REG(hw, STATUS);
1863                        reg_data &= ~0x80000000;
1864                        E1000_WRITE_REG(hw, STATUS, reg_data);
1865        }
1866        /* Do not need initialize Identification LED */
1867
1868        /* Set the media type and TBI compatibility */
1869        e1000_set_media_type(hw);
1870
1871        /* Must be called after e1000_set_media_type
1872         * because media_type is used */
1873        e1000_initialize_hardware_bits(hw);
1874
1875        /* Disabling VLAN filtering. */
1876        DEBUGOUT("Initializing the IEEE VLAN\n");
1877        /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1878        if (hw->mac_type != e1000_ich8lan) {
1879                if (hw->mac_type < e1000_82545_rev_3)
1880                        E1000_WRITE_REG(hw, VET, 0);
1881                e1000_clear_vfta(hw);
1882        }
1883
1884        /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1885        if (hw->mac_type == e1000_82542_rev2_0) {
1886                DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1887#ifdef CONFIG_DM_ETH
1888                dm_pci_write_config16(hw->pdev, PCI_COMMAND,
1889                                      hw->
1890                                      pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1891#else
1892                pci_write_config_word(hw->pdev, PCI_COMMAND,
1893                                      hw->
1894                                      pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1895#endif
1896                E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1897                E1000_WRITE_FLUSH(hw);
1898                mdelay(5);
1899        }
1900
1901        /* Setup the receive address. This involves initializing all of the Receive
1902         * Address Registers (RARs 0 - 15).
1903         */
1904        e1000_init_rx_addrs(hw, enetaddr);
1905
1906        /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1907        if (hw->mac_type == e1000_82542_rev2_0) {
1908                E1000_WRITE_REG(hw, RCTL, 0);
1909                E1000_WRITE_FLUSH(hw);
1910                mdelay(1);
1911#ifdef CONFIG_DM_ETH
1912                dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1913#else
1914                pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1915#endif
1916        }
1917
1918        /* Zero out the Multicast HASH table */
1919        DEBUGOUT("Zeroing the MTA\n");
1920        mta_size = E1000_MC_TBL_SIZE;
1921        if (hw->mac_type == e1000_ich8lan)
1922                mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1923        for (i = 0; i < mta_size; i++) {
1924                E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1925                /* use write flush to prevent Memory Write Block (MWB) from
1926                 * occuring when accessing our register space */
1927                E1000_WRITE_FLUSH(hw);
1928        }
1929
1930        switch (hw->mac_type) {
1931        case e1000_82545_rev_3:
1932        case e1000_82546_rev_3:
1933        case e1000_igb:
1934                break;
1935        default:
1936        /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1937        if (hw->bus_type == e1000_bus_type_pcix) {
1938#ifdef CONFIG_DM_ETH
1939                dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER,
1940                                     &pcix_cmd_word);
1941                dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI,
1942                                     &pcix_stat_hi_word);
1943#else
1944                pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1945                                     &pcix_cmd_word);
1946                pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1947                                     &pcix_stat_hi_word);
1948#endif
1949                cmd_mmrbc =
1950                    (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1951                    PCIX_COMMAND_MMRBC_SHIFT;
1952                stat_mmrbc =
1953                    (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1954                    PCIX_STATUS_HI_MMRBC_SHIFT;
1955                if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1956                        stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1957                if (cmd_mmrbc > stat_mmrbc) {
1958                        pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1959                        pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1960#ifdef CONFIG_DM_ETH
1961                        dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER,
1962                                              pcix_cmd_word);
1963#else
1964                        pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1965                                              pcix_cmd_word);
1966#endif
1967                }
1968        }
1969                break;
1970        }
1971
1972        /* More time needed for PHY to initialize */
1973        if (hw->mac_type == e1000_ich8lan)
1974                mdelay(15);
1975        if (hw->mac_type == e1000_igb)
1976                mdelay(15);
1977
1978        /* Call a subroutine to configure the link and setup flow control. */
1979        ret_val = e1000_setup_link(hw);
1980
1981        /* Set the transmit descriptor write-back policy */
1982        if (hw->mac_type > e1000_82544) {
1983                ctrl = E1000_READ_REG(hw, TXDCTL);
1984                ctrl =
1985                    (ctrl & ~E1000_TXDCTL_WTHRESH) |
1986                    E1000_TXDCTL_FULL_TX_DESC_WB;
1987                E1000_WRITE_REG(hw, TXDCTL, ctrl);
1988        }
1989
1990        /* Set the receive descriptor write back policy */
1991        if (hw->mac_type >= e1000_82571) {
1992                ctrl = E1000_READ_REG(hw, RXDCTL);
1993                ctrl =
1994                    (ctrl & ~E1000_RXDCTL_WTHRESH) |
1995                    E1000_RXDCTL_FULL_RX_DESC_WB;
1996                E1000_WRITE_REG(hw, RXDCTL, ctrl);
1997        }
1998
1999        switch (hw->mac_type) {
2000        default:
2001                break;
2002        case e1000_80003es2lan:
2003                /* Enable retransmit on late collisions */
2004                reg_data = E1000_READ_REG(hw, TCTL);
2005                reg_data |= E1000_TCTL_RTLC;
2006                E1000_WRITE_REG(hw, TCTL, reg_data);
2007
2008                /* Configure Gigabit Carry Extend Padding */
2009                reg_data = E1000_READ_REG(hw, TCTL_EXT);
2010                reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
2011                reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
2012                E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
2013
2014                /* Configure Transmit Inter-Packet Gap */
2015                reg_data = E1000_READ_REG(hw, TIPG);
2016                reg_data &= ~E1000_TIPG_IPGT_MASK;
2017                reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2018                E1000_WRITE_REG(hw, TIPG, reg_data);
2019
2020                reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
2021                reg_data &= ~0x00100000;
2022                E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
2023                /* Fall through */
2024        case e1000_82571:
2025        case e1000_82572:
2026        case e1000_ich8lan:
2027                ctrl = E1000_READ_REG(hw, TXDCTL1);
2028                ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
2029                        | E1000_TXDCTL_FULL_TX_DESC_WB;
2030                E1000_WRITE_REG(hw, TXDCTL1, ctrl);
2031                break;
2032        case e1000_82573:
2033        case e1000_82574:
2034                reg_data = E1000_READ_REG(hw, GCR);
2035                reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
2036                E1000_WRITE_REG(hw, GCR, reg_data);
2037        case e1000_igb:
2038                break;
2039        }
2040
2041        if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
2042                hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
2043                ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2044                /* Relaxed ordering must be disabled to avoid a parity
2045                 * error crash in a PCI slot. */
2046                ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2047                E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2048        }
2049
2050        return ret_val;
2051}
2052
2053/******************************************************************************
2054 * Configures flow control and link settings.
2055 *
2056 * hw - Struct containing variables accessed by shared code
2057 *
2058 * Determines which flow control settings to use. Calls the apropriate media-
2059 * specific link configuration function. Configures the flow control settings.
2060 * Assuming the adapter has a valid link partner, a valid link should be
2061 * established. Assumes the hardware has previously been reset and the
2062 * transmitter and receiver are not enabled.
2063 *****************************************************************************/
2064static int
2065e1000_setup_link(struct e1000_hw *hw)
2066{
2067        int32_t ret_val;
2068#ifndef CONFIG_E1000_NO_NVM
2069        uint32_t ctrl_ext;
2070        uint16_t eeprom_data;
2071#endif
2072
2073        DEBUGFUNC();
2074
2075        /* In the case of the phy reset being blocked, we already have a link.
2076         * We do not have to set it up again. */
2077        if (e1000_check_phy_reset_block(hw))
2078                return E1000_SUCCESS;
2079
2080#ifndef CONFIG_E1000_NO_NVM
2081        /* Read and store word 0x0F of the EEPROM. This word contains bits
2082         * that determine the hardware's default PAUSE (flow control) mode,
2083         * a bit that determines whether the HW defaults to enabling or
2084         * disabling auto-negotiation, and the direction of the
2085         * SW defined pins. If there is no SW over-ride of the flow
2086         * control setting, then the variable hw->fc will
2087         * be initialized based on a value in the EEPROM.
2088         */
2089        if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
2090                                &eeprom_data) < 0) {
2091                DEBUGOUT("EEPROM Read Error\n");
2092                return -E1000_ERR_EEPROM;
2093        }
2094#endif
2095        if (hw->fc == e1000_fc_default) {
2096                switch (hw->mac_type) {
2097                case e1000_ich8lan:
2098                case e1000_82573:
2099                case e1000_82574:
2100                case e1000_igb:
2101                        hw->fc = e1000_fc_full;
2102                        break;
2103                default:
2104#ifndef CONFIG_E1000_NO_NVM
2105                        ret_val = e1000_read_eeprom(hw,
2106                                EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
2107                        if (ret_val) {
2108                                DEBUGOUT("EEPROM Read Error\n");
2109                                return -E1000_ERR_EEPROM;
2110                        }
2111                        if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
2112                                hw->fc = e1000_fc_none;
2113                        else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
2114                                    EEPROM_WORD0F_ASM_DIR)
2115                                hw->fc = e1000_fc_tx_pause;
2116                        else
2117#endif
2118                                hw->fc = e1000_fc_full;
2119                        break;
2120                }
2121        }
2122
2123        /* We want to save off the original Flow Control configuration just
2124         * in case we get disconnected and then reconnected into a different
2125         * hub or switch with different Flow Control capabilities.
2126         */
2127        if (hw->mac_type == e1000_82542_rev2_0)
2128                hw->fc &= (~e1000_fc_tx_pause);
2129
2130        if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
2131                hw->fc &= (~e1000_fc_rx_pause);
2132
2133        hw->original_fc = hw->fc;
2134
2135        DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
2136
2137#ifndef CONFIG_E1000_NO_NVM
2138        /* Take the 4 bits from EEPROM word 0x0F that determine the initial
2139         * polarity value for the SW controlled pins, and setup the
2140         * Extended Device Control reg with that info.
2141         * This is needed because one of the SW controlled pins is used for
2142         * signal detection.  So this should be done before e1000_setup_pcs_link()
2143         * or e1000_phy_setup() is called.
2144         */
2145        if (hw->mac_type == e1000_82543) {
2146                ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
2147                            SWDPIO__EXT_SHIFT);
2148                E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2149        }
2150#endif
2151
2152        /* Call the necessary subroutine to configure the link. */
2153        ret_val = (hw->media_type == e1000_media_type_fiber) ?
2154            e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw);
2155        if (ret_val < 0) {
2156                return ret_val;
2157        }
2158
2159        /* Initialize the flow control address, type, and PAUSE timer
2160         * registers to their default values.  This is done even if flow
2161         * control is disabled, because it does not hurt anything to
2162         * initialize these registers.
2163         */
2164        DEBUGOUT("Initializing the Flow Control address, type"
2165                        "and timer regs\n");
2166
2167        /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
2168        if (hw->mac_type != e1000_ich8lan) {
2169                E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
2170                E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
2171                E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
2172        }
2173
2174        E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
2175
2176        /* Set the flow control receive threshold registers.  Normally,
2177         * these registers will be set to a default threshold that may be
2178         * adjusted later by the driver's runtime code.  However, if the
2179         * ability to transmit pause frames in not enabled, then these
2180         * registers will be set to 0.
2181         */
2182        if (!(hw->fc & e1000_fc_tx_pause)) {
2183                E1000_WRITE_REG(hw, FCRTL, 0);
2184                E1000_WRITE_REG(hw, FCRTH, 0);
2185        } else {
2186                /* We need to set up the Receive Threshold high and low water marks
2187                 * as well as (optionally) enabling the transmission of XON frames.
2188                 */
2189                if (hw->fc_send_xon) {
2190                        E1000_WRITE_REG(hw, FCRTL,
2191                                        (hw->fc_low_water | E1000_FCRTL_XONE));
2192                        E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2193                } else {
2194                        E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
2195                        E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2196                }
2197        }
2198        return ret_val;
2199}
2200
2201/******************************************************************************
2202 * Sets up link for a fiber based adapter
2203 *
2204 * hw - Struct containing variables accessed by shared code
2205 *
2206 * Manipulates Physical Coding Sublayer functions in order to configure
2207 * link. Assumes the hardware has been previously reset and the transmitter
2208 * and receiver are not enabled.
2209 *****************************************************************************/
2210static int
2211e1000_setup_fiber_link(struct e1000_hw *hw)
2212{
2213        uint32_t ctrl;
2214        uint32_t status;
2215        uint32_t txcw = 0;
2216        uint32_t i;
2217        uint32_t signal;
2218        int32_t ret_val;
2219
2220        DEBUGFUNC();
2221        /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
2222         * set when the optics detect a signal. On older adapters, it will be
2223         * cleared when there is a signal
2224         */
2225        ctrl = E1000_READ_REG(hw, CTRL);
2226        if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
2227                signal = E1000_CTRL_SWDPIN1;
2228        else
2229                signal = 0;
2230
2231        printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal,
2232               ctrl);
2233        /* Take the link out of reset */
2234        ctrl &= ~(E1000_CTRL_LRST);
2235
2236        e1000_config_collision_dist(hw);
2237
2238        /* Check for a software override of the flow control settings, and setup
2239         * the device accordingly.  If auto-negotiation is enabled, then software
2240         * will have to set the "PAUSE" bits to the correct value in the Tranmsit
2241         * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
2242         * auto-negotiation is disabled, then software will have to manually
2243         * configure the two flow control enable bits in the CTRL register.
2244         *
2245         * The possible values of the "fc" parameter are:
2246         *      0:  Flow control is completely disabled
2247         *      1:  Rx flow control is enabled (we can receive pause frames, but
2248         *          not send pause frames).
2249         *      2:  Tx flow control is enabled (we can send pause frames but we do
2250         *          not support receiving pause frames).
2251         *      3:  Both Rx and TX flow control (symmetric) are enabled.
2252         */
2253        switch (hw->fc) {
2254        case e1000_fc_none:
2255                /* Flow control is completely disabled by a software over-ride. */
2256                txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2257                break;
2258        case e1000_fc_rx_pause:
2259                /* RX Flow control is enabled and TX Flow control is disabled by a
2260                 * software over-ride. Since there really isn't a way to advertise
2261                 * that we are capable of RX Pause ONLY, we will advertise that we
2262                 * support both symmetric and asymmetric RX PAUSE. Later, we will
2263                 *  disable the adapter's ability to send PAUSE frames.
2264                 */
2265                txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2266                break;
2267        case e1000_fc_tx_pause:
2268                /* TX Flow control is enabled, and RX Flow control is disabled, by a
2269                 * software over-ride.
2270                 */
2271                txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2272                break;
2273        case e1000_fc_full:
2274                /* Flow control (both RX and TX) is enabled by a software over-ride. */
2275                txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2276                break;
2277        default:
2278                DEBUGOUT("Flow control param set incorrectly\n");
2279                return -E1000_ERR_CONFIG;
2280                break;
2281        }
2282
2283        /* Since auto-negotiation is enabled, take the link out of reset (the link
2284         * will be in reset, because we previously reset the chip). This will
2285         * restart auto-negotiation.  If auto-neogtiation is successful then the
2286         * link-up status bit will be set and the flow control enable bits (RFCE
2287         * and TFCE) will be set according to their negotiated value.
2288         */
2289        DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2290
2291        E1000_WRITE_REG(hw, TXCW, txcw);
2292        E1000_WRITE_REG(hw, CTRL, ctrl);
2293        E1000_WRITE_FLUSH(hw);
2294
2295        hw->txcw = txcw;
2296        mdelay(1);
2297
2298        /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2299         * indication in the Device Status Register.  Time-out if a link isn't
2300         * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2301         * less than 500 milliseconds even if the other end is doing it in SW).
2302         */
2303        if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2304                DEBUGOUT("Looking for Link\n");
2305                for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2306                        mdelay(10);
2307                        status = E1000_READ_REG(hw, STATUS);
2308                        if (status & E1000_STATUS_LU)
2309                                break;
2310                }
2311                if (i == (LINK_UP_TIMEOUT / 10)) {
2312                        /* AutoNeg failed to achieve a link, so we'll call
2313                         * e1000_check_for_link. This routine will force the link up if we
2314                         * detect a signal. This will allow us to communicate with
2315                         * non-autonegotiating link partners.
2316                         */
2317                        DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2318                        hw->autoneg_failed = 1;
2319                        ret_val = e1000_check_for_link(hw);
2320                        if (ret_val < 0) {
2321                                DEBUGOUT("Error while checking for link\n");
2322                                return ret_val;
2323                        }
2324                        hw->autoneg_failed = 0;
2325                } else {
2326                        hw->autoneg_failed = 0;
2327                        DEBUGOUT("Valid Link Found\n");
2328                }
2329        } else {
2330                DEBUGOUT("No Signal Detected\n");
2331                return -E1000_ERR_NOLINK;
2332        }
2333        return 0;
2334}
2335
2336/******************************************************************************
2337* Make sure we have a valid PHY and change PHY mode before link setup.
2338*
2339* hw - Struct containing variables accessed by shared code
2340******************************************************************************/
2341static int32_t
2342e1000_copper_link_preconfig(struct e1000_hw *hw)
2343{
2344        uint32_t ctrl;
2345        int32_t ret_val;
2346        uint16_t phy_data;
2347
2348        DEBUGFUNC();
2349
2350        ctrl = E1000_READ_REG(hw, CTRL);
2351        /* With 82543, we need to force speed and duplex on the MAC equal to what
2352         * the PHY speed and duplex configuration is. In addition, we need to
2353         * perform a hardware reset on the PHY to take it out of reset.
2354         */
2355        if (hw->mac_type > e1000_82543) {
2356                ctrl |= E1000_CTRL_SLU;
2357                ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2358                E1000_WRITE_REG(hw, CTRL, ctrl);
2359        } else {
2360                ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2361                                | E1000_CTRL_SLU);
2362                E1000_WRITE_REG(hw, CTRL, ctrl);
2363                ret_val = e1000_phy_hw_reset(hw);
2364                if (ret_val)
2365                        return ret_val;
2366        }
2367
2368        /* Make sure we have a valid PHY */
2369        ret_val = e1000_detect_gig_phy(hw);
2370        if (ret_val) {
2371                DEBUGOUT("Error, did not detect valid phy.\n");
2372                return ret_val;
2373        }
2374        DEBUGOUT("Phy ID = %x\n", hw->phy_id);
2375
2376        /* Set PHY to class A mode (if necessary) */
2377        ret_val = e1000_set_phy_mode(hw);
2378        if (ret_val)
2379                return ret_val;
2380        if ((hw->mac_type == e1000_82545_rev_3) ||
2381                (hw->mac_type == e1000_82546_rev_3)) {
2382                ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2383                                &phy_data);
2384                phy_data |= 0x00000008;
2385                ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2386                                phy_data);
2387        }
2388
2389        if (hw->mac_type <= e1000_82543 ||
2390                hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2391                hw->mac_type == e1000_82541_rev_2
2392                || hw->mac_type == e1000_82547_rev_2)
2393                        hw->phy_reset_disable = false;
2394
2395        return E1000_SUCCESS;
2396}
2397
2398/*****************************************************************************
2399 *
2400 * This function sets the lplu state according to the active flag.  When
2401 * activating lplu this function also disables smart speed and vise versa.
2402 * lplu will not be activated unless the device autonegotiation advertisment
2403 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2404 * hw: Struct containing variables accessed by shared code
2405 * active - true to enable lplu false to disable lplu.
2406 *
2407 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2408 *            E1000_SUCCESS at any other case.
2409 *
2410 ****************************************************************************/
2411
2412static int32_t
2413e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
2414{
2415        uint32_t phy_ctrl = 0;
2416        int32_t ret_val;
2417        uint16_t phy_data;
2418        DEBUGFUNC();
2419
2420        if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2421            && hw->phy_type != e1000_phy_igp_3)
2422                return E1000_SUCCESS;
2423
2424        /* During driver activity LPLU should not be used or it will attain link
2425         * from the lowest speeds starting from 10Mbps. The capability is used
2426         * for Dx transitions and states */
2427        if (hw->mac_type == e1000_82541_rev_2
2428                        || hw->mac_type == e1000_82547_rev_2) {
2429                ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2430                                &phy_data);
2431                if (ret_val)
2432                        return ret_val;
2433        } else if (hw->mac_type == e1000_ich8lan) {
2434                /* MAC writes into PHY register based on the state transition
2435                 * and start auto-negotiation. SW driver can overwrite the
2436                 * settings in CSR PHY power control E1000_PHY_CTRL register. */
2437                phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2438        } else {
2439                ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2440                                &phy_data);
2441                if (ret_val)
2442                        return ret_val;
2443        }
2444
2445        if (!active) {
2446                if (hw->mac_type == e1000_82541_rev_2 ||
2447                        hw->mac_type == e1000_82547_rev_2) {
2448                        phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2449                        ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2450                                        phy_data);
2451                        if (ret_val)
2452                                return ret_val;
2453                } else {
2454                        if (hw->mac_type == e1000_ich8lan) {
2455                                phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2456                                E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2457                        } else {
2458                                phy_data &= ~IGP02E1000_PM_D3_LPLU;
2459                                ret_val = e1000_write_phy_reg(hw,
2460                                        IGP02E1000_PHY_POWER_MGMT, phy_data);
2461                                if (ret_val)
2462                                        return ret_val;
2463                        }
2464                }
2465
2466        /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2467         * Dx states where the power conservation is most important.  During
2468         * driver activity we should enable SmartSpeed, so performance is
2469         * maintained. */
2470                if (hw->smart_speed == e1000_smart_speed_on) {
2471                        ret_val = e1000_read_phy_reg(hw,
2472                                        IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2473                        if (ret_val)
2474                                return ret_val;
2475
2476                        phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2477                        ret_val = e1000_write_phy_reg(hw,
2478                                        IGP01E1000_PHY_PORT_CONFIG, phy_data);
2479                        if (ret_val)
2480                                return ret_val;
2481                } else if (hw->smart_speed == e1000_smart_speed_off) {
2482                        ret_val = e1000_read_phy_reg(hw,
2483                                        IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2484                        if (ret_val)
2485                                return ret_val;
2486
2487                        phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2488                        ret_val = e1000_write_phy_reg(hw,
2489                                        IGP01E1000_PHY_PORT_CONFIG, phy_data);
2490                        if (ret_val)
2491                                return ret_val;
2492                }
2493
2494        } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2495                || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2496                (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2497
2498                if (hw->mac_type == e1000_82541_rev_2 ||
2499                    hw->mac_type == e1000_82547_rev_2) {
2500                        phy_data |= IGP01E1000_GMII_FLEX_SPD;
2501                        ret_val = e1000_write_phy_reg(hw,
2502                                        IGP01E1000_GMII_FIFO, phy_data);
2503                        if (ret_val)
2504                                return ret_val;
2505                } else {
2506                        if (hw->mac_type == e1000_ich8lan) {
2507                                phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2508                                E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2509                        } else {
2510                                phy_data |= IGP02E1000_PM_D3_LPLU;
2511                                ret_val = e1000_write_phy_reg(hw,
2512                                        IGP02E1000_PHY_POWER_MGMT, phy_data);
2513                                if (ret_val)
2514                                        return ret_val;
2515                        }
2516                }
2517
2518                /* When LPLU is enabled we should disable SmartSpeed */
2519                ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2520                                &phy_data);
2521                if (ret_val)
2522                        return ret_val;
2523
2524                phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2525                ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2526                                phy_data);
2527                if (ret_val)
2528                        return ret_val;
2529        }
2530        return E1000_SUCCESS;
2531}
2532
2533/*****************************************************************************
2534 *
2535 * This function sets the lplu d0 state according to the active flag.  When
2536 * activating lplu this function also disables smart speed and vise versa.
2537 * lplu will not be activated unless the device autonegotiation advertisment
2538 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2539 * hw: Struct containing variables accessed by shared code
2540 * active - true to enable lplu false to disable lplu.
2541 *
2542 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2543 *            E1000_SUCCESS at any other case.
2544 *
2545 ****************************************************************************/
2546
2547static int32_t
2548e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2549{
2550        uint32_t phy_ctrl = 0;
2551        int32_t ret_val;
2552        uint16_t phy_data;
2553        DEBUGFUNC();
2554
2555        if (hw->mac_type <= e1000_82547_rev_2)
2556                return E1000_SUCCESS;
2557
2558        if (hw->mac_type == e1000_ich8lan) {
2559                phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2560        } else if (hw->mac_type == e1000_igb) {
2561                phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
2562        } else {
2563                ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2564                                &phy_data);
2565                if (ret_val)
2566                        return ret_val;
2567        }
2568
2569        if (!active) {
2570                if (hw->mac_type == e1000_ich8lan) {
2571                        phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2572                        E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2573                } else if (hw->mac_type == e1000_igb) {
2574                        phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2575                        E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2576                } else {
2577                        phy_data &= ~IGP02E1000_PM_D0_LPLU;
2578                        ret_val = e1000_write_phy_reg(hw,
2579                                        IGP02E1000_PHY_POWER_MGMT, phy_data);
2580                        if (ret_val)
2581                                return ret_val;
2582                }
2583
2584                if (hw->mac_type == e1000_igb)
2585                        return E1000_SUCCESS;
2586
2587        /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2588         * Dx states where the power conservation is most important.  During
2589         * driver activity we should enable SmartSpeed, so performance is
2590         * maintained. */
2591                if (hw->smart_speed == e1000_smart_speed_on) {
2592                        ret_val = e1000_read_phy_reg(hw,
2593                                        IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2594                        if (ret_val)
2595                                return ret_val;
2596
2597                        phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2598                        ret_val = e1000_write_phy_reg(hw,
2599                                        IGP01E1000_PHY_PORT_CONFIG, phy_data);
2600                        if (ret_val)
2601                                return ret_val;
2602                } else if (hw->smart_speed == e1000_smart_speed_off) {
2603                        ret_val = e1000_read_phy_reg(hw,
2604                                        IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2605                        if (ret_val)
2606                                return ret_val;
2607
2608                        phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2609                        ret_val = e1000_write_phy_reg(hw,
2610                                        IGP01E1000_PHY_PORT_CONFIG, phy_data);
2611                        if (ret_val)
2612                                return ret_val;
2613                }
2614
2615
2616        } else {
2617
2618                if (hw->mac_type == e1000_ich8lan) {
2619                        phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2620                        E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2621                } else if (hw->mac_type == e1000_igb) {
2622                        phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2623                        E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2624                } else {
2625                        phy_data |= IGP02E1000_PM_D0_LPLU;
2626                        ret_val = e1000_write_phy_reg(hw,
2627                                        IGP02E1000_PHY_POWER_MGMT, phy_data);
2628                        if (ret_val)
2629                                return ret_val;
2630                }
2631
2632                if (hw->mac_type == e1000_igb)
2633                        return E1000_SUCCESS;
2634
2635                /* When LPLU is enabled we should disable SmartSpeed */
2636                ret_val = e1000_read_phy_reg(hw,
2637                                IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2638                if (ret_val)
2639                        return ret_val;
2640
2641                phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2642                ret_val = e1000_write_phy_reg(hw,
2643                                IGP01E1000_PHY_PORT_CONFIG, phy_data);
2644                if (ret_val)
2645                        return ret_val;
2646
2647        }
2648        return E1000_SUCCESS;
2649}
2650
2651/********************************************************************
2652* Copper link setup for e1000_phy_igp series.
2653*
2654* hw - Struct containing variables accessed by shared code
2655*********************************************************************/
2656static int32_t
2657e1000_copper_link_igp_setup(struct e1000_hw *hw)
2658{
2659        uint32_t led_ctrl;
2660        int32_t ret_val;
2661        uint16_t phy_data;
2662
2663        DEBUGFUNC();
2664
2665        if (hw->phy_reset_disable)
2666                return E1000_SUCCESS;
2667
2668        ret_val = e1000_phy_reset(hw);
2669        if (ret_val) {
2670                DEBUGOUT("Error Resetting the PHY\n");
2671                return ret_val;
2672        }
2673
2674        /* Wait 15ms for MAC to configure PHY from eeprom settings */
2675        mdelay(15);
2676        if (hw->mac_type != e1000_ich8lan) {
2677                /* Configure activity LED after PHY reset */
2678                led_ctrl = E1000_READ_REG(hw, LEDCTL);
2679                led_ctrl &= IGP_ACTIVITY_LED_MASK;
2680                led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2681                E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2682        }
2683
2684        /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2685        if (hw->phy_type == e1000_phy_igp) {
2686                /* disable lplu d3 during driver init */
2687                ret_val = e1000_set_d3_lplu_state(hw, false);
2688                if (ret_val) {
2689                        DEBUGOUT("Error Disabling LPLU D3\n");
2690                        return ret_val;
2691                }
2692        }
2693
2694        /* disable lplu d0 during driver init */
2695        ret_val = e1000_set_d0_lplu_state(hw, false);
2696        if (ret_val) {
2697                DEBUGOUT("Error Disabling LPLU D0\n");
2698                return ret_val;
2699        }
2700        /* Configure mdi-mdix settings */
2701        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2702        if (ret_val)
2703                return ret_val;
2704
2705        if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2706                hw->dsp_config_state = e1000_dsp_config_disabled;
2707                /* Force MDI for earlier revs of the IGP PHY */
2708                phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2709                                | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2710                hw->mdix = 1;
2711
2712        } else {
2713                hw->dsp_config_state = e1000_dsp_config_enabled;
2714                phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2715
2716                switch (hw->mdix) {
2717                case 1:
2718                        phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2719                        break;
2720                case 2:
2721                        phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2722                        break;
2723                case 0:
2724                default:
2725                        phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2726                        break;
2727                }
2728        }
2729        ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2730        if (ret_val)
2731                return ret_val;
2732
2733        /* set auto-master slave resolution settings */
2734        if (hw->autoneg) {
2735                e1000_ms_type phy_ms_setting = hw->master_slave;
2736
2737                if (hw->ffe_config_state == e1000_ffe_config_active)
2738                        hw->ffe_config_state = e1000_ffe_config_enabled;
2739
2740                if (hw->dsp_config_state == e1000_dsp_config_activated)
2741                        hw->dsp_config_state = e1000_dsp_config_enabled;
2742
2743                /* when autonegotiation advertisment is only 1000Mbps then we
2744                  * should disable SmartSpeed and enable Auto MasterSlave
2745                  * resolution as hardware default. */
2746                if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2747                        /* Disable SmartSpeed */
2748                        ret_val = e1000_read_phy_reg(hw,
2749                                        IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2750                        if (ret_val)
2751                                return ret_val;
2752                        phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2753                        ret_val = e1000_write_phy_reg(hw,
2754                                        IGP01E1000_PHY_PORT_CONFIG, phy_data);
2755                        if (ret_val)
2756                                return ret_val;
2757                        /* Set auto Master/Slave resolution process */
2758                        ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2759                                        &phy_data);
2760                        if (ret_val)
2761                                return ret_val;
2762                        phy_data &= ~CR_1000T_MS_ENABLE;
2763                        ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2764                                        phy_data);
2765                        if (ret_val)
2766                                return ret_val;
2767                }
2768
2769                ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2770                if (ret_val)
2771                        return ret_val;
2772
2773                /* load defaults for future use */
2774                hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2775                                ((phy_data & CR_1000T_MS_VALUE) ?
2776                                e1000_ms_force_master :
2777                                e1000_ms_force_slave) :
2778                                e1000_ms_auto;
2779
2780                switch (phy_ms_setting) {
2781                case e1000_ms_force_master:
2782                        phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2783                        break;
2784                case e1000_ms_force_slave:
2785                        phy_data |= CR_1000T_MS_ENABLE;
2786                        phy_data &= ~(CR_1000T_MS_VALUE);
2787                        break;
2788                case e1000_ms_auto:
2789                        phy_data &= ~CR_1000T_MS_ENABLE;
2790                default:
2791                        break;
2792                }
2793                ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2794                if (ret_val)
2795                        return ret_val;
2796        }
2797
2798        return E1000_SUCCESS;
2799}
2800
2801/*****************************************************************************
2802 * This function checks the mode of the firmware.
2803 *
2804 * returns  - true when the mode is IAMT or false.
2805 ****************************************************************************/
2806bool
2807e1000_check_mng_mode(struct e1000_hw *hw)
2808{
2809        uint32_t fwsm;
2810        DEBUGFUNC();
2811
2812        fwsm = E1000_READ_REG(hw, FWSM);
2813
2814        if (hw->mac_type == e1000_ich8lan) {
2815                if ((fwsm & E1000_FWSM_MODE_MASK) ==
2816                    (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2817                        return true;
2818        } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2819                       (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2820                        return true;
2821
2822        return false;
2823}
2824
2825static int32_t
2826e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2827{
2828        uint16_t swfw = E1000_SWFW_PHY0_SM;
2829        uint32_t reg_val;
2830        DEBUGFUNC();
2831
2832        if (e1000_is_second_port(hw))
2833                swfw = E1000_SWFW_PHY1_SM;
2834
2835        if (e1000_swfw_sync_acquire(hw, swfw))
2836                return -E1000_ERR_SWFW_SYNC;
2837
2838        reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2839                        & E1000_KUMCTRLSTA_OFFSET) | data;
2840        E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2841        udelay(2);
2842
2843        return E1000_SUCCESS;
2844}
2845
2846static int32_t
2847e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2848{
2849        uint16_t swfw = E1000_SWFW_PHY0_SM;
2850        uint32_t reg_val;
2851        DEBUGFUNC();
2852
2853        if (e1000_is_second_port(hw))
2854                swfw = E1000_SWFW_PHY1_SM;
2855
2856        if (e1000_swfw_sync_acquire(hw, swfw)) {
2857                debug("%s[%i]\n", __func__, __LINE__);
2858                return -E1000_ERR_SWFW_SYNC;
2859        }
2860
2861        /* Write register address */
2862        reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2863                        E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2864        E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2865        udelay(2);
2866
2867        /* Read the data returned */
2868        reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2869        *data = (uint16_t)reg_val;
2870
2871        return E1000_SUCCESS;
2872}
2873
2874/********************************************************************
2875* Copper link setup for e1000_phy_gg82563 series.
2876*
2877* hw - Struct containing variables accessed by shared code
2878*********************************************************************/
2879static int32_t
2880e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2881{
2882        int32_t ret_val;
2883        uint16_t phy_data;
2884        uint32_t reg_data;
2885
2886        DEBUGFUNC();
2887
2888        if (!hw->phy_reset_disable) {
2889                /* Enable CRS on TX for half-duplex operation. */
2890                ret_val = e1000_read_phy_reg(hw,
2891                                GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2892                if (ret_val)
2893                        return ret_val;
2894
2895                phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2896                /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2897                phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2898
2899                ret_val = e1000_write_phy_reg(hw,
2900                                GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2901                if (ret_val)
2902                        return ret_val;
2903
2904                /* Options:
2905                 *   MDI/MDI-X = 0 (default)
2906                 *   0 - Auto for all speeds
2907                 *   1 - MDI mode
2908                 *   2 - MDI-X mode
2909                 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2910                 */
2911                ret_val = e1000_read_phy_reg(hw,
2912                                GG82563_PHY_SPEC_CTRL, &phy_data);
2913                if (ret_val)
2914                        return ret_val;
2915
2916                phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2917
2918                switch (hw->mdix) {
2919                case 1:
2920                        phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2921                        break;
2922                case 2:
2923                        phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2924                        break;
2925                case 0:
2926                default:
2927                        phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2928                        break;
2929                }
2930
2931                /* Options:
2932                 *   disable_polarity_correction = 0 (default)
2933                 *       Automatic Correction for Reversed Cable Polarity
2934                 *   0 - Disabled
2935                 *   1 - Enabled
2936                 */
2937                phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2938                ret_val = e1000_write_phy_reg(hw,
2939                                GG82563_PHY_SPEC_CTRL, phy_data);
2940
2941                if (ret_val)
2942                        return ret_val;
2943
2944                /* SW Reset the PHY so all changes take effect */
2945                ret_val = e1000_phy_reset(hw);
2946                if (ret_val) {
2947                        DEBUGOUT("Error Resetting the PHY\n");
2948                        return ret_val;
2949                }
2950        } /* phy_reset_disable */
2951
2952        if (hw->mac_type == e1000_80003es2lan) {
2953                /* Bypass RX and TX FIFO's */
2954                ret_val = e1000_write_kmrn_reg(hw,
2955                                E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2956                                E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2957                                | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2958                if (ret_val)
2959                        return ret_val;
2960
2961                ret_val = e1000_read_phy_reg(hw,
2962                                GG82563_PHY_SPEC_CTRL_2, &phy_data);
2963                if (ret_val)
2964                        return ret_val;
2965
2966                phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2967                ret_val = e1000_write_phy_reg(hw,
2968                                GG82563_PHY_SPEC_CTRL_2, phy_data);
2969
2970                if (ret_val)
2971                        return ret_val;
2972
2973                reg_data = E1000_READ_REG(hw, CTRL_EXT);
2974                reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2975                E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2976
2977                ret_val = e1000_read_phy_reg(hw,
2978                                GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2979                if (ret_val)
2980                        return ret_val;
2981
2982        /* Do not init these registers when the HW is in IAMT mode, since the
2983         * firmware will have already initialized them.  We only initialize
2984         * them if the HW is not in IAMT mode.
2985         */
2986                if (e1000_check_mng_mode(hw) == false) {
2987                        /* Enable Electrical Idle on the PHY */
2988                        phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2989                        ret_val = e1000_write_phy_reg(hw,
2990                                        GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2991                        if (ret_val)
2992                                return ret_val;
2993
2994                        ret_val = e1000_read_phy_reg(hw,
2995                                        GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2996                        if (ret_val)
2997                                return ret_val;
2998
2999                        phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3000                        ret_val = e1000_write_phy_reg(hw,
3001                                        GG82563_PHY_KMRN_MODE_CTRL, phy_data);
3002
3003                        if (ret_val)
3004                                return ret_val;
3005                }
3006
3007                /* Workaround: Disable padding in Kumeran interface in the MAC
3008                 * and in the PHY to avoid CRC errors.
3009                 */
3010                ret_val = e1000_read_phy_reg(hw,
3011                                GG82563_PHY_INBAND_CTRL, &phy_data);
3012                if (ret_val)
3013                        return ret_val;
3014                phy_data |= GG82563_ICR_DIS_PADDING;
3015                ret_val = e1000_write_phy_reg(hw,
3016                                GG82563_PHY_INBAND_CTRL, phy_data);
3017                if (ret_val)
3018                        return ret_val;
3019        }
3020        return E1000_SUCCESS;
3021}
3022
3023/********************************************************************
3024* Copper link setup for e1000_phy_m88 series.
3025*
3026* hw - Struct containing variables accessed by shared code
3027*********************************************************************/
3028static int32_t
3029e1000_copper_link_mgp_setup(struct e1000_hw *hw)
3030{
3031        int32_t ret_val;
3032        uint16_t phy_data;
3033
3034        DEBUGFUNC();
3035
3036        if (hw->phy_reset_disable)
3037                return E1000_SUCCESS;
3038
3039        /* Enable CRS on TX. This must be set for half-duplex operation. */
3040        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3041        if (ret_val)
3042                return ret_val;
3043
3044        phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
3045
3046        /* Options:
3047         *   MDI/MDI-X = 0 (default)
3048         *   0 - Auto for all speeds
3049         *   1 - MDI mode
3050         *   2 - MDI-X mode
3051         *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
3052         */
3053        phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
3054
3055        switch (hw->mdix) {
3056        case 1:
3057                phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
3058                break;
3059        case 2:
3060                phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
3061                break;
3062        case 3:
3063                phy_data |= M88E1000_PSCR_AUTO_X_1000T;
3064                break;
3065        case 0:
3066        default:
3067                phy_data |= M88E1000_PSCR_AUTO_X_MODE;
3068                break;
3069        }
3070
3071        /* Options:
3072         *   disable_polarity_correction = 0 (default)
3073         *       Automatic Correction for Reversed Cable Polarity
3074         *   0 - Disabled
3075         *   1 - Enabled
3076         */
3077        phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
3078        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
3079        if (ret_val)
3080                return ret_val;
3081
3082        if (hw->phy_revision < M88E1011_I_REV_4) {
3083                /* Force TX_CLK in the Extended PHY Specific Control Register
3084                 * to 25MHz clock.
3085                 */
3086                ret_val = e1000_read_phy_reg(hw,
3087                                M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
3088                if (ret_val)
3089                        return ret_val;
3090
3091                phy_data |= M88E1000_EPSCR_TX_CLK_25;
3092
3093                if ((hw->phy_revision == E1000_REVISION_2) &&
3094                        (hw->phy_id == M88E1111_I_PHY_ID)) {
3095                        /* Vidalia Phy, set the downshift counter to 5x */
3096                        phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
3097                        phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
3098                        ret_val = e1000_write_phy_reg(hw,
3099                                        M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
3100                        if (ret_val)
3101                                return ret_val;
3102                } else {
3103                        /* Configure Master and Slave downshift values */
3104                        phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
3105                                        | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
3106                        phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
3107                                        | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
3108                        ret_val = e1000_write_phy_reg(hw,
3109                                        M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
3110                        if (ret_val)
3111                                return ret_val;
3112                }
3113        }
3114
3115        /* SW Reset the PHY so all changes take effect */
3116        ret_val = e1000_phy_reset(hw);
3117        if (ret_val) {
3118                DEBUGOUT("Error Resetting the PHY\n");
3119                return ret_val;
3120        }
3121
3122        return E1000_SUCCESS;
3123}
3124
3125/********************************************************************
3126* Setup auto-negotiation and flow control advertisements,
3127* and then perform auto-negotiation.
3128*
3129* hw - Struct containing variables accessed by shared code
3130*********************************************************************/
3131static int32_t
3132e1000_copper_link_autoneg(struct e1000_hw *hw)
3133{
3134        int32_t ret_val;
3135        uint16_t phy_data;
3136
3137        DEBUGFUNC();
3138
3139        /* Perform some bounds checking on the hw->autoneg_advertised
3140         * parameter.  If this variable is zero, then set it to the default.
3141         */
3142        hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
3143
3144        /* If autoneg_advertised is zero, we assume it was not defaulted
3145         * by the calling code so we set to advertise full capability.
3146         */
3147        if (hw->autoneg_advertised == 0)
3148                hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
3149
3150        /* IFE phy only supports 10/100 */
3151        if (hw->phy_type == e1000_phy_ife)
3152                hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
3153
3154        DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
3155        ret_val = e1000_phy_setup_autoneg(hw);
3156        if (ret_val) {
3157                DEBUGOUT("Error Setting up Auto-Negotiation\n");
3158                return ret_val;
3159        }
3160        DEBUGOUT("Restarting Auto-Neg\n");
3161
3162        /* Restart auto-negotiation by setting the Auto Neg Enable bit and
3163         * the Auto Neg Restart bit in the PHY control register.
3164         */
3165        ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3166        if (ret_val)
3167                return ret_val;
3168
3169        phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
3170        ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3171        if (ret_val)
3172                return ret_val;
3173
3174        /* Does the user want to wait for Auto-Neg to complete here, or
3175         * check at a later time (for example, callback routine).
3176         */
3177        /* If we do not wait for autonegtation to complete I
3178         * do not see a valid link status.
3179         * wait_autoneg_complete = 1 .
3180         */
3181        if (hw->wait_autoneg_complete) {
3182                ret_val = e1000_wait_autoneg(hw);
3183                if (ret_val) {
3184                        DEBUGOUT("Error while waiting for autoneg"
3185                                        "to complete\n");
3186                        return ret_val;
3187                }
3188        }
3189
3190        hw->get_link_status = true;
3191
3192        return E1000_SUCCESS;
3193}
3194
3195/******************************************************************************
3196* Config the MAC and the PHY after link is up.
3197*   1) Set up the MAC to the current PHY speed/duplex
3198*      if we are on 82543.  If we
3199*      are on newer silicon, we only need to configure
3200*      collision distance in the Transmit Control Register.
3201*   2) Set up flow control on the MAC to that established with
3202*      the link partner.
3203*   3) Config DSP to improve Gigabit link quality for some PHY revisions.
3204*
3205* hw - Struct containing variables accessed by shared code
3206******************************************************************************/
3207static int32_t
3208e1000_copper_link_postconfig(struct e1000_hw *hw)
3209{
3210        int32_t ret_val;
3211        DEBUGFUNC();
3212
3213        if (hw->mac_type >= e1000_82544) {
3214                e1000_config_collision_dist(hw);
3215        } else {
3216                ret_val = e1000_config_mac_to_phy(hw);
3217                if (ret_val) {
3218                        DEBUGOUT("Error configuring MAC to PHY settings\n");
3219                        return ret_val;
3220                }
3221        }
3222        ret_val = e1000_config_fc_after_link_up(hw);
3223        if (ret_val) {
3224                DEBUGOUT("Error Configuring Flow Control\n");
3225                return ret_val;
3226        }
3227        return E1000_SUCCESS;
3228}
3229
3230/******************************************************************************
3231* Detects which PHY is present and setup the speed and duplex
3232*
3233* hw - Struct containing variables accessed by shared code
3234******************************************************************************/
3235static int
3236e1000_setup_copper_link(struct e1000_hw *hw)
3237{
3238        int32_t ret_val;
3239        uint16_t i;
3240        uint16_t phy_data;
3241        uint16_t reg_data;
3242
3243        DEBUGFUNC();
3244
3245        switch (hw->mac_type) {
3246        case e1000_80003es2lan:
3247        case e1000_ich8lan:
3248                /* Set the mac to wait the maximum time between each
3249                 * iteration and increase the max iterations when
3250                 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3251                ret_val = e1000_write_kmrn_reg(hw,
3252                                GG82563_REG(0x34, 4), 0xFFFF);
3253                if (ret_val)
3254                        return ret_val;
3255                ret_val = e1000_read_kmrn_reg(hw,
3256                                GG82563_REG(0x34, 9), &reg_data);
3257                if (ret_val)
3258                        return ret_val;
3259                reg_data |= 0x3F;
3260                ret_val = e1000_write_kmrn_reg(hw,
3261                                GG82563_REG(0x34, 9), reg_data);
3262                if (ret_val)
3263                        return ret_val;
3264        default:
3265                break;
3266        }
3267
3268        /* Check if it is a valid PHY and set PHY mode if necessary. */
3269        ret_val = e1000_copper_link_preconfig(hw);
3270        if (ret_val)
3271                return ret_val;
3272        switch (hw->mac_type) {
3273        case e1000_80003es2lan:
3274                /* Kumeran registers are written-only */
3275                reg_data =
3276                E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3277                reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3278                ret_val = e1000_write_kmrn_reg(hw,
3279                                E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3280                if (ret_val)
3281                        return ret_val;
3282                break;
3283        default:
3284                break;
3285        }
3286
3287        if (hw->phy_type == e1000_phy_igp ||
3288                hw->phy_type == e1000_phy_igp_3 ||
3289                hw->phy_type == e1000_phy_igp_2) {
3290                ret_val = e1000_copper_link_igp_setup(hw);
3291                if (ret_val)
3292                        return ret_val;
3293        } else if (hw->phy_type == e1000_phy_m88 ||
3294                hw->phy_type == e1000_phy_igb) {
3295                ret_val = e1000_copper_link_mgp_setup(hw);
3296                if (ret_val)
3297                        return ret_val;
3298        } else if (hw->phy_type == e1000_phy_gg82563) {
3299                ret_val = e1000_copper_link_ggp_setup(hw);
3300                if (ret_val)
3301                        return ret_val;
3302        }
3303
3304        /* always auto */
3305        /* Setup autoneg and flow control advertisement
3306          * and perform autonegotiation */
3307        ret_val = e1000_copper_link_autoneg(hw);
3308        if (ret_val)
3309                return ret_val;
3310
3311        /* Check link status. Wait up to 100 microseconds for link to become
3312         * valid.
3313         */
3314        for (i = 0; i < 10; i++) {
3315                ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3316                if (ret_val)
3317                        return ret_val;
3318                ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3319                if (ret_val)
3320                        return ret_val;
3321
3322                if (phy_data & MII_SR_LINK_STATUS) {
3323                        /* Config the MAC and PHY after link is up */
3324                        ret_val = e1000_copper_link_postconfig(hw);
3325                        if (ret_val)
3326                                return ret_val;
3327
3328                        DEBUGOUT("Valid link established!!!\n");
3329                        return E1000_SUCCESS;
3330                }
3331                udelay(10);
3332        }
3333
3334        DEBUGOUT("Unable to establish link!!!\n");
3335        return E1000_SUCCESS;
3336}
3337
3338/******************************************************************************
3339* Configures PHY autoneg and flow control advertisement settings
3340*
3341* hw - Struct containing variables accessed by shared code
3342******************************************************************************/
3343int32_t
3344e1000_phy_setup_autoneg(struct e1000_hw *hw)
3345{
3346        int32_t ret_val;
3347        uint16_t mii_autoneg_adv_reg;
3348        uint16_t mii_1000t_ctrl_reg;
3349
3350        DEBUGFUNC();
3351
3352        /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3353        ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3354        if (ret_val)
3355                return ret_val;
3356
3357        if (hw->phy_type != e1000_phy_ife) {
3358                /* Read the MII 1000Base-T Control Register (Address 9). */
3359                ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3360                                &mii_1000t_ctrl_reg);
3361                if (ret_val)
3362                        return ret_val;
3363        } else
3364                mii_1000t_ctrl_reg = 0;
3365
3366        /* Need to parse both autoneg_advertised and fc and set up
3367         * the appropriate PHY registers.  First we will parse for
3368         * autoneg_advertised software override.  Since we can advertise
3369         * a plethora of combinations, we need to check each bit
3370         * individually.
3371         */
3372
3373        /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3374         * Advertisement Register (Address 4) and the 1000 mb speed bits in
3375         * the  1000Base-T Control Register (Address 9).
3376         */
3377        mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3378        mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3379
3380        DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3381
3382        /* Do we want to advertise 10 Mb Half Duplex? */
3383        if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3384                DEBUGOUT("Advertise 10mb Half duplex\n");
3385                mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3386        }
3387
3388        /* Do we want to advertise 10 Mb Full Duplex? */
3389        if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3390                DEBUGOUT("Advertise 10mb Full duplex\n");
3391                mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3392        }
3393
3394        /* Do we want to advertise 100 Mb Half Duplex? */
3395        if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3396                DEBUGOUT("Advertise 100mb Half duplex\n");
3397                mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3398        }
3399
3400        /* Do we want to advertise 100 Mb Full Duplex? */
3401        if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3402                DEBUGOUT("Advertise 100mb Full duplex\n");
3403                mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3404        }
3405
3406        /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3407        if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3408                DEBUGOUT
3409                    ("Advertise 1000mb Half duplex requested, request denied!\n");
3410        }
3411
3412        /* Do we want to advertise 1000 Mb Full Duplex? */
3413        if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3414                DEBUGOUT("Advertise 1000mb Full duplex\n");
3415                mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3416        }
3417
3418        /* Check for a software override of the flow control settings, and
3419         * setup the PHY advertisement registers accordingly.  If
3420         * auto-negotiation is enabled, then software will have to set the
3421         * "PAUSE" bits to the correct value in the Auto-Negotiation
3422         * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3423         *
3424         * The possible values of the "fc" parameter are:
3425         *      0:  Flow control is completely disabled
3426         *      1:  Rx flow control is enabled (we can receive pause frames
3427         *          but not send pause frames).
3428         *      2:  Tx flow control is enabled (we can send pause frames
3429         *          but we do not support receiving pause frames).
3430         *      3:  Both Rx and TX flow control (symmetric) are enabled.
3431         *  other:  No software override.  The flow control configuration
3432         *          in the EEPROM is used.
3433         */
3434        switch (hw->fc) {
3435        case e1000_fc_none:     /* 0 */
3436                /* Flow control (RX & TX) is completely disabled by a
3437                 * software over-ride.
3438                 */
3439                mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3440                break;
3441        case e1000_fc_rx_pause: /* 1 */
3442                /* RX Flow control is enabled, and TX Flow control is
3443                 * disabled, by a software over-ride.
3444                 */
3445                /* Since there really isn't a way to advertise that we are
3446                 * capable of RX Pause ONLY, we will advertise that we
3447                 * support both symmetric and asymmetric RX PAUSE.  Later
3448                 * (in e1000_config_fc_after_link_up) we will disable the
3449                 *hw's ability to send PAUSE frames.
3450                 */
3451                mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3452                break;
3453        case e1000_fc_tx_pause: /* 2 */
3454                /* TX Flow control is enabled, and RX Flow control is
3455                 * disabled, by a software over-ride.
3456                 */
3457                mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3458                mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3459                break;
3460        case e1000_fc_full:     /* 3 */
3461                /* Flow control (both RX and TX) is enabled by a software
3462                 * over-ride.
3463                 */
3464                mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3465                break;
3466        default:
3467                DEBUGOUT("Flow control param set incorrectly\n");
3468                return -E1000_ERR_CONFIG;
3469        }
3470
3471        ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3472        if (ret_val)
3473                return ret_val;
3474
3475        DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3476
3477        if (hw->phy_type != e1000_phy_ife) {
3478                ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3479                                mii_1000t_ctrl_reg);
3480                if (ret_val)
3481                        return ret_val;
3482        }
3483
3484        return E1000_SUCCESS;
3485}
3486
3487/******************************************************************************
3488* Sets the collision distance in the Transmit Control register
3489*
3490* hw - Struct containing variables accessed by shared code
3491*
3492* Link should have been established previously. Reads the speed and duplex
3493* information from the Device Status register.
3494******************************************************************************/
3495static void
3496e1000_config_collision_dist(struct e1000_hw *hw)
3497{
3498        uint32_t tctl, coll_dist;
3499
3500        DEBUGFUNC();
3501
3502        if (hw->mac_type < e1000_82543)
3503                coll_dist = E1000_COLLISION_DISTANCE_82542;
3504        else
3505                coll_dist = E1000_COLLISION_DISTANCE;
3506
3507        tctl = E1000_READ_REG(hw, TCTL);
3508
3509        tctl &= ~E1000_TCTL_COLD;
3510        tctl |= coll_dist << E1000_COLD_SHIFT;
3511
3512        E1000_WRITE_REG(hw, TCTL, tctl);
3513        E1000_WRITE_FLUSH(hw);
3514}
3515
3516/******************************************************************************
3517* Sets MAC speed and duplex settings to reflect the those in the PHY
3518*
3519* hw - Struct containing variables accessed by shared code
3520* mii_reg - data to write to the MII control register
3521*
3522* The contents of the PHY register containing the needed information need to
3523* be passed in.
3524******************************************************************************/
3525static int
3526e1000_config_mac_to_phy(struct e1000_hw *hw)
3527{
3528        uint32_t ctrl;
3529        uint16_t phy_data;
3530
3531        DEBUGFUNC();
3532
3533        /* Read the Device Control Register and set the bits to Force Speed
3534         * and Duplex.
3535         */
3536        ctrl = E1000_READ_REG(hw, CTRL);
3537        ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3538        ctrl &= ~(E1000_CTRL_ILOS);
3539        ctrl |= (E1000_CTRL_SPD_SEL);
3540
3541        /* Set up duplex in the Device Control and Transmit Control
3542         * registers depending on negotiated values.
3543         */
3544        if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3545                DEBUGOUT("PHY Read Error\n");
3546                return -E1000_ERR_PHY;
3547        }
3548        if (phy_data & M88E1000_PSSR_DPLX)
3549                ctrl |= E1000_CTRL_FD;
3550        else
3551                ctrl &= ~E1000_CTRL_FD;
3552
3553        e1000_config_collision_dist(hw);
3554
3555        /* Set up speed in the Device Control register depending on
3556         * negotiated values.
3557         */
3558        if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3559                ctrl |= E1000_CTRL_SPD_1000;
3560        else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3561                ctrl |= E1000_CTRL_SPD_100;
3562        /* Write the configured values back to the Device Control Reg. */
3563        E1000_WRITE_REG(hw, CTRL, ctrl);
3564        return 0;
3565}
3566
3567/******************************************************************************
3568 * Forces the MAC's flow control settings.
3569 *
3570 * hw - Struct containing variables accessed by shared code
3571 *
3572 * Sets the TFCE and RFCE bits in the device control register to reflect
3573 * the adapter settings. TFCE and RFCE need to be explicitly set by
3574 * software when a Copper PHY is used because autonegotiation is managed
3575 * by the PHY rather than the MAC. Software must also configure these
3576 * bits when link is forced on a fiber connection.
3577 *****************************************************************************/
3578static int
3579e1000_force_mac_fc(struct e1000_hw *hw)
3580{
3581        uint32_t ctrl;
3582
3583        DEBUGFUNC();
3584
3585        /* Get the current configuration of the Device Control Register */
3586        ctrl = E1000_READ_REG(hw, CTRL);
3587
3588        /* Because we didn't get link via the internal auto-negotiation
3589         * mechanism (we either forced link or we got link via PHY
3590         * auto-neg), we have to manually enable/disable transmit an
3591         * receive flow control.
3592         *
3593         * The "Case" statement below enables/disable flow control
3594         * according to the "hw->fc" parameter.
3595         *
3596         * The possible values of the "fc" parameter are:
3597         *      0:  Flow control is completely disabled
3598         *      1:  Rx flow control is enabled (we can receive pause
3599         *          frames but not send pause frames).
3600         *      2:  Tx flow control is enabled (we can send pause frames
3601         *          frames but we do not receive pause frames).
3602         *      3:  Both Rx and TX flow control (symmetric) is enabled.
3603         *  other:  No other values should be possible at this point.
3604         */
3605
3606        switch (hw->fc) {
3607        case e1000_fc_none:
3608                ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3609                break;
3610        case e1000_fc_rx_pause:
3611                ctrl &= (~E1000_CTRL_TFCE);
3612                ctrl |= E1000_CTRL_RFCE;
3613                break;
3614        case e1000_fc_tx_pause:
3615                ctrl &= (~E1000_CTRL_RFCE);
3616                ctrl |= E1000_CTRL_TFCE;
3617                break;
3618        case e1000_fc_full:
3619                ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3620                break;
3621        default:
3622                DEBUGOUT("Flow control param set incorrectly\n");
3623                return -E1000_ERR_CONFIG;
3624        }
3625
3626        /* Disable TX Flow Control for 82542 (rev 2.0) */
3627        if (hw->mac_type == e1000_82542_rev2_0)
3628                ctrl &= (~E1000_CTRL_TFCE);
3629
3630        E1000_WRITE_REG(hw, CTRL, ctrl);
3631        return 0;
3632}
3633
3634/******************************************************************************
3635 * Configures flow control settings after link is established
3636 *
3637 * hw - Struct containing variables accessed by shared code
3638 *
3639 * Should be called immediately after a valid link has been established.
3640 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3641 * and autonegotiation is enabled, the MAC flow control settings will be set
3642 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3643 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3644 *****************************************************************************/
3645static int32_t
3646e1000_config_fc_after_link_up(struct e1000_hw *hw)
3647{
3648        int32_t ret_val;
3649        uint16_t mii_status_reg;
3650        uint16_t mii_nway_adv_reg;
3651        uint16_t mii_nway_lp_ability_reg;
3652        uint16_t speed;
3653        uint16_t duplex;
3654
3655        DEBUGFUNC();
3656
3657        /* Check for the case where we have fiber media and auto-neg failed
3658         * so we had to force link.  In this case, we need to force the
3659         * configuration of the MAC to match the "fc" parameter.
3660         */
3661        if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3662                || ((hw->media_type == e1000_media_type_internal_serdes)
3663                && (hw->autoneg_failed))
3664                || ((hw->media_type == e1000_media_type_copper)
3665                && (!hw->autoneg))) {
3666                ret_val = e1000_force_mac_fc(hw);
3667                if (ret_val < 0) {
3668                        DEBUGOUT("Error forcing flow control settings\n");
3669                        return ret_val;
3670                }
3671        }
3672
3673        /* Check for the case where we have copper media and auto-neg is
3674         * enabled.  In this case, we need to check and see if Auto-Neg
3675         * has completed, and if so, how the PHY and link partner has
3676         * flow control configured.
3677         */
3678        if (hw->media_type == e1000_media_type_copper) {
3679                /* Read the MII Status Register and check to see if AutoNeg
3680                 * has completed.  We read this twice because this reg has
3681                 * some "sticky" (latched) bits.
3682                 */
3683                if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3684                        DEBUGOUT("PHY Read Error\n");
3685                        return -E1000_ERR_PHY;
3686                }
3687                if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3688                        DEBUGOUT("PHY Read Error\n");
3689                        return -E1000_ERR_PHY;
3690                }
3691
3692                if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3693                        /* The AutoNeg process has completed, so we now need to
3694                         * read both the Auto Negotiation Advertisement Register
3695                         * (Address 4) and the Auto_Negotiation Base Page Ability
3696                         * Register (Address 5) to determine how flow control was
3697                         * negotiated.
3698                         */
3699                        if (e1000_read_phy_reg
3700                            (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3701                                DEBUGOUT("PHY Read Error\n");
3702                                return -E1000_ERR_PHY;
3703                        }
3704                        if (e1000_read_phy_reg
3705                            (hw, PHY_LP_ABILITY,
3706                             &mii_nway_lp_ability_reg) < 0) {
3707                                DEBUGOUT("PHY Read Error\n");
3708                                return -E1000_ERR_PHY;
3709                        }
3710
3711                        /* Two bits in the Auto Negotiation Advertisement Register
3712                         * (Address 4) and two bits in the Auto Negotiation Base
3713                         * Page Ability Register (Address 5) determine flow control
3714                         * for both the PHY and the link partner.  The following
3715                         * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3716                         * 1999, describes these PAUSE resolution bits and how flow
3717                         * control is determined based upon these settings.
3718                         * NOTE:  DC = Don't Care
3719                         *
3720                         *   LOCAL DEVICE  |   LINK PARTNER
3721                         * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3722                         *-------|---------|-------|---------|--------------------
3723                         *   0   |    0    |  DC   |   DC    | e1000_fc_none
3724                         *   0   |    1    |   0   |   DC    | e1000_fc_none
3725                         *   0   |    1    |   1   |    0    | e1000_fc_none
3726                         *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3727                         *   1   |    0    |   0   |   DC    | e1000_fc_none
3728                         *   1   |   DC    |   1   |   DC    | e1000_fc_full
3729                         *   1   |    1    |   0   |    0    | e1000_fc_none
3730                         *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3731                         *
3732                         */
3733                        /* Are both PAUSE bits set to 1?  If so, this implies
3734                         * Symmetric Flow Control is enabled at both ends.  The
3735                         * ASM_DIR bits are irrelevant per the spec.
3736                         *
3737                         * For Symmetric Flow Control:
3738                         *
3739                         *   LOCAL DEVICE  |   LINK PARTNER
3740                         * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3741                         *-------|---------|-------|---------|--------------------
3742                         *   1   |   DC    |   1   |   DC    | e1000_fc_full
3743                         *
3744                         */
3745                        if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3746                            (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3747                                /* Now we need to check if the user selected RX ONLY
3748                                 * of pause frames.  In this case, we had to advertise
3749                                 * FULL flow control because we could not advertise RX
3750                                 * ONLY. Hence, we must now check to see if we need to
3751                                 * turn OFF  the TRANSMISSION of PAUSE frames.
3752                                 */
3753                                if (hw->original_fc == e1000_fc_full) {
3754                                        hw->fc = e1000_fc_full;
3755                                        DEBUGOUT("Flow Control = FULL.\r\n");
3756                                } else {
3757                                        hw->fc = e1000_fc_rx_pause;
3758                                        DEBUGOUT
3759                                            ("Flow Control = RX PAUSE frames only.\r\n");
3760                                }
3761                        }
3762                        /* For receiving PAUSE frames ONLY.
3763                         *
3764                         *   LOCAL DEVICE  |   LINK PARTNER
3765                         * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3766                         *-------|---------|-------|---------|--------------------
3767                         *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3768                         *
3769                         */
3770                        else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3771                                 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3772                                 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3773                                 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3774                        {
3775                                hw->fc = e1000_fc_tx_pause;
3776                                DEBUGOUT
3777                                    ("Flow Control = TX PAUSE frames only.\r\n");
3778                        }
3779                        /* For transmitting PAUSE frames ONLY.
3780                         *
3781                         *   LOCAL DEVICE  |   LINK PARTNER
3782                         * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3783                         *-------|---------|-------|---------|--------------------
3784                         *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3785                         *
3786                         */
3787                        else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3788                                 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3789                                 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3790                                 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3791                        {
3792                                hw->fc = e1000_fc_rx_pause;
3793                                DEBUGOUT
3794                                    ("Flow Control = RX PAUSE frames only.\r\n");
3795                        }
3796                        /* Per the IEEE spec, at this point flow control should be
3797                         * disabled.  However, we want to consider that we could
3798                         * be connected to a legacy switch that doesn't advertise
3799                         * desired flow control, but can be forced on the link
3800                         * partner.  So if we advertised no flow control, that is
3801                         * what we will resolve to.  If we advertised some kind of
3802                         * receive capability (Rx Pause Only or Full Flow Control)
3803                         * and the link partner advertised none, we will configure
3804                         * ourselves to enable Rx Flow Control only.  We can do
3805                         * this safely for two reasons:  If the link partner really
3806                         * didn't want flow control enabled, and we enable Rx, no
3807                         * harm done since we won't be receiving any PAUSE frames
3808                         * anyway.  If the intent on the link partner was to have
3809                         * flow control enabled, then by us enabling RX only, we
3810                         * can at least receive pause frames and process them.
3811                         * This is a good idea because in most cases, since we are
3812                         * predominantly a server NIC, more times than not we will
3813                         * be asked to delay transmission of packets than asking
3814                         * our link partner to pause transmission of frames.
3815                         */
3816                        else if (hw->original_fc == e1000_fc_none ||
3817                                 hw->original_fc == e1000_fc_tx_pause) {
3818                                hw->fc = e1000_fc_none;
3819                                DEBUGOUT("Flow Control = NONE.\r\n");
3820                        } else {
3821                                hw->fc = e1000_fc_rx_pause;
3822                                DEBUGOUT
3823                                    ("Flow Control = RX PAUSE frames only.\r\n");
3824                        }
3825
3826                        /* Now we need to do one last check...  If we auto-
3827                         * negotiated to HALF DUPLEX, flow control should not be
3828                         * enabled per IEEE 802.3 spec.
3829                         */
3830                        e1000_get_speed_and_duplex(hw, &speed, &duplex);
3831
3832                        if (duplex == HALF_DUPLEX)
3833                                hw->fc = e1000_fc_none;
3834
3835                        /* Now we call a subroutine to actually force the MAC
3836                         * controller to use the correct flow control settings.
3837                         */
3838                        ret_val = e1000_force_mac_fc(hw);
3839                        if (ret_val < 0) {
3840                                DEBUGOUT
3841                                    ("Error forcing flow control settings\n");
3842                                return ret_val;
3843                        }
3844                } else {
3845                        DEBUGOUT
3846                            ("Copper PHY and Auto Neg has not completed.\r\n");
3847                }
3848        }
3849        return E1000_SUCCESS;
3850}
3851
3852/******************************************************************************
3853 * Checks to see if the link status of the hardware has changed.
3854 *
3855 * hw - Struct containing variables accessed by shared code
3856 *
3857 * Called by any function that needs to check the link status of the adapter.
3858 *****************************************************************************/
3859static int
3860e1000_check_for_link(struct e1000_hw *hw)
3861{
3862        uint32_t rxcw;
3863        uint32_t ctrl;
3864        uint32_t status;
3865        uint32_t rctl;
3866        uint32_t signal;
3867        int32_t ret_val;
3868        uint16_t phy_data;
3869        uint16_t lp_capability;
3870
3871        DEBUGFUNC();
3872
3873        /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3874         * set when the optics detect a signal. On older adapters, it will be
3875         * cleared when there is a signal
3876         */
3877        ctrl = E1000_READ_REG(hw, CTRL);
3878        if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3879                signal = E1000_CTRL_SWDPIN1;
3880        else
3881                signal = 0;
3882
3883        status = E1000_READ_REG(hw, STATUS);
3884        rxcw = E1000_READ_REG(hw, RXCW);
3885        DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3886
3887        /* If we have a copper PHY then we only want to go out to the PHY
3888         * registers to see if Auto-Neg has completed and/or if our link
3889         * status has changed.  The get_link_status flag will be set if we
3890         * receive a Link Status Change interrupt or we have Rx Sequence
3891         * Errors.
3892         */
3893        if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3894                /* First we want to see if the MII Status Register reports
3895                 * link.  If so, then we want to get the current speed/duplex
3896                 * of the PHY.
3897                 * Read the register twice since the link bit is sticky.
3898                 */
3899                if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3900                        DEBUGOUT("PHY Read Error\n");
3901                        return -E1000_ERR_PHY;
3902                }
3903                if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3904                        DEBUGOUT("PHY Read Error\n");
3905                        return -E1000_ERR_PHY;
3906                }
3907
3908                if (phy_data & MII_SR_LINK_STATUS) {
3909                        hw->get_link_status = false;
3910                } else {
3911                        /* No link detected */
3912                        return -E1000_ERR_NOLINK;
3913                }
3914
3915                /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
3916                 * have Si on board that is 82544 or newer, Auto
3917                 * Speed Detection takes care of MAC speed/duplex
3918                 * configuration.  So we only need to configure Collision
3919                 * Distance in the MAC.  Otherwise, we need to force
3920                 * speed/duplex on the MAC to the current PHY speed/duplex
3921                 * settings.
3922                 */
3923                if (hw->mac_type >= e1000_82544)
3924                        e1000_config_collision_dist(hw);
3925                else {
3926                        ret_val = e1000_config_mac_to_phy(hw);
3927                        if (ret_val < 0) {
3928                                DEBUGOUT
3929                                    ("Error configuring MAC to PHY settings\n");
3930                                return ret_val;
3931                        }
3932                }
3933
3934                /* Configure Flow Control now that Auto-Neg has completed. First, we
3935                 * need to restore the desired flow control settings because we may
3936                 * have had to re-autoneg with a different link partner.
3937                 */
3938                ret_val = e1000_config_fc_after_link_up(hw);
3939                if (ret_val < 0) {
3940                        DEBUGOUT("Error configuring flow control\n");
3941                        return ret_val;
3942                }
3943
3944                /* At this point we know that we are on copper and we have
3945                 * auto-negotiated link.  These are conditions for checking the link
3946                 * parter capability register.  We use the link partner capability to
3947                 * determine if TBI Compatibility needs to be turned on or off.  If
3948                 * the link partner advertises any speed in addition to Gigabit, then
3949                 * we assume that they are GMII-based, and TBI compatibility is not
3950                 * needed. If no other speeds are advertised, we assume the link
3951                 * partner is TBI-based, and we turn on TBI Compatibility.
3952                 */
3953                if (hw->tbi_compatibility_en) {
3954                        if (e1000_read_phy_reg
3955                            (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3956                                DEBUGOUT("PHY Read Error\n");
3957                                return -E1000_ERR_PHY;
3958                        }
3959                        if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3960                                             NWAY_LPAR_10T_FD_CAPS |
3961                                             NWAY_LPAR_100TX_HD_CAPS |
3962                                             NWAY_LPAR_100TX_FD_CAPS |
3963                                             NWAY_LPAR_100T4_CAPS)) {
3964                                /* If our link partner advertises anything in addition to
3965                                 * gigabit, we do not need to enable TBI compatibility.
3966                                 */
3967                                if (hw->tbi_compatibility_on) {
3968                                        /* If we previously were in the mode, turn it off. */
3969                                        rctl = E1000_READ_REG(hw, RCTL);
3970                                        rctl &= ~E1000_RCTL_SBP;
3971                                        E1000_WRITE_REG(hw, RCTL, rctl);
3972                                        hw->tbi_compatibility_on = false;
3973                                }
3974                        } else {
3975                                /* If TBI compatibility is was previously off, turn it on. For
3976                                 * compatibility with a TBI link partner, we will store bad
3977                                 * packets. Some frames have an additional byte on the end and
3978                                 * will look like CRC errors to to the hardware.
3979                                 */
3980                                if (!hw->tbi_compatibility_on) {
3981                                        hw->tbi_compatibility_on = true;
3982                                        rctl = E1000_READ_REG(hw, RCTL);
3983                                        rctl |= E1000_RCTL_SBP;
3984                                        E1000_WRITE_REG(hw, RCTL, rctl);
3985                                }
3986                        }
3987                }
3988        }
3989        /* If we don't have link (auto-negotiation failed or link partner cannot
3990         * auto-negotiate), the cable is plugged in (we have signal), and our
3991         * link partner is not trying to auto-negotiate with us (we are receiving
3992         * idles or data), we need to force link up. We also need to give
3993         * auto-negotiation time to complete, in case the cable was just plugged
3994         * in. The autoneg_failed flag does this.
3995         */
3996        else if ((hw->media_type == e1000_media_type_fiber) &&
3997                 (!(status & E1000_STATUS_LU)) &&
3998                 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3999                 (!(rxcw & E1000_RXCW_C))) {
4000                if (hw->autoneg_failed == 0) {
4001                        hw->autoneg_failed = 1;
4002                        return 0;
4003                }
4004                DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
4005
4006                /* Disable auto-negotiation in the TXCW register */
4007                E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
4008
4009                /* Force link-up and also force full-duplex. */
4010                ctrl = E1000_READ_REG(hw, CTRL);
4011                ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
4012                E1000_WRITE_REG(hw, CTRL, ctrl);
4013
4014                /* Configure Flow Control after forcing link up. */
4015                ret_val = e1000_config_fc_after_link_up(hw);
4016                if (ret_val < 0) {
4017                        DEBUGOUT("Error configuring flow control\n");
4018                        return ret_val;
4019                }
4020        }
4021        /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
4022         * auto-negotiation in the TXCW register and disable forced link in the
4023         * Device Control register in an attempt to auto-negotiate with our link
4024         * partner.
4025         */
4026        else if ((hw->media_type == e1000_media_type_fiber) &&
4027                 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
4028                DEBUGOUT
4029                    ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
4030                E1000_WRITE_REG(hw, TXCW, hw->txcw);
4031                E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
4032        }
4033        return 0;
4034}
4035
4036/******************************************************************************
4037* Configure the MAC-to-PHY interface for 10/100Mbps
4038*
4039* hw - Struct containing variables accessed by shared code
4040******************************************************************************/
4041static int32_t
4042e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
4043{
4044        int32_t ret_val = E1000_SUCCESS;
4045        uint32_t tipg;
4046        uint16_t reg_data;
4047
4048        DEBUGFUNC();
4049
4050        reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
4051        ret_val = e1000_write_kmrn_reg(hw,
4052                        E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
4053        if (ret_val)
4054                return ret_val;
4055
4056        /* Configure Transmit Inter-Packet Gap */
4057        tipg = E1000_READ_REG(hw, TIPG);
4058        tipg &= ~E1000_TIPG_IPGT_MASK;
4059        tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
4060        E1000_WRITE_REG(hw, TIPG, tipg);
4061
4062        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
4063
4064        if (ret_val)
4065                return ret_val;
4066
4067        if (duplex == HALF_DUPLEX)
4068                reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
4069        else
4070                reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
4071
4072        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
4073
4074        return ret_val;
4075}
4076
4077static int32_t
4078e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
4079{
4080        int32_t ret_val = E1000_SUCCESS;
4081        uint16_t reg_data;
4082        uint32_t tipg;
4083
4084        DEBUGFUNC();
4085
4086        reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
4087        ret_val = e1000_write_kmrn_reg(hw,
4088                        E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
4089        if (ret_val)
4090                return ret_val;
4091
4092        /* Configure Transmit Inter-Packet Gap */
4093        tipg = E1000_READ_REG(hw, TIPG);
4094        tipg &= ~E1000_TIPG_IPGT_MASK;
4095        tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
4096        E1000_WRITE_REG(hw, TIPG, tipg);
4097
4098        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
4099
4100        if (ret_val)
4101                return ret_val;
4102
4103        reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
4104        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
4105
4106        return ret_val;
4107}
4108
4109/******************************************************************************
4110 * Detects the current speed and duplex settings of the hardware.
4111 *
4112 * hw - Struct containing variables accessed by shared code
4113 * speed - Speed of the connection
4114 * duplex - Duplex setting of the connection
4115 *****************************************************************************/
4116static int
4117e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
4118                uint16_t *duplex)
4119{
4120        uint32_t status;
4121        int32_t ret_val;
4122        uint16_t phy_data;
4123
4124        DEBUGFUNC();
4125
4126        if (hw->mac_type >= e1000_82543) {
4127                status = E1000_READ_REG(hw, STATUS);
4128                if (status & E1000_STATUS_SPEED_1000) {
4129                        *speed = SPEED_1000;
4130                        DEBUGOUT("1000 Mbs, ");
4131                } else if (status & E1000_STATUS_SPEED_100) {
4132                        *speed = SPEED_100;
4133                        DEBUGOUT("100 Mbs, ");
4134                } else {
4135                        *speed = SPEED_10;
4136                        DEBUGOUT("10 Mbs, ");
4137                }
4138
4139                if (status & E1000_STATUS_FD) {
4140                        *duplex = FULL_DUPLEX;
4141                        DEBUGOUT("Full Duplex\r\n");
4142                } else {
4143                        *duplex = HALF_DUPLEX;
4144                        DEBUGOUT(" Half Duplex\r\n");
4145                }
4146        } else {
4147                DEBUGOUT("1000 Mbs, Full Duplex\r\n");
4148                *speed = SPEED_1000;
4149                *duplex = FULL_DUPLEX;
4150        }
4151
4152        /* IGP01 PHY may advertise full duplex operation after speed downgrade
4153         * even if it is operating at half duplex.  Here we set the duplex
4154         * settings to match the duplex in the link partner's capabilities.
4155         */
4156        if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
4157                ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
4158                if (ret_val)
4159                        return ret_val;
4160
4161                if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
4162                        *duplex = HALF_DUPLEX;
4163                else {
4164                        ret_val = e1000_read_phy_reg(hw,
4165                                        PHY_LP_ABILITY, &phy_data);
4166                        if (ret_val)
4167                                return ret_val;
4168                        if ((*speed == SPEED_100 &&
4169                                !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
4170                                || (*speed == SPEED_10
4171                                && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
4172                                *duplex = HALF_DUPLEX;
4173                }
4174        }
4175
4176        if ((hw->mac_type == e1000_80003es2lan) &&
4177                (hw->media_type == e1000_media_type_copper)) {
4178                if (*speed == SPEED_1000)
4179                        ret_val = e1000_configure_kmrn_for_1000(hw);
4180                else
4181                        ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
4182                if (ret_val)
4183                        return ret_val;
4184        }
4185        return E1000_SUCCESS;
4186}
4187
4188/******************************************************************************
4189* Blocks until autoneg completes or times out (~4.5 seconds)
4190*
4191* hw - Struct containing variables accessed by shared code
4192******************************************************************************/
4193static int
4194e1000_wait_autoneg(struct e1000_hw *hw)
4195{
4196        uint16_t i;
4197        uint16_t phy_data;
4198
4199        DEBUGFUNC();
4200        DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4201
4202        /* We will wait for autoneg to complete or timeout to expire. */
4203        for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
4204                /* Read the MII Status Register and wait for Auto-Neg
4205                 * Complete bit to be set.
4206                 */
4207                if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4208                        DEBUGOUT("PHY Read Error\n");
4209                        return -E1000_ERR_PHY;
4210                }
4211                if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4212                        DEBUGOUT("PHY Read Error\n");
4213                        return -E1000_ERR_PHY;
4214                }
4215                if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4216                        DEBUGOUT("Auto-Neg complete.\n");
4217                        return 0;
4218                }
4219                mdelay(100);
4220        }
4221        DEBUGOUT("Auto-Neg timedout.\n");
4222        return -E1000_ERR_TIMEOUT;
4223}
4224
4225/******************************************************************************
4226* Raises the Management Data Clock
4227*
4228* hw - Struct containing variables accessed by shared code
4229* ctrl - Device control register's current value
4230******************************************************************************/
4231static void
4232e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4233{
4234        /* Raise the clock input to the Management Data Clock (by setting the MDC
4235         * bit), and then delay 2 microseconds.
4236         */
4237        E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4238        E1000_WRITE_FLUSH(hw);
4239        udelay(2);
4240}
4241
4242/******************************************************************************
4243* Lowers the Management Data Clock
4244*
4245* hw - Struct containing variables accessed by shared code
4246* ctrl - Device control register's current value
4247******************************************************************************/
4248static void
4249e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4250{
4251        /* Lower the clock input to the Management Data Clock (by clearing the MDC
4252         * bit), and then delay 2 microseconds.
4253         */
4254        E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4255        E1000_WRITE_FLUSH(hw);
4256        udelay(2);
4257}
4258
4259/******************************************************************************
4260* Shifts data bits out to the PHY
4261*
4262* hw - Struct containing variables accessed by shared code
4263* data - Data to send out to the PHY
4264* count - Number of bits to shift out
4265*
4266* Bits are shifted out in MSB to LSB order.
4267******************************************************************************/
4268static void
4269e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4270{
4271        uint32_t ctrl;
4272        uint32_t mask;
4273
4274        /* We need to shift "count" number of bits out to the PHY. So, the value
4275         * in the "data" parameter will be shifted out to the PHY one bit at a
4276         * time. In order to do this, "data" must be broken down into bits.
4277         */
4278        mask = 0x01;
4279        mask <<= (count - 1);
4280
4281        ctrl = E1000_READ_REG(hw, CTRL);
4282
4283        /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4284        ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4285
4286        while (mask) {
4287                /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4288                 * then raising and lowering the Management Data Clock. A "0" is
4289                 * shifted out to the PHY by setting the MDIO bit to "0" and then
4290                 * raising and lowering the clock.
4291                 */
4292                if (data & mask)
4293                        ctrl |= E1000_CTRL_MDIO;
4294                else
4295                        ctrl &= ~E1000_CTRL_MDIO;
4296
4297                E1000_WRITE_REG(hw, CTRL, ctrl);
4298                E1000_WRITE_FLUSH(hw);
4299
4300                udelay(2);
4301
4302                e1000_raise_mdi_clk(hw, &ctrl);
4303                e1000_lower_mdi_clk(hw, &ctrl);
4304
4305                mask = mask >> 1;
4306        }
4307}
4308
4309/******************************************************************************
4310* Shifts data bits in from the PHY
4311*
4312* hw - Struct containing variables accessed by shared code
4313*
4314* Bits are shifted in in MSB to LSB order.
4315******************************************************************************/
4316static uint16_t
4317e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4318{
4319        uint32_t ctrl;
4320        uint16_t data = 0;
4321        uint8_t i;
4322
4323        /* In order to read a register from the PHY, we need to shift in a total
4324         * of 18 bits from the PHY. The first two bit (turnaround) times are used
4325         * to avoid contention on the MDIO pin when a read operation is performed.
4326         * These two bits are ignored by us and thrown away. Bits are "shifted in"
4327         * by raising the input to the Management Data Clock (setting the MDC bit),
4328         * and then reading the value of the MDIO bit.
4329         */
4330        ctrl = E1000_READ_REG(hw, CTRL);
4331
4332        /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4333        ctrl &= ~E1000_CTRL_MDIO_DIR;
4334        ctrl &= ~E1000_CTRL_MDIO;
4335
4336        E1000_WRITE_REG(hw, CTRL, ctrl);
4337        E1000_WRITE_FLUSH(hw);
4338
4339        /* Raise and Lower the clock before reading in the data. This accounts for
4340         * the turnaround bits. The first clock occurred when we clocked out the
4341         * last bit of the Register Address.
4342         */
4343        e1000_raise_mdi_clk(hw, &ctrl);
4344        e1000_lower_mdi_clk(hw, &ctrl);
4345
4346        for (data = 0, i = 0; i < 16; i++) {
4347                data = data << 1;
4348                e1000_raise_mdi_clk(hw, &ctrl);
4349                ctrl = E1000_READ_REG(hw, CTRL);
4350                /* Check to see if we shifted in a "1". */
4351                if (ctrl & E1000_CTRL_MDIO)
4352                        data |= 1;
4353                e1000_lower_mdi_clk(hw, &ctrl);
4354        }
4355
4356        e1000_raise_mdi_clk(hw, &ctrl);
4357        e1000_lower_mdi_clk(hw, &ctrl);
4358
4359        return data;
4360}
4361
4362/*****************************************************************************
4363* Reads the value from a PHY register
4364*
4365* hw - Struct containing variables accessed by shared code
4366* reg_addr - address of the PHY register to read
4367******************************************************************************/
4368static int
4369e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4370{
4371        uint32_t i;
4372        uint32_t mdic = 0;
4373        const uint32_t phy_addr = 1;
4374
4375        if (reg_addr > MAX_PHY_REG_ADDRESS) {
4376                DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4377                return -E1000_ERR_PARAM;
4378        }
4379
4380        if (hw->mac_type > e1000_82543) {
4381                /* Set up Op-code, Phy Address, and register address in the MDI
4382                 * Control register.  The MAC will take care of interfacing with the
4383                 * PHY to retrieve the desired data.
4384                 */
4385                mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4386                        (phy_addr << E1000_MDIC_PHY_SHIFT) |
4387                        (E1000_MDIC_OP_READ));
4388
4389                E1000_WRITE_REG(hw, MDIC, mdic);
4390
4391                /* Poll the ready bit to see if the MDI read completed */
4392                for (i = 0; i < 64; i++) {
4393                        udelay(10);
4394                        mdic = E1000_READ_REG(hw, MDIC);
4395                        if (mdic & E1000_MDIC_READY)
4396                                break;
4397                }
4398                if (!(mdic & E1000_MDIC_READY)) {
4399                        DEBUGOUT("MDI Read did not complete\n");
4400                        return -E1000_ERR_PHY;
4401                }
4402                if (mdic & E1000_MDIC_ERROR) {
4403                        DEBUGOUT("MDI Error\n");
4404                        return -E1000_ERR_PHY;
4405                }
4406                *phy_data = (uint16_t) mdic;
4407        } else {
4408                /* We must first send a preamble through the MDIO pin to signal the
4409                 * beginning of an MII instruction.  This is done by sending 32
4410                 * consecutive "1" bits.
4411                 */
4412                e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4413
4414                /* Now combine the next few fields that are required for a read
4415                 * operation.  We use this method instead of calling the
4416                 * e1000_shift_out_mdi_bits routine five different times. The format of
4417                 * a MII read instruction consists of a shift out of 14 bits and is
4418                 * defined as follows:
4419                 *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4420                 * followed by a shift in of 18 bits.  This first two bits shifted in
4421                 * are TurnAround bits used to avoid contention on the MDIO pin when a
4422                 * READ operation is performed.  These two bits are thrown away
4423                 * followed by a shift in of 16 bits which contains the desired data.
4424                 */
4425                mdic = ((reg_addr) | (phy_addr << 5) |
4426                        (PHY_OP_READ << 10) | (PHY_SOF << 12));
4427
4428                e1000_shift_out_mdi_bits(hw, mdic, 14);
4429
4430                /* Now that we've shifted out the read command to the MII, we need to
4431                 * "shift in" the 16-bit value (18 total bits) of the requested PHY
4432                 * register address.
4433                 */
4434                *phy_data = e1000_shift_in_mdi_bits(hw);
4435        }
4436        return 0;
4437}
4438
4439/******************************************************************************
4440* Writes a value to a PHY register
4441*
4442* hw - Struct containing variables accessed by shared code
4443* reg_addr - address of the PHY register to write
4444* data - data to write to the PHY
4445******************************************************************************/
4446static int
4447e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4448{
4449        uint32_t i;
4450        uint32_t mdic = 0;
4451        const uint32_t phy_addr = 1;
4452
4453        if (reg_addr > MAX_PHY_REG_ADDRESS) {
4454                DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4455                return -E1000_ERR_PARAM;
4456        }
4457
4458        if (hw->mac_type > e1000_82543) {
4459                /* Set up Op-code, Phy Address, register address, and data intended
4460                 * for the PHY register in the MDI Control register.  The MAC will take
4461                 * care of interfacing with the PHY to send the desired data.
4462                 */
4463                mdic = (((uint32_t) phy_data) |
4464                        (reg_addr << E1000_MDIC_REG_SHIFT) |
4465                        (phy_addr << E1000_MDIC_PHY_SHIFT) |
4466                        (E1000_MDIC_OP_WRITE));
4467
4468                E1000_WRITE_REG(hw, MDIC, mdic);
4469
4470                /* Poll the ready bit to see if the MDI read completed */
4471                for (i = 0; i < 64; i++) {
4472                        udelay(10);
4473                        mdic = E1000_READ_REG(hw, MDIC);
4474                        if (mdic & E1000_MDIC_READY)
4475                                break;
4476                }
4477                if (!(mdic & E1000_MDIC_READY)) {
4478                        DEBUGOUT("MDI Write did not complete\n");
4479                        return -E1000_ERR_PHY;
4480                }
4481        } else {
4482                /* We'll need to use the SW defined pins to shift the write command
4483                 * out to the PHY. We first send a preamble to the PHY to signal the
4484                 * beginning of the MII instruction.  This is done by sending 32
4485                 * consecutive "1" bits.
4486                 */
4487                e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4488
4489                /* Now combine the remaining required fields that will indicate a
4490                 * write operation. We use this method instead of calling the
4491                 * e1000_shift_out_mdi_bits routine for each field in the command. The
4492                 * format of a MII write instruction is as follows:
4493                 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4494                 */
4495                mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4496                        (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4497                mdic <<= 16;
4498                mdic |= (uint32_t) phy_data;
4499
4500                e1000_shift_out_mdi_bits(hw, mdic, 32);
4501        }
4502        return 0;
4503}
4504
4505/******************************************************************************
4506 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4507 * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
4508 * the caller to figure out how to deal with it.
4509 *
4510 * hw - Struct containing variables accessed by shared code
4511 *
4512 * returns: - E1000_BLK_PHY_RESET
4513 *            E1000_SUCCESS
4514 *
4515 *****************************************************************************/
4516int32_t
4517e1000_check_phy_reset_block(struct e1000_hw *hw)
4518{
4519        uint32_t manc = 0;
4520        uint32_t fwsm = 0;
4521
4522        if (hw->mac_type == e1000_ich8lan) {
4523                fwsm = E1000_READ_REG(hw, FWSM);
4524                return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4525                                                : E1000_BLK_PHY_RESET;
4526        }
4527
4528        if (hw->mac_type > e1000_82547_rev_2)
4529                manc = E1000_READ_REG(hw, MANC);
4530        return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4531                E1000_BLK_PHY_RESET : E1000_SUCCESS;
4532}
4533
4534/***************************************************************************
4535 * Checks if the PHY configuration is done
4536 *
4537 * hw: Struct containing variables accessed by shared code
4538 *
4539 * returns: - E1000_ERR_RESET if fail to reset MAC
4540 *            E1000_SUCCESS at any other case.
4541 *
4542 ***************************************************************************/
4543static int32_t
4544e1000_get_phy_cfg_done(struct e1000_hw *hw)
4545{
4546        int32_t timeout = PHY_CFG_TIMEOUT;
4547        uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4548
4549        DEBUGFUNC();
4550
4551        switch (hw->mac_type) {
4552        default:
4553                mdelay(10);
4554                break;
4555
4556        case e1000_80003es2lan:
4557                /* Separate *_CFG_DONE_* bit for each port */
4558                if (e1000_is_second_port(hw))
4559                        cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4560                /* Fall Through */
4561
4562        case e1000_82571:
4563        case e1000_82572:
4564        case e1000_igb:
4565                while (timeout) {
4566                        if (hw->mac_type == e1000_igb) {
4567                                if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
4568                                        break;
4569                        } else {
4570                                if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4571                                        break;
4572                        }
4573                        mdelay(1);
4574                        timeout--;
4575                }
4576                if (!timeout) {
4577                        DEBUGOUT("MNG configuration cycle has not "
4578                                        "completed.\n");
4579                        return -E1000_ERR_RESET;
4580                }
4581                break;
4582        }
4583
4584        return E1000_SUCCESS;
4585}
4586
4587/******************************************************************************
4588* Returns the PHY to the power-on reset state
4589*
4590* hw - Struct containing variables accessed by shared code
4591******************************************************************************/
4592int32_t
4593e1000_phy_hw_reset(struct e1000_hw *hw)
4594{
4595        uint16_t swfw = E1000_SWFW_PHY0_SM;
4596        uint32_t ctrl, ctrl_ext;
4597        uint32_t led_ctrl;
4598        int32_t ret_val;
4599
4600        DEBUGFUNC();
4601
4602        /* In the case of the phy reset being blocked, it's not an error, we
4603         * simply return success without performing the reset. */
4604        ret_val = e1000_check_phy_reset_block(hw);
4605        if (ret_val)
4606                return E1000_SUCCESS;
4607
4608        DEBUGOUT("Resetting Phy...\n");
4609
4610        if (hw->mac_type > e1000_82543) {
4611                if (e1000_is_second_port(hw))
4612                        swfw = E1000_SWFW_PHY1_SM;
4613
4614                if (e1000_swfw_sync_acquire(hw, swfw)) {
4615                        DEBUGOUT("Unable to acquire swfw sync\n");
4616                        return -E1000_ERR_SWFW_SYNC;
4617                }
4618
4619                /* Read the device control register and assert the E1000_CTRL_PHY_RST
4620                 * bit. Then, take it out of reset.
4621                 */
4622                ctrl = E1000_READ_REG(hw, CTRL);
4623                E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4624                E1000_WRITE_FLUSH(hw);
4625
4626                if (hw->mac_type < e1000_82571)
4627                        udelay(10);
4628                else
4629                        udelay(100);
4630
4631                E1000_WRITE_REG(hw, CTRL, ctrl);
4632                E1000_WRITE_FLUSH(hw);
4633
4634                if (hw->mac_type >= e1000_82571)
4635                        mdelay(10);
4636
4637        } else {
4638                /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4639                 * bit to put the PHY into reset. Then, take it out of reset.
4640                 */
4641                ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4642                ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4643                ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4644                E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4645                E1000_WRITE_FLUSH(hw);
4646                mdelay(10);
4647                ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4648                E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4649                E1000_WRITE_FLUSH(hw);
4650        }
4651        udelay(150);
4652
4653        if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4654                /* Configure activity LED after PHY reset */
4655                led_ctrl = E1000_READ_REG(hw, LEDCTL);
4656                led_ctrl &= IGP_ACTIVITY_LED_MASK;
4657                led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4658                E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4659        }
4660
4661        e1000_swfw_sync_release(hw, swfw);
4662
4663        /* Wait for FW to finish PHY configuration. */
4664        ret_val = e1000_get_phy_cfg_done(hw);
4665        if (ret_val != E1000_SUCCESS)
4666                return ret_val;
4667
4668        return ret_val;
4669}
4670
4671/******************************************************************************
4672 * IGP phy init script - initializes the GbE PHY
4673 *
4674 * hw - Struct containing variables accessed by shared code
4675 *****************************************************************************/
4676static void
4677e1000_phy_init_script(struct e1000_hw *hw)
4678{
4679        uint32_t ret_val;
4680        uint16_t phy_saved_data;
4681        DEBUGFUNC();
4682
4683        if (hw->phy_init_script) {
4684                mdelay(20);
4685
4686                /* Save off the current value of register 0x2F5B to be
4687                 * restored at the end of this routine. */
4688                ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4689
4690                /* Disabled the PHY transmitter */
4691                e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4692
4693                mdelay(20);
4694
4695                e1000_write_phy_reg(hw, 0x0000, 0x0140);
4696
4697                mdelay(5);
4698
4699                switch (hw->mac_type) {
4700                case e1000_82541:
4701                case e1000_82547:
4702                        e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4703
4704                        e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4705
4706                        e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4707
4708                        e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4709
4710                        e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4711
4712                        e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4713
4714                        e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4715
4716                        e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4717
4718                        e1000_write_phy_reg(hw, 0x2010, 0x0008);
4719                        break;
4720
4721                case e1000_82541_rev_2:
4722                case e1000_82547_rev_2:
4723                        e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4724                        break;
4725                default:
4726                        break;
4727                }
4728
4729                e1000_write_phy_reg(hw, 0x0000, 0x3300);
4730
4731                mdelay(20);
4732
4733                /* Now enable the transmitter */
4734                if (!ret_val)
4735                        e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4736
4737                if (hw->mac_type == e1000_82547) {
4738                        uint16_t fused, fine, coarse;
4739
4740                        /* Move to analog registers page */
4741                        e1000_read_phy_reg(hw,
4742                                IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4743
4744                        if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4745                                e1000_read_phy_reg(hw,
4746                                        IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4747
4748                                fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4749                                coarse = fused
4750                                        & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4751
4752                                if (coarse >
4753                                        IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4754                                        coarse -=
4755                                        IGP01E1000_ANALOG_FUSE_COARSE_10;
4756                                        fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4757                                } else if (coarse
4758                                        == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4759                                        fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4760
4761                                fused = (fused
4762                                        & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4763                                        (fine
4764                                        & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4765                                        (coarse
4766                                        & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4767
4768                                e1000_write_phy_reg(hw,
4769                                        IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4770                                e1000_write_phy_reg(hw,
4771                                        IGP01E1000_ANALOG_FUSE_BYPASS,
4772                                IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4773                        }
4774                }
4775        }
4776}
4777
4778/******************************************************************************
4779* Resets the PHY
4780*
4781* hw - Struct containing variables accessed by shared code
4782*
4783* Sets bit 15 of the MII Control register
4784******************************************************************************/
4785int32_t
4786e1000_phy_reset(struct e1000_hw *hw)
4787{
4788        int32_t ret_val;
4789        uint16_t phy_data;
4790
4791        DEBUGFUNC();
4792
4793        /* In the case of the phy reset being blocked, it's not an error, we
4794         * simply return success without performing the reset. */
4795        ret_val = e1000_check_phy_reset_block(hw);
4796        if (ret_val)
4797                return E1000_SUCCESS;
4798
4799        switch (hw->phy_type) {
4800        case e1000_phy_igp:
4801        case e1000_phy_igp_2:
4802        case e1000_phy_igp_3:
4803        case e1000_phy_ife:
4804        case e1000_phy_igb:
4805                ret_val = e1000_phy_hw_reset(hw);
4806                if (ret_val)
4807                        return ret_val;
4808                break;
4809        default:
4810                ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4811                if (ret_val)
4812                        return ret_val;
4813
4814                phy_data |= MII_CR_RESET;
4815                ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4816                if (ret_val)
4817                        return ret_val;
4818
4819                udelay(1);
4820                break;
4821        }
4822
4823        if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4824                e1000_phy_init_script(hw);
4825
4826        return E1000_SUCCESS;
4827}
4828
4829static int e1000_set_phy_type (struct e1000_hw *hw)
4830{
4831        DEBUGFUNC ();
4832
4833        if (hw->mac_type == e1000_undefined)
4834                return -E1000_ERR_PHY_TYPE;
4835
4836        switch (hw->phy_id) {
4837        case M88E1000_E_PHY_ID:
4838        case M88E1000_I_PHY_ID:
4839        case M88E1011_I_PHY_ID:
4840        case M88E1111_I_PHY_ID:
4841                hw->phy_type = e1000_phy_m88;
4842                break;
4843        case IGP01E1000_I_PHY_ID:
4844                if (hw->mac_type == e1000_82541 ||
4845                        hw->mac_type == e1000_82541_rev_2 ||
4846                        hw->mac_type == e1000_82547 ||
4847                        hw->mac_type == e1000_82547_rev_2) {
4848                        hw->phy_type = e1000_phy_igp;
4849                        break;
4850                }
4851        case IGP03E1000_E_PHY_ID:
4852                hw->phy_type = e1000_phy_igp_3;
4853                break;
4854        case IFE_E_PHY_ID:
4855        case IFE_PLUS_E_PHY_ID:
4856        case IFE_C_E_PHY_ID:
4857                hw->phy_type = e1000_phy_ife;
4858                break;
4859        case GG82563_E_PHY_ID:
4860                if (hw->mac_type == e1000_80003es2lan) {
4861                        hw->phy_type = e1000_phy_gg82563;
4862                        break;
4863                }
4864        case BME1000_E_PHY_ID:
4865                hw->phy_type = e1000_phy_bm;
4866                break;
4867        case I210_I_PHY_ID:
4868                hw->phy_type = e1000_phy_igb;
4869                break;
4870                /* Fall Through */
4871        default:
4872                /* Should never have loaded on this device */
4873                hw->phy_type = e1000_phy_undefined;
4874                return -E1000_ERR_PHY_TYPE;
4875        }
4876
4877        return E1000_SUCCESS;
4878}
4879
4880/******************************************************************************
4881* Probes the expected PHY address for known PHY IDs
4882*
4883* hw - Struct containing variables accessed by shared code
4884******************************************************************************/
4885static int32_t
4886e1000_detect_gig_phy(struct e1000_hw *hw)
4887{
4888        int32_t phy_init_status, ret_val;
4889        uint16_t phy_id_high, phy_id_low;
4890        bool match = false;
4891
4892        DEBUGFUNC();
4893
4894        /* The 82571 firmware may still be configuring the PHY.  In this
4895         * case, we cannot access the PHY until the configuration is done.  So
4896         * we explicitly set the PHY values. */
4897        if (hw->mac_type == e1000_82571 ||
4898                hw->mac_type == e1000_82572) {
4899                hw->phy_id = IGP01E1000_I_PHY_ID;
4900                hw->phy_type = e1000_phy_igp_2;
4901                return E1000_SUCCESS;
4902        }
4903
4904        /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4905         * work- around that forces PHY page 0 to be set or the reads fail.
4906         * The rest of the code in this routine uses e1000_read_phy_reg to
4907         * read the PHY ID.  So for ESB-2 we need to have this set so our
4908         * reads won't fail.  If the attached PHY is not a e1000_phy_gg82563,
4909         * the routines below will figure this out as well. */
4910        if (hw->mac_type == e1000_80003es2lan)
4911                hw->phy_type = e1000_phy_gg82563;
4912
4913        /* Read the PHY ID Registers to identify which PHY is onboard. */
4914        ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4915        if (ret_val)
4916                return ret_val;
4917
4918        hw->phy_id = (uint32_t) (phy_id_high << 16);
4919        udelay(20);
4920        ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4921        if (ret_val)
4922                return ret_val;
4923
4924        hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4925        hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4926
4927        switch (hw->mac_type) {
4928        case e1000_82543:
4929                if (hw->phy_id == M88E1000_E_PHY_ID)
4930                        match = true;
4931                break;
4932        case e1000_82544:
4933                if (hw->phy_id == M88E1000_I_PHY_ID)
4934                        match = true;
4935                break;
4936        case e1000_82540:
4937        case e1000_82545:
4938        case e1000_82545_rev_3:
4939        case e1000_82546:
4940        case e1000_82546_rev_3:
4941                if (hw->phy_id == M88E1011_I_PHY_ID)
4942                        match = true;
4943                break;
4944        case e1000_82541:
4945        case e1000_82541_rev_2:
4946        case e1000_82547:
4947        case e1000_82547_rev_2:
4948                if(hw->phy_id == IGP01E1000_I_PHY_ID)
4949                        match = true;
4950
4951                break;
4952        case e1000_82573:
4953                if (hw->phy_id == M88E1111_I_PHY_ID)
4954                        match = true;
4955                break;
4956        case e1000_82574:
4957                if (hw->phy_id == BME1000_E_PHY_ID)
4958                        match = true;
4959                break;
4960        case e1000_80003es2lan:
4961                if (hw->phy_id == GG82563_E_PHY_ID)
4962                        match = true;
4963                break;
4964        case e1000_ich8lan:
4965                if (hw->phy_id == IGP03E1000_E_PHY_ID)
4966                        match = true;
4967                if (hw->phy_id == IFE_E_PHY_ID)
4968                        match = true;
4969                if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4970                        match = true;
4971                if (hw->phy_id == IFE_C_E_PHY_ID)
4972                        match = true;
4973                break;
4974        case e1000_igb:
4975                if (hw->phy_id == I210_I_PHY_ID)
4976                        match = true;
4977                break;
4978        default:
4979                DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4980                return -E1000_ERR_CONFIG;
4981        }
4982
4983        phy_init_status = e1000_set_phy_type(hw);
4984
4985        if ((match) && (phy_init_status == E1000_SUCCESS)) {
4986                DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4987                return 0;
4988        }
4989        DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4990        return -E1000_ERR_PHY;
4991}
4992
4993/*****************************************************************************
4994 * Set media type and TBI compatibility.
4995 *
4996 * hw - Struct containing variables accessed by shared code
4997 * **************************************************************************/
4998void
4999e1000_set_media_type(struct e1000_hw *hw)
5000{
5001        uint32_t status;
5002
5003        DEBUGFUNC();
5004
5005        if (hw->mac_type != e1000_82543) {
5006                /* tbi_compatibility is only valid on 82543 */
5007                hw->tbi_compatibility_en = false;
5008        }
5009
5010        switch (hw->device_id) {
5011        case E1000_DEV_ID_82545GM_SERDES:
5012        case E1000_DEV_ID_82546GB_SERDES:
5013        case E1000_DEV_ID_82571EB_SERDES:
5014        case E1000_DEV_ID_82571EB_SERDES_DUAL:
5015        case E1000_DEV_ID_82571EB_SERDES_QUAD:
5016        case E1000_DEV_ID_82572EI_SERDES:
5017        case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
5018                hw->media_type = e1000_media_type_internal_serdes;
5019                break;
5020        default:
5021                switch (hw->mac_type) {
5022                case e1000_82542_rev2_0:
5023                case e1000_82542_rev2_1:
5024                        hw->media_type = e1000_media_type_fiber;
5025                        break;
5026                case e1000_ich8lan:
5027                case e1000_82573:
5028                case e1000_82574:
5029                case e1000_igb:
5030                        /* The STATUS_TBIMODE bit is reserved or reused
5031                         * for the this device.
5032                         */
5033                        hw->media_type = e1000_media_type_copper;
5034                        break;
5035                default:
5036                        status = E1000_READ_REG(hw, STATUS);
5037                        if (status & E1000_STATUS_TBIMODE) {
5038                                hw->media_type = e1000_media_type_fiber;
5039                                /* tbi_compatibility not valid on fiber */
5040                                hw->tbi_compatibility_en = false;
5041                        } else {
5042                                hw->media_type = e1000_media_type_copper;
5043                        }
5044                        break;
5045                }
5046        }
5047}
5048
5049/**
5050 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
5051 *
5052 * e1000_sw_init initializes the Adapter private data structure.
5053 * Fields are initialized based on PCI device information and
5054 * OS network device settings (MTU size).
5055 **/
5056
5057static int
5058e1000_sw_init(struct e1000_hw *hw)
5059{
5060        int result;
5061
5062        /* PCI config space info */
5063#ifdef CONFIG_DM_ETH
5064        dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
5065        dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
5066        dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
5067                             &hw->subsystem_vendor_id);
5068        dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
5069
5070        dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
5071        dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
5072#else
5073        pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
5074        pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
5075        pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
5076                             &hw->subsystem_vendor_id);
5077        pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
5078
5079        pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
5080        pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
5081#endif
5082
5083        /* identify the MAC */
5084        result = e1000_set_mac_type(hw);
5085        if (result) {
5086                E1000_ERR(hw, "Unknown MAC Type\n");
5087                return result;
5088        }
5089
5090        switch (hw->mac_type) {
5091        default:
5092                break;
5093        case e1000_82541:
5094        case e1000_82547:
5095        case e1000_82541_rev_2:
5096        case e1000_82547_rev_2:
5097                hw->phy_init_script = 1;
5098                break;
5099        }
5100
5101        /* flow control settings */
5102        hw->fc_high_water = E1000_FC_HIGH_THRESH;
5103        hw->fc_low_water = E1000_FC_LOW_THRESH;
5104        hw->fc_pause_time = E1000_FC_PAUSE_TIME;
5105        hw->fc_send_xon = 1;
5106
5107        /* Media type - copper or fiber */
5108        hw->tbi_compatibility_en = true;
5109        e1000_set_media_type(hw);
5110
5111        if (hw->mac_type >= e1000_82543) {
5112                uint32_t status = E1000_READ_REG(hw, STATUS);
5113
5114                if (status & E1000_STATUS_TBIMODE) {
5115                        DEBUGOUT("fiber interface\n");
5116                        hw->media_type = e1000_media_type_fiber;
5117                } else {
5118                        DEBUGOUT("copper interface\n");
5119                        hw->media_type = e1000_media_type_copper;
5120                }
5121        } else {
5122                hw->media_type = e1000_media_type_fiber;
5123        }
5124
5125        hw->wait_autoneg_complete = true;
5126        if (hw->mac_type < e1000_82543)
5127                hw->report_tx_early = 0;
5128        else
5129                hw->report_tx_early = 1;
5130
5131        return E1000_SUCCESS;
5132}
5133
5134void
5135fill_rx(struct e1000_hw *hw)
5136{
5137        struct e1000_rx_desc *rd;
5138        unsigned long flush_start, flush_end;
5139
5140        rx_last = rx_tail;
5141        rd = rx_base + rx_tail;
5142        rx_tail = (rx_tail + 1) % 8;
5143        memset(rd, 0, 16);
5144        rd->buffer_addr = cpu_to_le64(virt_to_phys(packet));
5145
5146        /*
5147         * Make sure there are no stale data in WB over this area, which
5148         * might get written into the memory while the e1000 also writes
5149         * into the same memory area.
5150         */
5151        invalidate_dcache_range((unsigned long)packet,
5152                                (unsigned long)packet + 4096);
5153        /* Dump the DMA descriptor into RAM. */
5154        flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5155        flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5156        flush_dcache_range(flush_start, flush_end);
5157
5158        E1000_WRITE_REG(hw, RDT, rx_tail);
5159}
5160
5161/**
5162 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
5163 * @adapter: board private structure
5164 *
5165 * Configure the Tx unit of the MAC after a reset.
5166 **/
5167
5168static void
5169e1000_configure_tx(struct e1000_hw *hw)
5170{
5171        unsigned long tctl;
5172        unsigned long tipg, tarc;
5173        uint32_t ipgr1, ipgr2;
5174
5175        E1000_WRITE_REG(hw, TDBAL, lower_32_bits(virt_to_phys(tx_base)));
5176        E1000_WRITE_REG(hw, TDBAH, upper_32_bits(virt_to_phys(tx_base)));
5177
5178        E1000_WRITE_REG(hw, TDLEN, 128);
5179
5180        /* Setup the HW Tx Head and Tail descriptor pointers */
5181        E1000_WRITE_REG(hw, TDH, 0);
5182        E1000_WRITE_REG(hw, TDT, 0);
5183        tx_tail = 0;
5184
5185        /* Set the default values for the Tx Inter Packet Gap timer */
5186        if (hw->mac_type <= e1000_82547_rev_2 &&
5187            (hw->media_type == e1000_media_type_fiber ||
5188             hw->media_type == e1000_media_type_internal_serdes))
5189                tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
5190        else
5191                tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
5192
5193        /* Set the default values for the Tx Inter Packet Gap timer */
5194        switch (hw->mac_type) {
5195        case e1000_82542_rev2_0:
5196        case e1000_82542_rev2_1:
5197                tipg = DEFAULT_82542_TIPG_IPGT;
5198                ipgr1 = DEFAULT_82542_TIPG_IPGR1;
5199                ipgr2 = DEFAULT_82542_TIPG_IPGR2;
5200                break;
5201        case e1000_80003es2lan:
5202                ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5203                ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
5204                break;
5205        default:
5206                ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5207                ipgr2 = DEFAULT_82543_TIPG_IPGR2;
5208                break;
5209        }
5210        tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
5211        tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
5212        E1000_WRITE_REG(hw, TIPG, tipg);
5213        /* Program the Transmit Control Register */
5214        tctl = E1000_READ_REG(hw, TCTL);
5215        tctl &= ~E1000_TCTL_CT;
5216        tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
5217            (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
5218
5219        if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
5220                tarc = E1000_READ_REG(hw, TARC0);
5221                /* set the speed mode bit, we'll clear it if we're not at
5222                 * gigabit link later */
5223                /* git bit can be set to 1*/
5224        } else if (hw->mac_type == e1000_80003es2lan) {
5225                tarc = E1000_READ_REG(hw, TARC0);
5226                tarc |= 1;
5227                E1000_WRITE_REG(hw, TARC0, tarc);
5228                tarc = E1000_READ_REG(hw, TARC1);
5229                tarc |= 1;
5230                E1000_WRITE_REG(hw, TARC1, tarc);
5231        }
5232
5233
5234        e1000_config_collision_dist(hw);
5235        /* Setup Transmit Descriptor Settings for eop descriptor */
5236        hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
5237
5238        /* Need to set up RS bit */
5239        if (hw->mac_type < e1000_82543)
5240                hw->txd_cmd |= E1000_TXD_CMD_RPS;
5241        else
5242                hw->txd_cmd |= E1000_TXD_CMD_RS;
5243
5244
5245        if (hw->mac_type == e1000_igb) {
5246                E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
5247
5248                uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
5249                reg_txdctl |= 1 << 25;
5250                E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
5251                mdelay(20);
5252        }
5253
5254
5255
5256        E1000_WRITE_REG(hw, TCTL, tctl);
5257
5258
5259}
5260
5261/**
5262 * e1000_setup_rctl - configure the receive control register
5263 * @adapter: Board private structure
5264 **/
5265static void
5266e1000_setup_rctl(struct e1000_hw *hw)
5267{
5268        uint32_t rctl;
5269
5270        rctl = E1000_READ_REG(hw, RCTL);
5271
5272        rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
5273
5274        rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
5275                | E1000_RCTL_RDMTS_HALF;        /* |
5276                        (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
5277
5278        if (hw->tbi_compatibility_on == 1)
5279                rctl |= E1000_RCTL_SBP;
5280        else
5281                rctl &= ~E1000_RCTL_SBP;
5282
5283        rctl &= ~(E1000_RCTL_SZ_4096);
5284                rctl |= E1000_RCTL_SZ_2048;
5285                rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
5286        E1000_WRITE_REG(hw, RCTL, rctl);
5287}
5288
5289/**
5290 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5291 * @adapter: board private structure
5292 *
5293 * Configure the Rx unit of the MAC after a reset.
5294 **/
5295static void
5296e1000_configure_rx(struct e1000_hw *hw)
5297{
5298        unsigned long rctl, ctrl_ext;
5299        rx_tail = 0;
5300
5301        /* make sure receives are disabled while setting up the descriptors */
5302        rctl = E1000_READ_REG(hw, RCTL);
5303        E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
5304        if (hw->mac_type >= e1000_82540) {
5305                /* Set the interrupt throttling rate.  Value is calculated
5306                 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
5307#define MAX_INTS_PER_SEC        8000
5308#define DEFAULT_ITR             1000000000/(MAX_INTS_PER_SEC * 256)
5309                E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
5310        }
5311
5312        if (hw->mac_type >= e1000_82571) {
5313                ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5314                /* Reset delay timers after every interrupt */
5315                ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5316                E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5317                E1000_WRITE_FLUSH(hw);
5318        }
5319        /* Setup the Base and Length of the Rx Descriptor Ring */
5320        E1000_WRITE_REG(hw, RDBAL, lower_32_bits(virt_to_phys(rx_base)));
5321        E1000_WRITE_REG(hw, RDBAH, upper_32_bits(virt_to_phys(rx_base)));
5322
5323        E1000_WRITE_REG(hw, RDLEN, 128);
5324
5325        /* Setup the HW Rx Head and Tail Descriptor Pointers */
5326        E1000_WRITE_REG(hw, RDH, 0);
5327        E1000_WRITE_REG(hw, RDT, 0);
5328        /* Enable Receives */
5329
5330        if (hw->mac_type == e1000_igb) {
5331
5332                uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
5333                reg_rxdctl |= 1 << 25;
5334                E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
5335                mdelay(20);
5336        }
5337
5338        E1000_WRITE_REG(hw, RCTL, rctl);
5339
5340        fill_rx(hw);
5341}
5342
5343/**************************************************************************
5344POLL - Wait for a frame
5345***************************************************************************/
5346static int
5347_e1000_poll(struct e1000_hw *hw)
5348{
5349        struct e1000_rx_desc *rd;
5350        unsigned long inval_start, inval_end;
5351        uint32_t len;
5352
5353        /* return true if there's an ethernet packet ready to read */
5354        rd = rx_base + rx_last;
5355
5356        /* Re-load the descriptor from RAM. */
5357        inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5358        inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5359        invalidate_dcache_range(inval_start, inval_end);
5360
5361        if (!(rd->status & E1000_RXD_STAT_DD))
5362                return 0;
5363        /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
5364        /* Packet received, make sure the data are re-loaded from RAM. */
5365        len = le16_to_cpu(rd->length);
5366        invalidate_dcache_range((unsigned long)packet,
5367                                (unsigned long)packet +
5368                                roundup(len, ARCH_DMA_MINALIGN));
5369        return len;
5370}
5371
5372static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length)
5373{
5374        void *nv_packet = (void *)txpacket;
5375        struct e1000_tx_desc *txp;
5376        int i = 0;
5377        unsigned long flush_start, flush_end;
5378
5379        txp = tx_base + tx_tail;
5380        tx_tail = (tx_tail + 1) % 8;
5381
5382        txp->buffer_addr = cpu_to_le64(virt_to_phys(nv_packet));
5383        txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5384        txp->upper.data = 0;
5385
5386        /* Dump the packet into RAM so e1000 can pick them. */
5387        flush_dcache_range((unsigned long)nv_packet,
5388                           (unsigned long)nv_packet +
5389                           roundup(length, ARCH_DMA_MINALIGN));
5390        /* Dump the descriptor into RAM as well. */
5391        flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
5392        flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5393        flush_dcache_range(flush_start, flush_end);
5394
5395        E1000_WRITE_REG(hw, TDT, tx_tail);
5396
5397        E1000_WRITE_FLUSH(hw);
5398        while (1) {
5399                invalidate_dcache_range(flush_start, flush_end);
5400                if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
5401                        break;
5402                if (i++ > TOUT_LOOP) {
5403                        DEBUGOUT("e1000: tx timeout\n");
5404                        return 0;
5405                }
5406                udelay(10);     /* give the nic a chance to write to the register */
5407        }
5408        return 1;
5409}
5410
5411static void
5412_e1000_disable(struct e1000_hw *hw)
5413{
5414        /* Turn off the ethernet interface */
5415        E1000_WRITE_REG(hw, RCTL, 0);
5416        E1000_WRITE_REG(hw, TCTL, 0);
5417
5418        /* Clear the transmit ring */
5419        E1000_WRITE_REG(hw, TDH, 0);
5420        E1000_WRITE_REG(hw, TDT, 0);
5421
5422        /* Clear the receive ring */
5423        E1000_WRITE_REG(hw, RDH, 0);
5424        E1000_WRITE_REG(hw, RDT, 0);
5425
5426        mdelay(10);
5427}
5428
5429/*reset function*/
5430static inline int
5431e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6])
5432{
5433        e1000_reset_hw(hw);
5434        if (hw->mac_type >= e1000_82544)
5435                E1000_WRITE_REG(hw, WUC, 0);
5436
5437        return e1000_init_hw(hw, enetaddr);
5438}
5439
5440static int
5441_e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6])
5442{
5443        int ret_val = 0;
5444
5445        ret_val = e1000_reset(hw, enetaddr);
5446        if (ret_val < 0) {
5447                if ((ret_val == -E1000_ERR_NOLINK) ||
5448                    (ret_val == -E1000_ERR_TIMEOUT)) {
5449                        E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val);
5450                } else {
5451                        E1000_ERR(hw, "Hardware Initialization Failed\n");
5452                }
5453                return ret_val;
5454        }
5455        e1000_configure_tx(hw);
5456        e1000_setup_rctl(hw);
5457        e1000_configure_rx(hw);
5458        return 0;
5459}
5460
5461/******************************************************************************
5462 * Gets the current PCI bus type of hardware
5463 *
5464 * hw - Struct containing variables accessed by shared code
5465 *****************************************************************************/
5466void e1000_get_bus_type(struct e1000_hw *hw)
5467{
5468        uint32_t status;
5469
5470        switch (hw->mac_type) {
5471        case e1000_82542_rev2_0:
5472        case e1000_82542_rev2_1:
5473                hw->bus_type = e1000_bus_type_pci;
5474                break;
5475        case e1000_82571:
5476        case e1000_82572:
5477        case e1000_82573:
5478        case e1000_82574:
5479        case e1000_80003es2lan:
5480        case e1000_ich8lan:
5481        case e1000_igb:
5482                hw->bus_type = e1000_bus_type_pci_express;
5483                break;
5484        default:
5485                status = E1000_READ_REG(hw, STATUS);
5486                hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5487                                e1000_bus_type_pcix : e1000_bus_type_pci;
5488                break;
5489        }
5490}
5491
5492#ifndef CONFIG_DM_ETH
5493/* A list of all registered e1000 devices */
5494static LIST_HEAD(e1000_hw_list);
5495#endif
5496
5497#ifdef CONFIG_DM_ETH
5498static int e1000_init_one(struct e1000_hw *hw, int cardnum,
5499                          struct udevice *devno, unsigned char enetaddr[6])
5500#else
5501static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
5502                          unsigned char enetaddr[6])
5503#endif
5504{
5505        u32 val;
5506
5507        /* Assign the passed-in values */
5508#ifdef CONFIG_DM_ETH
5509        hw->pdev = devno;
5510#else
5511        hw->pdev = devno;
5512#endif
5513        hw->cardnum = cardnum;
5514
5515        /* Print a debug message with the IO base address */
5516#ifdef CONFIG_DM_ETH
5517        dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val);
5518#else
5519        pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5520#endif
5521        E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
5522
5523        /* Try to enable I/O accesses and bus-mastering */
5524        val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5525#ifdef CONFIG_DM_ETH
5526        dm_pci_write_config32(devno, PCI_COMMAND, val);
5527#else
5528        pci_write_config_dword(devno, PCI_COMMAND, val);
5529#endif
5530
5531        /* Make sure it worked */
5532#ifdef CONFIG_DM_ETH
5533        dm_pci_read_config32(devno, PCI_COMMAND, &val);
5534#else
5535        pci_read_config_dword(devno, PCI_COMMAND, &val);
5536#endif
5537        if (!(val & PCI_COMMAND_MEMORY)) {
5538                E1000_ERR(hw, "Can't enable I/O memory\n");
5539                return -ENOSPC;
5540        }
5541        if (!(val & PCI_COMMAND_MASTER)) {
5542                E1000_ERR(hw, "Can't enable bus-mastering\n");
5543                return -EPERM;
5544        }
5545
5546        /* Are these variables needed? */
5547        hw->fc = e1000_fc_default;
5548        hw->original_fc = e1000_fc_default;
5549        hw->autoneg_failed = 0;
5550        hw->autoneg = 1;
5551        hw->get_link_status = true;
5552#ifndef CONFIG_E1000_NO_NVM
5553        hw->eeprom_semaphore_present = true;
5554#endif
5555#ifdef CONFIG_DM_ETH
5556        hw->hw_addr = dm_pci_map_bar(devno,     PCI_BASE_ADDRESS_0,
5557                                                PCI_REGION_MEM);
5558#else
5559        hw->hw_addr = pci_map_bar(devno,        PCI_BASE_ADDRESS_0,
5560                                                PCI_REGION_MEM);
5561#endif
5562        hw->mac_type = e1000_undefined;
5563
5564        /* MAC and Phy settings */
5565        if (e1000_sw_init(hw) < 0) {
5566                E1000_ERR(hw, "Software init failed\n");
5567                return -EIO;
5568        }
5569        if (e1000_check_phy_reset_block(hw))
5570                E1000_ERR(hw, "PHY Reset is blocked!\n");
5571
5572        /* Basic init was OK, reset the hardware and allow SPI access */
5573        e1000_reset_hw(hw);
5574
5575#ifndef CONFIG_E1000_NO_NVM
5576        /* Validate the EEPROM and get chipset information */
5577        if (e1000_init_eeprom_params(hw)) {
5578                E1000_ERR(hw, "EEPROM is invalid!\n");
5579                return -EINVAL;
5580        }
5581        if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
5582            e1000_validate_eeprom_checksum(hw))
5583                return -ENXIO;
5584        e1000_read_mac_addr(hw, enetaddr);
5585#endif
5586        e1000_get_bus_type(hw);
5587
5588#ifndef CONFIG_E1000_NO_NVM
5589        printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n       ",
5590               enetaddr[0], enetaddr[1], enetaddr[2],
5591               enetaddr[3], enetaddr[4], enetaddr[5]);
5592#else
5593        memset(enetaddr, 0, 6);
5594        printf("e1000: no NVM\n");
5595#endif
5596
5597        return 0;
5598}
5599
5600/* Put the name of a device in a string */
5601static void e1000_name(char *str, int cardnum)
5602{
5603        sprintf(str, "e1000#%u", cardnum);
5604}
5605
5606#ifndef CONFIG_DM_ETH
5607/**************************************************************************
5608TRANSMIT - Transmit a frame
5609***************************************************************************/
5610static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
5611{
5612        struct e1000_hw *hw = nic->priv;
5613
5614        return _e1000_transmit(hw, txpacket, length);
5615}
5616
5617/**************************************************************************
5618DISABLE - Turn off ethernet interface
5619***************************************************************************/
5620static void
5621e1000_disable(struct eth_device *nic)
5622{
5623        struct e1000_hw *hw = nic->priv;
5624
5625        _e1000_disable(hw);
5626}
5627
5628/**************************************************************************
5629INIT - set up ethernet interface(s)
5630***************************************************************************/
5631static int
5632e1000_init(struct eth_device *nic, struct bd_info *bis)
5633{
5634        struct e1000_hw *hw = nic->priv;
5635
5636        return _e1000_init(hw, nic->enetaddr);
5637}
5638
5639static int
5640e1000_poll(struct eth_device *nic)
5641{
5642        struct e1000_hw *hw = nic->priv;
5643        int len;
5644
5645        len = _e1000_poll(hw);
5646        if (len) {
5647                net_process_received_packet((uchar *)packet, len);
5648                fill_rx(hw);
5649        }
5650
5651        return len ? 1 : 0;
5652}
5653#endif /* !CONFIG_DM_ETH */
5654
5655#ifdef CONFIG_DM_ETH
5656static int e1000_write_hwaddr(struct udevice *dev)
5657#else
5658static int e1000_write_hwaddr(struct eth_device *dev)
5659#endif
5660{
5661#ifndef CONFIG_E1000_NO_NVM
5662        unsigned char current_mac[6];
5663#ifdef CONFIG_DM_ETH
5664        struct eth_pdata *plat = dev_get_plat(dev);
5665        struct e1000_hw *hw = dev_get_priv(dev);
5666        u8 *mac = plat->enetaddr;
5667#else
5668        struct e1000_hw *hw = dev->priv;
5669        u8 *mac = dev->enetaddr;
5670#endif
5671        uint16_t data[3];
5672        int ret_val, i;
5673
5674        DEBUGOUT("%s: mac=%pM\n", __func__, mac);
5675
5676        if ((hw->eeprom.type == e1000_eeprom_invm) &&
5677            !(E1000_READ_REG(hw, EECD) & E1000_EECD_FLASH_DETECTED_I210))
5678                return -ENOSYS;
5679
5680        memset(current_mac, 0, 6);
5681
5682        /* Read from EEPROM, not from registers, to make sure
5683         * the address is persistently configured
5684         */
5685        ret_val = e1000_read_mac_addr_from_eeprom(hw, current_mac);
5686        DEBUGOUT("%s: current mac=%pM\n", __func__, current_mac);
5687
5688        /* Only write to EEPROM if the given address is different or
5689         * reading the current address failed
5690         */
5691        if (!ret_val && memcmp(current_mac, mac, 6) == 0)
5692                return 0;
5693
5694        for (i = 0; i < 3; ++i)
5695                data[i] = mac[i * 2 + 1] << 8 | mac[i * 2];
5696
5697        ret_val = e1000_write_eeprom_srwr(hw, 0x0, 3, data);
5698
5699        if (!ret_val)
5700                ret_val = e1000_update_eeprom_checksum_i210(hw);
5701
5702        return ret_val;
5703#else
5704        return 0;
5705#endif
5706}
5707
5708#ifndef CONFIG_DM_ETH
5709/**************************************************************************
5710PROBE - Look for an adapter, this routine's visible to the outside
5711You should omit the last argument struct pci_device * for a non-PCI NIC
5712***************************************************************************/
5713int
5714e1000_initialize(struct bd_info * bis)
5715{
5716        unsigned int i;
5717        pci_dev_t devno;
5718        int ret;
5719
5720        DEBUGFUNC();
5721
5722        /* Find and probe all the matching PCI devices */
5723        for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5724                /*
5725                 * These will never get freed due to errors, this allows us to
5726                 * perform SPI EEPROM programming from U-Boot, for example.
5727                 */
5728                struct eth_device *nic = malloc(sizeof(*nic));
5729                struct e1000_hw *hw = malloc(sizeof(*hw));
5730                if (!nic || !hw) {
5731                        printf("e1000#%u: Out of Memory!\n", i);
5732                        free(nic);
5733                        free(hw);
5734                        continue;
5735                }
5736
5737                /* Make sure all of the fields are initially zeroed */
5738                memset(nic, 0, sizeof(*nic));
5739                memset(hw, 0, sizeof(*hw));
5740                nic->priv = hw;
5741
5742                /* Generate a card name */
5743                e1000_name(nic->name, i);
5744                hw->name = nic->name;
5745
5746                ret = e1000_init_one(hw, i, devno, nic->enetaddr);
5747                if (ret)
5748                        continue;
5749                list_add_tail(&hw->list_node, &e1000_hw_list);
5750
5751                hw->nic = nic;
5752
5753                /* Set up the function pointers and register the device */
5754                nic->init = e1000_init;
5755                nic->recv = e1000_poll;
5756                nic->send = e1000_transmit;
5757                nic->halt = e1000_disable;
5758                nic->write_hwaddr = e1000_write_hwaddr;
5759                eth_register(nic);
5760        }
5761
5762        return i;
5763}
5764
5765struct e1000_hw *e1000_find_card(unsigned int cardnum)
5766{
5767        struct e1000_hw *hw;
5768
5769        list_for_each_entry(hw, &e1000_hw_list, list_node)
5770                if (hw->cardnum == cardnum)
5771                        return hw;
5772
5773        return NULL;
5774}
5775#endif /* !CONFIG_DM_ETH */
5776
5777#ifdef CONFIG_CMD_E1000
5778static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc,
5779                    char *const argv[])
5780{
5781        unsigned char *mac = NULL;
5782#ifdef CONFIG_DM_ETH
5783        struct eth_pdata *plat;
5784        struct udevice *dev;
5785        char name[30];
5786        int ret;
5787#endif
5788#if !defined(CONFIG_DM_ETH) || defined(CONFIG_E1000_SPI)
5789        struct e1000_hw *hw;
5790#endif
5791        int cardnum;
5792
5793        if (argc < 3) {
5794                cmd_usage(cmdtp);
5795                return 1;
5796        }
5797
5798        /* Make sure we can find the requested e1000 card */
5799        cardnum = simple_strtoul(argv[1], NULL, 10);
5800#ifdef CONFIG_DM_ETH
5801        e1000_name(name, cardnum);
5802        ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
5803        if (!ret) {
5804                plat = dev_get_plat(dev);
5805                mac = plat->enetaddr;
5806        }
5807#else
5808        hw = e1000_find_card(cardnum);
5809        if (hw)
5810                mac = hw->nic->enetaddr;
5811#endif
5812        if (!mac) {
5813                printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5814                return 1;
5815        }
5816
5817        if (!strcmp(argv[2], "print-mac-address")) {
5818                printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5819                        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5820                return 0;
5821        }
5822
5823#ifdef CONFIG_E1000_SPI
5824#ifdef CONFIG_DM_ETH
5825        hw = dev_get_priv(dev);
5826#endif
5827        /* Handle the "SPI" subcommand */
5828        if (!strcmp(argv[2], "spi"))
5829                return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5830#endif
5831
5832        cmd_usage(cmdtp);
5833        return 1;
5834}
5835
5836U_BOOT_CMD(
5837        e1000, 7, 0, do_e1000,
5838        "Intel e1000 controller management",
5839        /*  */"<card#> print-mac-address\n"
5840#ifdef CONFIG_E1000_SPI
5841        "e1000 <card#> spi show [<offset> [<length>]]\n"
5842        "e1000 <card#> spi dump <addr> <offset> <length>\n"
5843        "e1000 <card#> spi program <addr> <offset> <length>\n"
5844        "e1000 <card#> spi checksum [update]\n"
5845#endif
5846        "       - Manage the Intel E1000 PCI device"
5847);
5848#endif /* not CONFIG_CMD_E1000 */
5849
5850#ifdef CONFIG_DM_ETH
5851static int e1000_eth_start(struct udevice *dev)
5852{
5853        struct eth_pdata *plat = dev_get_plat(dev);
5854        struct e1000_hw *hw = dev_get_priv(dev);
5855
5856        return _e1000_init(hw, plat->enetaddr);
5857}
5858
5859static void e1000_eth_stop(struct udevice *dev)
5860{
5861        struct e1000_hw *hw = dev_get_priv(dev);
5862
5863        _e1000_disable(hw);
5864}
5865
5866static int e1000_eth_send(struct udevice *dev, void *packet, int length)
5867{
5868        struct e1000_hw *hw = dev_get_priv(dev);
5869        int ret;
5870
5871        ret = _e1000_transmit(hw, packet, length);
5872
5873        return ret ? 0 : -ETIMEDOUT;
5874}
5875
5876static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp)
5877{
5878        struct e1000_hw *hw = dev_get_priv(dev);
5879        int len;
5880
5881        len = _e1000_poll(hw);
5882        if (len)
5883                *packetp = packet;
5884
5885        return len ? len : -EAGAIN;
5886}
5887
5888static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length)
5889{
5890        struct e1000_hw *hw = dev_get_priv(dev);
5891
5892        fill_rx(hw);
5893
5894        return 0;
5895}
5896
5897static int e1000_eth_probe(struct udevice *dev)
5898{
5899        struct eth_pdata *plat = dev_get_plat(dev);
5900        struct e1000_hw *hw = dev_get_priv(dev);
5901        int ret;
5902
5903        hw->name = dev->name;
5904        ret = e1000_init_one(hw, trailing_strtol(dev->name),
5905                             dev, plat->enetaddr);
5906        if (ret < 0) {
5907                printf(pr_fmt("failed to initialize card: %d\n"), ret);
5908                return ret;
5909        }
5910
5911        return 0;
5912}
5913
5914static int e1000_eth_bind(struct udevice *dev)
5915{
5916        char name[20];
5917
5918        /*
5919         * A simple way to number the devices. When device tree is used this
5920         * is unnecessary, but when the device is just discovered on the PCI
5921         * bus we need a name. We could instead have the uclass figure out
5922         * which devices are different and number them.
5923         */
5924        e1000_name(name, num_cards++);
5925
5926        return device_set_name(dev, name);
5927}
5928
5929static const struct eth_ops e1000_eth_ops = {
5930        .start  = e1000_eth_start,
5931        .send   = e1000_eth_send,
5932        .recv   = e1000_eth_recv,
5933        .stop   = e1000_eth_stop,
5934        .free_pkt = e1000_free_pkt,
5935        .write_hwaddr = e1000_write_hwaddr,
5936};
5937
5938static const struct udevice_id e1000_eth_ids[] = {
5939        { .compatible = "intel,e1000" },
5940        { }
5941};
5942
5943U_BOOT_DRIVER(eth_e1000) = {
5944        .name   = "eth_e1000",
5945        .id     = UCLASS_ETH,
5946        .of_match = e1000_eth_ids,
5947        .bind   = e1000_eth_bind,
5948        .probe  = e1000_eth_probe,
5949        .ops    = &e1000_eth_ops,
5950        .priv_auto      = sizeof(struct e1000_hw),
5951        .plat_auto      = sizeof(struct eth_pdata),
5952};
5953
5954U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);
5955#endif
5956