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10#include <common.h>
11#include <dm.h>
12#include <pci.h>
13#include <asm/global_data.h>
14#include <asm/io.h>
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19
20struct phytium_pcie {
21 void *cfg_base;
22};
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32static int phytium_pci_skip_dev(pci_dev_t parent)
33{
34 unsigned char pos, id;
35 unsigned long addr = 0x40000000;
36 unsigned short capreg;
37 unsigned char port_type;
38
39 addr += PCI_BUS(parent) << 20;
40 addr += PCI_DEV(parent) << 15;
41 addr += PCI_FUNC(parent) << 12;
42
43 pos = 0x34;
44 while (1) {
45 pos = readb(addr + pos);
46 if (pos < 0x40)
47 break;
48 pos &= ~3;
49 id = readb(addr + pos);
50 if (id == 0xff)
51 break;
52 if (id == 0x10) {
53 capreg = readw(addr + pos + 2);
54 port_type = (capreg >> 4) & 0xf;
55 if (port_type == 0x6 || port_type == 0x4)
56 return 1;
57 else
58 return 0;
59 }
60 pos += 1;
61 }
62 return 0;
63}
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79static int pci_phytium_conf_address(const struct udevice *bus, pci_dev_t bdf,
80 uint offset, void **paddress)
81{
82 struct phytium_pcie *pcie = dev_get_priv(bus);
83 void *addr;
84 pci_dev_t bdf_parent;
85
86 unsigned int bus_no = PCI_BUS(bdf);
87 unsigned int dev_no = PCI_DEV(bdf);
88
89 bdf_parent = PCI_BDF((bus_no - 1), 0, 0);
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91 addr = pcie->cfg_base;
92 addr += PCI_BUS(bdf) << 20;
93 addr += PCI_DEV(bdf) << 15;
94 addr += PCI_FUNC(bdf) << 12;
95
96 if (bus_no > 0 && dev_no > 0) {
97 if ((readb(addr + PCI_HEADER_TYPE) & 0x7f) !=
98 PCI_HEADER_TYPE_BRIDGE)
99 return -ENODEV;
100 if (phytium_pci_skip_dev(bdf_parent))
101 return -ENODEV;
102 }
103
104 addr += offset;
105 *paddress = addr;
106
107 return 0;
108}
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122static int pci_phytium_read_config(const struct udevice *bus, pci_dev_t bdf,
123 uint offset, ulong *valuep,
124 enum pci_size_t size)
125{
126 return pci_generic_mmap_read_config(bus, pci_phytium_conf_address,
127 bdf, offset, valuep, size);
128}
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142static int pci_phytium_write_config(struct udevice *bus, pci_dev_t bdf,
143 uint offset, ulong value,
144 enum pci_size_t size)
145{
146 return pci_generic_mmap_write_config(bus, pci_phytium_conf_address,
147 bdf, offset, value, size);
148}
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160static int pci_phytium_of_to_plat(struct udevice *dev)
161{
162 struct phytium_pcie *pcie = dev_get_priv(dev);
163 struct fdt_resource reg_res;
164
165 DECLARE_GLOBAL_DATA_PTR;
166
167 int err;
168
169 err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
170 0, ®_res);
171 if (err < 0) {
172 pr_err("\"reg\" resource not found\n");
173 return err;
174 }
175
176 pcie->cfg_base = map_physmem(reg_res.start,
177 fdt_resource_size(®_res),
178 MAP_NOCACHE);
179
180 return 0;
181}
182
183static const struct dm_pci_ops pci_phytium_ops = {
184 .read_config = pci_phytium_read_config,
185 .write_config = pci_phytium_write_config,
186};
187
188static const struct udevice_id pci_phytium_ids[] = {
189 { .compatible = "phytium,pcie-host-1.0" },
190 { }
191};
192
193U_BOOT_DRIVER(pci_phytium) = {
194 .name = "pci_phytium",
195 .id = UCLASS_PCI,
196 .of_match = pci_phytium_ids,
197 .ops = &pci_phytium_ops,
198 .of_to_plat = pci_phytium_of_to_plat,
199 .priv_auto = sizeof(struct phytium_pcie),
200};
201