LXR uboot/drivers/spi/tegra210

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * NVIDIA Tegra210 QSPI controller driver
   4 *
   5 * (C) Copyright 2015-2020 NVIDIA Corporation <www.nvidia.com>
   6 *
   7 */
   8
   9#include <common.h>
  10#include <dm.h>
  11#include <log.h>
  12#include <time.h>
  13#include <asm/global_data.h>
  14#include <asm/io.h>
  15#include <asm/arch/clock.h>
  16#include <asm/arch-tegra/clk_rst.h>
  17#include <spi.h>
  18#include <fdtdec.h>
  19#include <linux/bitops.h>
  20#include <linux/delay.h>
  21#include "tegra_spi.h"
  22
  23DECLARE_GLOBAL_DATA_PTR;
  24
  25/* COMMAND1 */
  26#define QSPI_CMD1_GO                    BIT(31)
  27#define QSPI_CMD1_M_S                   BIT(30)
  28#define QSPI_CMD1_MODE_MASK             GENMASK(1,0)
  29#define QSPI_CMD1_MODE_SHIFT            28
  30#define QSPI_CMD1_CS_SEL_MASK           GENMASK(1,0)
  31#define QSPI_CMD1_CS_SEL_SHIFT          26
  32#define QSPI_CMD1_CS_POL_INACTIVE0      BIT(22)
  33#define QSPI_CMD1_CS_SW_HW              BIT(21)
  34#define QSPI_CMD1_CS_SW_VAL             BIT(20)
  35#define QSPI_CMD1_IDLE_SDA_MASK         GENMASK(1,0)
  36#define QSPI_CMD1_IDLE_SDA_SHIFT        18
  37#define QSPI_CMD1_BIDIR                 BIT(17)
  38#define QSPI_CMD1_LSBI_FE               BIT(16)
  39#define QSPI_CMD1_LSBY_FE               BIT(15)
  40#define QSPI_CMD1_BOTH_EN_BIT           BIT(14)
  41#define QSPI_CMD1_BOTH_EN_BYTE          BIT(13)
  42#define QSPI_CMD1_RX_EN                 BIT(12)
  43#define QSPI_CMD1_TX_EN                 BIT(11)
  44#define QSPI_CMD1_PACKED                BIT(5)
  45#define QSPI_CMD1_BITLEN_MASK           GENMASK(4,0)
  46#define QSPI_CMD1_BITLEN_SHIFT          0
  47
  48/* COMMAND2 */
  49#define QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT        10
  50#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(14,10)
  51#define QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT        0
  52#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(7,0)
  53
  54/* TRANSFER STATUS */
  55#define QSPI_XFER_STS_RDY               BIT(30)
  56
  57/* FIFO STATUS */
  58#define QSPI_FIFO_STS_CS_INACTIVE       BIT(31)
  59#define QSPI_FIFO_STS_FRAME_END         BIT(30)
  60#define QSPI_FIFO_STS_RX_FIFO_FLUSH     BIT(15)
  61#define QSPI_FIFO_STS_TX_FIFO_FLUSH     BIT(14)
  62#define QSPI_FIFO_STS_ERR               BIT(8)
  63#define QSPI_FIFO_STS_TX_FIFO_OVF       BIT(7)
  64#define QSPI_FIFO_STS_TX_FIFO_UNR       BIT(6)
  65#define QSPI_FIFO_STS_RX_FIFO_OVF       BIT(5)
  66#define QSPI_FIFO_STS_RX_FIFO_UNR       BIT(4)
  67#define QSPI_FIFO_STS_TX_FIFO_FULL      BIT(3)
  68#define QSPI_FIFO_STS_TX_FIFO_EMPTY     BIT(2)
  69#define QSPI_FIFO_STS_RX_FIFO_FULL      BIT(1)
  70#define QSPI_FIFO_STS_RX_FIFO_EMPTY     BIT(0)
  71
  72#define QSPI_TIMEOUT            1000
  73
  74struct qspi_regs {
  75        u32 command1;   /* 000:QSPI_COMMAND1 register */
  76        u32 command2;   /* 004:QSPI_COMMAND2 register */
  77        u32 timing1;    /* 008:QSPI_CS_TIM1 register */
  78        u32 timing2;    /* 00c:QSPI_CS_TIM2 register */
  79        u32 xfer_status;/* 010:QSPI_TRANS_STATUS register */
  80        u32 fifo_status;/* 014:QSPI_FIFO_STATUS register */
  81        u32 tx_data;    /* 018:QSPI_TX_DATA register */
  82        u32 rx_data;    /* 01c:QSPI_RX_DATA register */
  83        u32 dma_ctl;    /* 020:QSPI_DMA_CTL register */
  84        u32 dma_blk;    /* 024:QSPI_DMA_BLK register */
  85        u32 rsvd[56];   /* 028-107 reserved */
  86        u32 tx_fifo;    /* 108:QSPI_FIFO1 register */
  87        u32 rsvd2[31];  /* 10c-187 reserved */
  88        u32 rx_fifo;    /* 188:QSPI_FIFO2 register */
  89        u32 spare_ctl;  /* 18c:QSPI_SPARE_CTRL register */
  90};
  91
  92struct tegra210_qspi_priv {
  93        struct qspi_regs *regs;
  94        unsigned int freq;
  95        unsigned int mode;
  96        int periph_id;
  97        int valid;
  98        int last_transaction_us;
  99};
 100
 101static int tegra210_qspi_of_to_plat(struct udevice *bus)
 102{
 103        struct tegra_spi_plat *plat = dev_get_plat(bus);
 104
 105        plat->base = dev_read_addr(bus);
 106        plat->periph_id = clock_decode_periph_id(bus);
 107
 108        if (plat->periph_id == PERIPH_ID_NONE) {
 109                debug("%s: could not decode periph id %d\n", __func__,
 110                      plat->periph_id);
 111                return -FDT_ERR_NOTFOUND;
 112        }
 113
 114        /* Use 500KHz as a suitable default */
 115        plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
 116                                               500000);
 117        plat->deactivate_delay_us = dev_read_u32_default(bus,
 118                                                         "spi-deactivate-delay",
 119                                                         0);
 120        debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
 121              __func__, plat->base, plat->periph_id, plat->frequency,
 122              plat->deactivate_delay_us);
 123
 124        return 0;
 125}
 126
 127static int tegra210_qspi_probe(struct udevice *bus)
 128{
 129        struct tegra_spi_plat *plat = dev_get_plat(bus);
 130        struct tegra210_qspi_priv *priv = dev_get_priv(bus);
 131
 132        priv->regs = (struct qspi_regs *)plat->base;
 133        struct qspi_regs *regs = priv->regs;
 134
 135        priv->last_transaction_us = timer_get_us();
 136        priv->freq = plat->frequency;
 137        priv->periph_id = plat->periph_id;
 138
 139        debug("%s: Freq = %u, id = %d\n", __func__, priv->freq,
 140              priv->periph_id);
 141        /* Change SPI clock to correct frequency, PLLP_OUT0 source */
 142        clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
 143
 144        /* Set tap delays here, clock change above resets QSPI controller */
 145        u32 reg = (0x09 << QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT) |
 146                   (0x0C << QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT);
 147        writel(reg, &regs->command2);
 148        debug("%s: COMMAND2 = %08x\n", __func__, readl(&regs->command2));
 149
 150        return 0;
 151}
 152
 153static int tegra210_qspi_claim_bus(struct udevice *dev)
 154{
 155        struct udevice *bus = dev->parent;
 156        struct tegra210_qspi_priv *priv = dev_get_priv(bus);
 157        struct qspi_regs *regs = priv->regs;
 158
 159        debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
 160
 161        /* Set master mode and sw controlled CS */
 162        setbits_le32(&regs->command1, QSPI_CMD1_M_S | QSPI_CMD1_CS_SW_HW |
 163                     (priv->mode << QSPI_CMD1_MODE_SHIFT));
 164        debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
 165
 166        return 0;
 167}
 168
 169/**
 170 * Activate the CS by driving it LOW
 171 *
 172 * @param slave Pointer to spi_slave to which controller has to
 173 *              communicate with
 174 */
 175static void spi_cs_activate(struct udevice *dev)
 176{
 177        struct udevice *bus = dev->parent;
 178        struct tegra_spi_plat *pdata = dev_get_plat(bus);
 179        struct tegra210_qspi_priv *priv = dev_get_priv(bus);
 180
 181        /* If it's too soon to do another transaction, wait */
 182        if (pdata->deactivate_delay_us &&
 183            priv->last_transaction_us) {
 184                ulong delay_us;         /* The delay completed so far */
 185                delay_us = timer_get_us() - priv->last_transaction_us;
 186                if (delay_us < pdata->deactivate_delay_us)
 187                        udelay(pdata->deactivate_delay_us - delay_us);
 188        }
 189
 190        clrbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
 191}
 192
 193/**
 194 * Deactivate the CS by driving it HIGH
 195 *
 196 * @param slave Pointer to spi_slave to which controller has to
 197 *              communicate with
 198 */
 199static void spi_cs_deactivate(struct udevice *dev)
 200{
 201        struct udevice *bus = dev->parent;
 202        struct tegra_spi_plat *pdata = dev_get_plat(bus);
 203        struct tegra210_qspi_priv *priv = dev_get_priv(bus);
 204
 205        setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
 206
 207        /* Remember time of this transaction so we can honour the bus delay */
 208        if (pdata->deactivate_delay_us)
 209                priv->last_transaction_us = timer_get_us();
 210
 211        debug("Deactivate CS, bus '%s'\n", bus->name);
 212}
 213
 214static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen,
 215                             const void *data_out, void *data_in,
 216                             unsigned long flags)
 217{
 218        struct udevice *bus = dev->parent;
 219        struct tegra210_qspi_priv *priv = dev_get_priv(bus);
 220        struct qspi_regs *regs = priv->regs;
 221        u32 reg, tmpdout, tmpdin = 0;
 222        const u8 *dout = data_out;
 223        u8 *din = data_in;
 224        int num_bytes, tm, ret;
 225
 226        debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
 227              __func__, dev_seq(bus), spi_chip_select(dev), dout, din, bitlen);
 228        if (bitlen % 8)
 229                return -1;
 230        num_bytes = bitlen / 8;
 231
 232        ret = 0;
 233
 234        /* clear all error status bits */
 235        reg = readl(&regs->fifo_status);
 236        writel(reg, &regs->fifo_status);
 237
 238        /* flush RX/TX FIFOs */
 239        setbits_le32(&regs->fifo_status,
 240                     (QSPI_FIFO_STS_RX_FIFO_FLUSH |
 241                      QSPI_FIFO_STS_TX_FIFO_FLUSH));
 242
 243        tm = QSPI_TIMEOUT;
 244        while ((tm && readl(&regs->fifo_status) &
 245                      (QSPI_FIFO_STS_RX_FIFO_FLUSH |
 246                       QSPI_FIFO_STS_TX_FIFO_FLUSH))) {
 247                tm--;
 248                udelay(1);
 249        }
 250
 251        if (!tm) {
 252                printf("%s: timeout during QSPI FIFO flush!\n",
 253                       __func__);
 254                return -1;
 255        }
 256
 257        /*
 258         * Notes:
 259         *   1. don't set LSBY_FE, so no need to swap bytes from/to TX/RX FIFOs;
 260         *   2. don't set RX_EN and TX_EN yet.
 261         *      (SW needs to make sure that while programming the blk_size,
 262         *       tx_en and rx_en bits must be zero)
 263         *      [TODO] I (Yen Lin) have problems when both RX/TX EN bits are set
 264         *             i.e., both dout and din are not NULL.
 265         */
 266        clrsetbits_le32(&regs->command1,
 267                        (QSPI_CMD1_LSBI_FE | QSPI_CMD1_LSBY_FE |
 268                         QSPI_CMD1_RX_EN | QSPI_CMD1_TX_EN),
 269                        (spi_chip_select(dev) << QSPI_CMD1_CS_SEL_SHIFT));
 270
 271        /* set xfer size to 1 block (32 bits) */
 272        writel(0, &regs->dma_blk);
 273
 274        if (flags & SPI_XFER_BEGIN)
 275                spi_cs_activate(dev);
 276
 277        /* handle data in 32-bit chunks */
 278        while (num_bytes > 0) {
 279                int bytes;
 280
 281                tmpdout = 0;
 282                bytes = (num_bytes > 4) ?  4 : num_bytes;
 283
 284                if (dout != NULL) {
 285                        memcpy((void *)&tmpdout, (void *)dout, bytes);
 286                        dout += bytes;
 287                        num_bytes -= bytes;
 288                        writel(tmpdout, &regs->tx_fifo);
 289                        setbits_le32(&regs->command1, QSPI_CMD1_TX_EN);
 290                }
 291
 292                if (din != NULL)
 293                        setbits_le32(&regs->command1, QSPI_CMD1_RX_EN);
 294
 295                /* clear ready bit */
 296                setbits_le32(&regs->xfer_status, QSPI_XFER_STS_RDY);
 297
 298                clrsetbits_le32(&regs->command1,
 299                                QSPI_CMD1_BITLEN_MASK << QSPI_CMD1_BITLEN_SHIFT,
 300                                (bytes * 8 - 1) << QSPI_CMD1_BITLEN_SHIFT);
 301
 302                /* Need to stabilize other reg bits before GO bit set.
 303                 * As per the TRM:
 304                 * "For successful operation at various freq combinations,
 305                 * a minimum of 4-5 spi_clk cycle delay might be required
 306                 * before enabling the PIO or DMA bits. The worst case delay
 307                 * calculation can be done considering slowest qspi_clk as
 308                 * 1MHz. Based on that 1us delay should be enough before
 309                 * enabling PIO or DMA." Padded another 1us for safety.
 310                 */
 311                udelay(2);
 312                setbits_le32(&regs->command1, QSPI_CMD1_GO);
 313                udelay(1);
 314
 315                /*
 316                 * Wait for SPI transmit FIFO to empty, or to time out.
 317                 * The RX FIFO status will be read and cleared last
 318                 */
 319                for (tm = 0; tm < QSPI_TIMEOUT; ++tm) {
 320                        u32 fifo_status, xfer_status;
 321
 322                        xfer_status = readl(&regs->xfer_status);
 323                        if (!(xfer_status & QSPI_XFER_STS_RDY))
 324                                continue;
 325
 326                        fifo_status = readl(&regs->fifo_status);
 327                        if (fifo_status & QSPI_FIFO_STS_ERR) {
 328                                debug("%s: got a fifo error: ", __func__);
 329                                if (fifo_status & QSPI_FIFO_STS_TX_FIFO_OVF)
 330                                        debug("tx FIFO overflow ");
 331                                if (fifo_status & QSPI_FIFO_STS_TX_FIFO_UNR)
 332                                        debug("tx FIFO underrun ");
 333                                if (fifo_status & QSPI_FIFO_STS_RX_FIFO_OVF)
 334                                        debug("rx FIFO overflow ");
 335                                if (fifo_status & QSPI_FIFO_STS_RX_FIFO_UNR)
 336                                        debug("rx FIFO underrun ");
 337                                if (fifo_status & QSPI_FIFO_STS_TX_FIFO_FULL)
 338                                        debug("tx FIFO full ");
 339                                if (fifo_status & QSPI_FIFO_STS_TX_FIFO_EMPTY)
 340                                        debug("tx FIFO empty ");
 341                                if (fifo_status & QSPI_FIFO_STS_RX_FIFO_FULL)
 342                                        debug("rx FIFO full ");
 343                                if (fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)
 344                                        debug("rx FIFO empty ");
 345                                debug("\n");
 346                                break;
 347                        }
 348
 349                        if (!(fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)) {
 350                                tmpdin = readl(&regs->rx_fifo);
 351                                if (din != NULL) {
 352                                        memcpy(din, &tmpdin, bytes);
 353                                        din += bytes;
 354                                        num_bytes -= bytes;
 355                                }
 356                        }
 357                        break;
 358                }
 359
 360                if (tm >= QSPI_TIMEOUT)
 361                        ret = tm;
 362
 363                /* clear ACK RDY, etc. bits */
 364                writel(readl(&regs->fifo_status), &regs->fifo_status);
 365        }
 366
 367        if (flags & SPI_XFER_END)
 368                spi_cs_deactivate(dev);
 369
 370        debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
 371              __func__, tmpdin, readl(&regs->fifo_status));
 372
 373        if (ret) {
 374                printf("%s: timeout during SPI transfer, tm %d\n",
 375                       __func__, ret);
 376                return -1;
 377        }
 378
 379        return ret;
 380}
 381
 382static int tegra210_qspi_set_speed(struct udevice *bus, uint speed)
 383{
 384        struct tegra_spi_plat *plat = dev_get_plat(bus);
 385        struct tegra210_qspi_priv *priv = dev_get_priv(bus);
 386
 387        if (speed > plat->frequency)
 388                speed = plat->frequency;
 389        priv->freq = speed;
 390        debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
 391
 392        return 0;
 393}
 394
 395static int tegra210_qspi_set_mode(struct udevice *bus, uint mode)
 396{
 397        struct tegra210_qspi_priv *priv = dev_get_priv(bus);
 398
 399        priv->mode = mode;
 400        debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
 401
 402        return 0;
 403}
 404
 405static const struct dm_spi_ops tegra210_qspi_ops = {
 406        .claim_bus      = tegra210_qspi_claim_bus,
 407        .xfer           = tegra210_qspi_xfer,
 408        .set_speed      = tegra210_qspi_set_speed,
 409        .set_mode       = tegra210_qspi_set_mode,
 410        /*
 411         * cs_info is not needed, since we require all chip selects to be
 412         * in the device tree explicitly
 413         */
 414};
 415
 416static const struct udevice_id tegra210_qspi_ids[] = {
 417        { .compatible = "nvidia,tegra210-qspi" },
 418        { }
 419};
 420
 421U_BOOT_DRIVER(tegra210_qspi) = {
 422        .name = "tegra210-qspi",
 423        .id = UCLASS_SPI,
 424        .of_match = tegra210_qspi_ids,
 425        .ops = &tegra210_qspi_ops,
 426        .of_to_plat = tegra210_qspi_of_to_plat,
 427        .plat_auto      = sizeof(struct tegra_spi_plat),
 428        .priv_auto      = sizeof(struct tegra210_qspi_priv),
 429        .per_child_auto = sizeof(struct spi_slave),
 430        .probe = tegra210_qspi_probe,
 431};
 432