1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2020 Cortina Access Inc. 4 * 5 * Configuration for Cortina-Access Presidio board 6 */ 7 8#ifndef __PRESIDIO_ASIC_H 9#define __PRESIDIO_ASIC_H 10 11#define CONFIG_REMAKE_ELF 12 13#define CONFIG_SUPPORT_RAW_INITRD 14 15#define CONFIG_SYS_INIT_SP_ADDR 0x00100000 16#define CONFIG_SYS_BOOTM_LEN 0x00c00000 17 18/* Generic Timer Definitions */ 19#define COUNTER_FREQUENCY 25000000 20#define CONFIG_SYS_TIMER_RATE COUNTER_FREQUENCY 21#define CONFIG_SYS_TIMER_COUNTER 0xf4321008 22 23/* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE 24 * does not yet support DT. Thus define it here. 25 */ 26#define CONFIG_GICV2 27#define GICD_BASE 0xf7011000 28#define GICC_BASE 0xf7012000 29 30/* Size of malloc() pool */ 31#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) 32 33#define CONFIG_SYS_TIMER_BASE 0xf4321000 34 35/* Use external clock source */ 36#define PRESIDIO_APB_CLK 125000000 37#define CORTINA_PER_IO_FREQ PRESIDIO_APB_CLK 38 39/* Cortina Serial Configuration */ 40#define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK) 41#define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \ 42 (void *)CONFIG_SYS_SERIAL1} 43 44#define CONFIG_SYS_SERIAL0 PER_UART0_CFG 45#define CONFIG_SYS_SERIAL1 PER_UART1_CFG 46 47/* BOOTP options */ 48#define CONFIG_BOOTP_BOOTFILESIZE 49 50/* Miscellaneous configurable options */ 51#define CONFIG_SYS_LOAD_ADDR (DDR_BASE + 0x10000000) 52#define CONFIG_LAST_STAGE_INIT 53 54/* SDRAM Bank #1 */ 55#define DDR_BASE 0x00000000 56#define PHYS_SDRAM_1 DDR_BASE 57#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */ 58#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 59 60/* Console I/O Buffer Size */ 61#define CONFIG_SYS_CBSIZE 256 62#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 63 sizeof(CONFIG_SYS_PROMPT) + 16) 64#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 65 66#define KSEG1_ATU_XLAT(x) (x) 67 68/* HW REG ADDR */ 69#define NI_READ_POLL_COUNT 1000 70#define CA_NI_MDIO_REG_BASE 0xF4338 71#define NI_HV_GLB_MAC_ADDR_CFG0_OFFSET 0x010 72#define NI_HV_GLB_MAC_ADDR_CFG1_OFFSET 0x014 73#define NI_HV_PT_BASE 0x400 74#define NI_HV_XRAM_BASE 0x820 75#define GLOBAL_BLOCK_RESET_OFFSET 0x04 76#define GLOBAL_GLOBAL_CONFIG_OFFSET 0x20 77#define GLOBAL_IO_DRIVE_CONTROL_OFFSET 0x4c 78 79/* max command args */ 80#define CONFIG_SYS_MAXARGS 64 81#define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0" 82 83/* nand driver parameters */ 84#ifdef CONFIG_TARGET_PRESIDIO_ASIC 85 #define CONFIG_SYS_NAND_ONFI_DETECTION 86 #define CONFIG_SYS_MAX_NAND_DEVICE 1 87 #define CONFIG_SYS_NAND_MAX_CHIPS 1 88 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE 89 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 90#endif 91 92#endif /* __PRESIDIO_ASIC_H */ 93