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11#ifndef __TISCI_PROTOCOL_H
12#define __TISCI_PROTOCOL_H
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23#include <linux/bitops.h>
24struct ti_sci_version_info {
25 u8 abi_major;
26 u8 abi_minor;
27 u16 firmware_revision;
28 char firmware_description[32];
29};
30
31struct ti_sci_handle;
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50struct ti_sci_board_ops {
51 int (*board_config)(const struct ti_sci_handle *handle,
52 u64 addr, u32 size);
53 int (*board_config_rm)(const struct ti_sci_handle *handle,
54 u64 addr, u32 size);
55 int (*board_config_security)(const struct ti_sci_handle *handle,
56 u64 addr, u32 size);
57 int (*board_config_pm)(const struct ti_sci_handle *handle,
58 u64 addr, u32 size);
59};
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122struct ti_sci_dev_ops {
123 int (*get_device)(const struct ti_sci_handle *handle, u32 id);
124 int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id);
125 int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
126 int (*idle_device_exclusive)(const struct ti_sci_handle *handle,
127 u32 id);
128 int (*put_device)(const struct ti_sci_handle *handle, u32 id);
129 int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
130 int (*get_context_loss_count)(const struct ti_sci_handle *handle,
131 u32 id, u32 *count);
132 int (*is_idle)(const struct ti_sci_handle *handle, u32 id,
133 bool *requested_state);
134 int (*is_stop)(const struct ti_sci_handle *handle, u32 id,
135 bool *req_state, bool *current_state);
136 int (*is_on)(const struct ti_sci_handle *handle, u32 id,
137 bool *req_state, bool *current_state);
138 int (*is_transitioning)(const struct ti_sci_handle *handle, u32 id,
139 bool *current_state);
140 int (*set_device_resets)(const struct ti_sci_handle *handle, u32 id,
141 u32 reset_state);
142 int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id,
143 u32 *reset_state);
144 int (*release_exclusive_devices)(const struct ti_sci_handle *handle);
145};
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196struct ti_sci_clk_ops {
197 int (*get_clock)(const struct ti_sci_handle *handle, u32 did, u8 cid,
198 bool needs_ssc, bool can_change_freq,
199 bool enable_input_term);
200 int (*idle_clock)(const struct ti_sci_handle *handle, u32 did, u8 cid);
201 int (*put_clock)(const struct ti_sci_handle *handle, u32 did, u8 cid);
202 int (*is_auto)(const struct ti_sci_handle *handle, u32 did, u8 cid,
203 bool *req_state);
204 int (*is_on)(const struct ti_sci_handle *handle, u32 did, u8 cid,
205 bool *req_state, bool *current_state);
206 int (*is_off)(const struct ti_sci_handle *handle, u32 did, u8 cid,
207 bool *req_state, bool *current_state);
208 int (*set_parent)(const struct ti_sci_handle *handle, u32 did, u8 cid,
209 u8 parent_id);
210 int (*get_parent)(const struct ti_sci_handle *handle, u32 did, u8 cid,
211 u8 *parent_id);
212 int (*get_num_parents)(const struct ti_sci_handle *handle, u32 did,
213 u8 cid, u8 *num_parents);
214 int (*get_best_match_freq)(const struct ti_sci_handle *handle, u32 did,
215 u8 cid, u64 min_freq, u64 target_freq,
216 u64 max_freq, u64 *match_freq);
217 int (*set_freq)(const struct ti_sci_handle *handle, u32 did, u8 cid,
218 u64 min_freq, u64 target_freq, u64 max_freq);
219 int (*get_freq)(const struct ti_sci_handle *handle, u32 did, u8 cid,
220 u64 *current_freq);
221};
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240struct ti_sci_rm_core_ops {
241 int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id,
242 u8 subtype, u16 *range_start, u16 *range_num);
243 int (*get_range_from_shost)(const struct ti_sci_handle *handle,
244 u32 dev_id, u8 subtype, u8 s_host,
245 u16 *range_start, u16 *range_num);
246};
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256struct ti_sci_core_ops {
257 int (*reboot_device)(const struct ti_sci_handle *handle);
258 int (*query_msmc)(const struct ti_sci_handle *handle,
259 u64 *msmc_start, u64 *msmc_end);
260};
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283struct ti_sci_proc_ops {
284 int (*proc_request)(const struct ti_sci_handle *handle, u8 pid);
285 int (*proc_release)(const struct ti_sci_handle *handle, u8 pid);
286 int (*proc_handover)(const struct ti_sci_handle *handle, u8 pid,
287 u8 hid);
288 int (*set_proc_boot_cfg)(const struct ti_sci_handle *handle, u8 pid,
289 u64 bv, u32 cfg_set, u32 cfg_clr);
290 int (*set_proc_boot_ctrl)(const struct ti_sci_handle *handle, u8 pid,
291 u32 ctrl_set, u32 ctrl_clr);
292 int (*proc_auth_boot_image)(const struct ti_sci_handle *handle,
293 u64 *image_addr, u32 *image_size);
294 int (*get_proc_boot_status)(const struct ti_sci_handle *handle, u8 pid,
295 u64 *bv, u32 *cfg_flags, u32 *ctrl_flags,
296 u32 *sts_flags);
297 int (*proc_shutdown_no_wait)(const struct ti_sci_handle *handle,
298 u8 pid);
299};
300
301#define TI_SCI_RING_MODE_RING (0)
302#define TI_SCI_RING_MODE_MESSAGE (1)
303#define TI_SCI_RING_MODE_CREDENTIALS (2)
304#define TI_SCI_RING_MODE_QM (3)
305
306#define TI_SCI_MSG_UNUSED_SECONDARY_HOST TI_SCI_RM_NULL_U8
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309#define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0)
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311#define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1)
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313#define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2)
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315#define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3)
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317#define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4)
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319#define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5)
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321#define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
322 (TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
323 TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
324 TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
325 TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
326 TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID)
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332struct ti_sci_rm_ringacc_ops {
333 int (*config)(const struct ti_sci_handle *handle,
334 u32 valid_params, u16 nav_id, u16 index,
335 u32 addr_lo, u32 addr_hi, u32 count, u8 mode,
336 u8 size, u8 order_id
337 );
338};
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353struct ti_sci_rm_psil_ops {
354 int (*pair)(const struct ti_sci_handle *handle, u32 nav_id,
355 u32 src_thread, u32 dst_thread);
356 int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id,
357 u32 src_thread, u32 dst_thread);
358};
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360
361#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR 2
362#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB 3
363#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR 10
364#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR 11
365#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR 12
366#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR 13
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368
369#define TI_SCI_RM_UDMAP_ATYPE_PHYS 0
370#define TI_SCI_RM_UDMAP_ATYPE_INTERMEDIATE 1
371#define TI_SCI_RM_UDMAP_ATYPE_VIRTUAL 2
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373
374#define TI_SCI_RM_UDMAP_SCHED_PRIOR_HIGH 0
375#define TI_SCI_RM_UDMAP_SCHED_PRIOR_MEDHIGH 1
376#define TI_SCI_RM_UDMAP_SCHED_PRIOR_MEDLOW 2
377#define TI_SCI_RM_UDMAP_SCHED_PRIOR_LOW 3
378
379#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0
380#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2
381
382#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES 1
383#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2
384#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3
385
386#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_TCHAN 0
387#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN 1
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389
390#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0)
391#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1)
392#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID BIT(2)
393#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID BIT(3)
394#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID BIT(4)
395#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID BIT(5)
396#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6)
397#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7)
398#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8)
399#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14)
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407struct ti_sci_msg_rm_udmap_tx_ch_cfg {
408 u32 valid_params;
409#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID BIT(9)
410#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID BIT(10)
411#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11)
412#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12)
413#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13)
414#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID BIT(15)
415#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID BIT(16)
416 u16 nav_id;
417 u16 index;
418 u8 tx_pause_on_err;
419 u8 tx_filt_einfo;
420 u8 tx_filt_pswords;
421 u8 tx_atype;
422 u8 tx_chan_type;
423 u8 tx_supr_tdpkt;
424 u16 tx_fetch_size;
425 u8 tx_credit_count;
426 u16 txcq_qnum;
427 u8 tx_priority;
428 u8 tx_qos;
429 u8 tx_orderid;
430 u16 fdepth;
431 u8 tx_sched_priority;
432 u8 tx_burst_size;
433 u8 tx_tdtype;
434 u8 extended_ch_type;
435};
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443struct ti_sci_msg_rm_udmap_rx_ch_cfg {
444 u32 valid_params;
445#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9)
446#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID BIT(10)
447#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11)
448#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID BIT(12)
449 u16 nav_id;
450 u16 index;
451 u16 rx_fetch_size;
452 u16 rxcq_qnum;
453 u8 rx_priority;
454 u8 rx_qos;
455 u8 rx_orderid;
456 u8 rx_sched_priority;
457 u16 flowid_start;
458 u16 flowid_cnt;
459 u8 rx_pause_on_err;
460 u8 rx_atype;
461 u8 rx_chan_type;
462 u8 rx_ignore_short;
463 u8 rx_ignore_long;
464 u8 rx_burst_size;
465};
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473struct ti_sci_msg_rm_udmap_flow_cfg {
474 u32 valid_params;
475#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID BIT(0)
476#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID BIT(1)
477#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID BIT(2)
478#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID BIT(3)
479#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID BIT(4)
480#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID BIT(5)
481#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID BIT(6)
482#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID BIT(7)
483#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID BIT(8)
484#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID BIT(9)
485#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID BIT(10)
486#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID BIT(11)
487#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID BIT(12)
488#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID BIT(13)
489#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID BIT(14)
490#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID BIT(15)
491#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID BIT(16)
492#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID BIT(17)
493#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID BIT(18)
494 u16 nav_id;
495 u16 flow_index;
496 u8 rx_einfo_present;
497 u8 rx_psinfo_present;
498 u8 rx_error_handling;
499 u8 rx_desc_type;
500 u16 rx_sop_offset;
501 u16 rx_dest_qnum;
502 u8 rx_src_tag_hi;
503 u8 rx_src_tag_lo;
504 u8 rx_dest_tag_hi;
505 u8 rx_dest_tag_lo;
506 u8 rx_src_tag_hi_sel;
507 u8 rx_src_tag_lo_sel;
508 u8 rx_dest_tag_hi_sel;
509 u8 rx_dest_tag_lo_sel;
510 u16 rx_fdq0_sz0_qnum;
511 u16 rx_fdq1_qnum;
512 u16 rx_fdq2_qnum;
513 u16 rx_fdq3_qnum;
514 u8 rx_ps_location;
515};
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523struct ti_sci_rm_udmap_ops {
524 int (*tx_ch_cfg)(const struct ti_sci_handle *handle,
525 const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params);
526 int (*rx_ch_cfg)(const struct ti_sci_handle *handle,
527 const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params);
528 int (*rx_flow_cfg)(
529 const struct ti_sci_handle *handle,
530 const struct ti_sci_msg_rm_udmap_flow_cfg *params);
531};
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549struct ti_sci_msg_fwl_region {
550 u16 fwl_id;
551 u16 region;
552 u32 n_permission_regs;
553 u32 control;
554 u32 permissions[3];
555 u64 start_address;
556 u64 end_address;
557} __packed;
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575struct ti_sci_msg_fwl_owner {
576 u16 fwl_id;
577 u16 region;
578 u8 owner_index;
579 u8 owner_privid;
580 u16 owner_permission_bits;
581} __packed;
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589struct ti_sci_fwl_ops {
590 int (*set_fwl_region)(const struct ti_sci_handle *handle, const struct ti_sci_msg_fwl_region *region);
591 int (*get_fwl_region)(const struct ti_sci_handle *handle, struct ti_sci_msg_fwl_region *region);
592 int (*change_fwl_owner)(const struct ti_sci_handle *handle, struct ti_sci_msg_fwl_owner *owner);
593};
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605struct ti_sci_ops {
606 struct ti_sci_board_ops board_ops;
607 struct ti_sci_dev_ops dev_ops;
608 struct ti_sci_clk_ops clk_ops;
609 struct ti_sci_core_ops core_ops;
610 struct ti_sci_proc_ops proc_ops;
611 struct ti_sci_rm_core_ops rm_core_ops;
612 struct ti_sci_rm_ringacc_ops rm_ring_ops;
613 struct ti_sci_rm_psil_ops rm_psil_ops;
614 struct ti_sci_rm_udmap_ops rm_udmap_ops;
615 struct ti_sci_fwl_ops fwl_ops;
616};
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623struct ti_sci_handle {
624 struct ti_sci_ops ops;
625 struct ti_sci_version_info version;
626};
627
628#define TI_SCI_RESOURCE_NULL 0xffff
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636struct ti_sci_resource_desc {
637 u16 start;
638 u16 num;
639 unsigned long *res_map;
640};
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648struct ti_sci_resource {
649 u16 sets;
650 struct ti_sci_resource_desc *desc;
651};
652
653#if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL)
654
655const struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct udevice *dev);
656const struct ti_sci_handle *ti_sci_get_handle(struct udevice *dev);
657const struct ti_sci_handle *ti_sci_get_by_phandle(struct udevice *dev,
658 const char *property);
659u16 ti_sci_get_free_resource(struct ti_sci_resource *res);
660void ti_sci_release_resource(struct ti_sci_resource *res, u16 id);
661struct ti_sci_resource *
662devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
663 struct udevice *dev, u32 dev_id, char *of_prop);
664
665#else
666
667static inline
668const struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct udevice *dev)
669{
670 return ERR_PTR(-EINVAL);
671}
672
673static inline const struct ti_sci_handle *ti_sci_get_handle(struct udevice *dev)
674{
675 return ERR_PTR(-EINVAL);
676}
677
678static inline
679const struct ti_sci_handle *ti_sci_get_by_phandle(struct udevice *dev,
680 const char *property)
681{
682 return ERR_PTR(-EINVAL);
683}
684
685static inline u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
686{
687 return TI_SCI_RESOURCE_NULL;
688}
689
690static inline void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
691{
692}
693
694static inline struct ti_sci_resource *
695devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
696 struct udevice *dev, u32 dev_id, char *of_prop)
697{
698 return ERR_PTR(-EINVAL);
699}
700#endif
701
702#endif
703