1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select ARM_ERRATA_855873 if !TFABOOT 5 select FSL_LAYERSCAPE 6 select FSL_LSCH2 7 select SYS_FSL_SRDS_1 8 select SYS_HAS_SERDES 9 select SYS_FSL_DDR_BE 10 select SYS_FSL_MMDC 11 select SYS_FSL_ERRATUM_A010315 12 select SYS_FSL_ERRATUM_A009798 13 select SYS_FSL_ERRATUM_A008997 14 select SYS_FSL_ERRATUM_A009007 15 select SYS_FSL_ERRATUM_A009008 16 select ARCH_EARLY_INIT_R 17 select BOARD_EARLY_INIT_F 18 select SYS_I2C_MXC 19 select SYS_I2C_MXC_I2C1 if !DM_I2C 20 select SYS_I2C_MXC_I2C2 if !DM_I2C 21 imply PANIC_HANG 22 23config ARCH_LS1028A 24 bool 25 select ARMV8_SET_SMPEN 26 select FSL_LAYERSCAPE 27 select FSL_LSCH3 28 select NXP_LSCH3_2 29 select SYS_FSL_HAS_CCI400 30 select SYS_FSL_SRDS_1 31 select SYS_HAS_SERDES 32 select SYS_FSL_DDR 33 select SYS_FSL_DDR_LE 34 select SYS_FSL_DDR_VER_50 35 select SYS_FSL_HAS_DDR3 36 select SYS_FSL_HAS_DDR4 37 select SYS_FSL_HAS_SEC 38 select SYS_FSL_SEC_COMPAT_5 39 select SYS_FSL_SEC_LE 40 select FSL_TZASC_1 41 select ARCH_EARLY_INIT_R 42 select BOARD_EARLY_INIT_F 43 select SYS_I2C_MXC 44 select SYS_FSL_ERRATUM_A008997 45 select SYS_FSL_ERRATUM_A009007 46 select SYS_FSL_ERRATUM_A008514 if !TFABOOT 47 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 48 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 49 select SYS_FSL_ERRATUM_A050382 50 select SYS_FSL_ERRATUM_A011334 51 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND 52 select RESV_RAM if GIC_V3_ITS 53 imply PANIC_HANG 54 55config ARCH_LS1043A 56 bool 57 select ARMV8_SET_SMPEN 58 select ARM_ERRATA_855873 if !TFABOOT 59 select FSL_LAYERSCAPE 60 select FSL_LSCH2 61 select HAS_FSL_XHCI_USB if USB_HOST 62 select SYS_FSL_SRDS_1 63 select SYS_HAS_SERDES 64 select SYS_FSL_DDR 65 select SYS_FSL_DDR_BE 66 select SYS_FSL_DDR_VER_50 67 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 68 select SYS_FSL_ERRATUM_A008997 69 select SYS_FSL_ERRATUM_A009007 70 select SYS_FSL_ERRATUM_A009008 71 select SYS_FSL_ERRATUM_A009660 if !TFABOOT 72 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 73 select SYS_FSL_ERRATUM_A009798 74 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 75 select SYS_FSL_ERRATUM_A010315 76 select SYS_FSL_ERRATUM_A010539 77 select SYS_FSL_HAS_DDR3 78 select SYS_FSL_HAS_DDR4 79 select ARCH_EARLY_INIT_R 80 select BOARD_EARLY_INIT_F 81 select SYS_I2C_MXC 82 select SYS_I2C_MXC_I2C1 if !DM_I2C 83 select SYS_I2C_MXC_I2C2 if !DM_I2C 84 select SYS_I2C_MXC_I2C3 if !DM_I2C 85 select SYS_I2C_MXC_I2C4 if !DM_I2C 86 imply CMD_PCI 87 88config ARCH_LS1046A 89 bool 90 select ARMV8_SET_SMPEN 91 select FSL_LAYERSCAPE 92 select FSL_LSCH2 93 select HAS_FSL_XHCI_USB if USB_HOST 94 select SYS_FSL_SRDS_1 95 select SYS_HAS_SERDES 96 select SYS_FSL_DDR 97 select SYS_FSL_DDR_BE 98 select SYS_FSL_DDR_VER_50 99 select SYS_FSL_ERRATUM_A008336 if !TFABOOT 100 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 101 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 102 select SYS_FSL_ERRATUM_A008997 103 select SYS_FSL_ERRATUM_A009007 104 select SYS_FSL_ERRATUM_A009008 105 select SYS_FSL_ERRATUM_A009798 106 select SYS_FSL_ERRATUM_A009801 107 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 108 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 109 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 110 select SYS_FSL_ERRATUM_A010539 111 select SYS_FSL_HAS_DDR4 112 select SYS_FSL_SRDS_2 113 select ARCH_EARLY_INIT_R 114 select BOARD_EARLY_INIT_F 115 select SYS_I2C_MXC 116 select SYS_I2C_MXC_I2C1 if !DM_I2C 117 select SYS_I2C_MXC_I2C2 if !DM_I2C 118 select SYS_I2C_MXC_I2C3 if !DM_I2C 119 select SYS_I2C_MXC_I2C4 if !DM_I2C 120 imply SCSI 121 imply SCSI_AHCI 122 123config ARCH_LS1088A 124 bool 125 select ARMV8_SET_SMPEN 126 select ARM_ERRATA_855873 if !TFABOOT 127 select FSL_LAYERSCAPE 128 select FSL_LSCH3 129 select SYS_FSL_SRDS_1 130 select SYS_HAS_SERDES 131 select SYS_FSL_DDR 132 select SYS_FSL_DDR_LE 133 select SYS_FSL_DDR_VER_50 134 select SYS_FSL_EC1 135 select SYS_FSL_EC2 136 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 137 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 138 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 139 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 140 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 141 select SYS_FSL_ERRATUM_A009007 142 select SYS_FSL_HAS_CCI400 143 select SYS_FSL_HAS_DDR4 144 select SYS_FSL_HAS_RGMII 145 select SYS_FSL_HAS_SEC 146 select SYS_FSL_SEC_COMPAT_5 147 select SYS_FSL_SEC_LE 148 select SYS_FSL_SRDS_1 149 select SYS_FSL_SRDS_2 150 select FSL_TZASC_1 151 select FSL_TZASC_400 152 select FSL_TZPC_BP147 153 select ARCH_EARLY_INIT_R 154 select BOARD_EARLY_INIT_F 155 select SYS_I2C_MXC 156 select SYS_I2C_MXC_I2C1 if !TFABOOT 157 select SYS_I2C_MXC_I2C2 if !TFABOOT 158 select SYS_I2C_MXC_I2C3 if !TFABOOT 159 select SYS_I2C_MXC_I2C4 if !TFABOOT 160 select RESV_RAM if GIC_V3_ITS 161 imply SCSI 162 imply PANIC_HANG 163 164config ARCH_LS2080A 165 bool 166 select ARMV8_SET_SMPEN 167 select ARM_ERRATA_826974 168 select ARM_ERRATA_828024 169 select ARM_ERRATA_829520 170 select ARM_ERRATA_833471 171 select FSL_LAYERSCAPE 172 select FSL_LSCH3 173 select SYS_FSL_SRDS_1 174 select SYS_HAS_SERDES 175 select SYS_FSL_DDR 176 select SYS_FSL_DDR_LE 177 select SYS_FSL_DDR_VER_50 178 select SYS_FSL_HAS_CCN504 179 select SYS_FSL_HAS_DP_DDR 180 select SYS_FSL_HAS_SEC 181 select SYS_FSL_HAS_DDR4 182 select SYS_FSL_SEC_COMPAT_5 183 select SYS_FSL_SEC_LE 184 select SYS_FSL_SRDS_2 185 select FSL_TZASC_1 186 select FSL_TZASC_2 187 select FSL_TZASC_400 188 select FSL_TZPC_BP147 189 select SYS_FSL_ERRATUM_A008336 if !TFABOOT 190 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 191 select SYS_FSL_ERRATUM_A008514 if !TFABOOT 192 select SYS_FSL_ERRATUM_A008585 193 select SYS_FSL_ERRATUM_A008997 194 select SYS_FSL_ERRATUM_A009007 195 select SYS_FSL_ERRATUM_A009008 196 select SYS_FSL_ERRATUM_A009635 197 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 198 select SYS_FSL_ERRATUM_A009798 199 select SYS_FSL_ERRATUM_A009801 200 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 201 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 202 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 203 select SYS_FSL_ERRATUM_A009203 204 select ARCH_EARLY_INIT_R 205 select BOARD_EARLY_INIT_F 206 select SYS_I2C_MXC 207 select SYS_I2C_MXC_I2C1 if !TFABOOT 208 select SYS_I2C_MXC_I2C2 if !TFABOOT 209 select SYS_I2C_MXC_I2C3 if !TFABOOT 210 select SYS_I2C_MXC_I2C4 if !TFABOOT 211 select RESV_RAM if GIC_V3_ITS 212 imply DISTRO_DEFAULTS 213 imply PANIC_HANG 214 215config ARCH_LX2162A 216 bool 217 select ARMV8_SET_SMPEN 218 select FSL_LSCH3 219 select NXP_LSCH3_2 220 select SYS_HAS_SERDES 221 select SYS_FSL_SRDS_1 222 select SYS_FSL_SRDS_2 223 select SYS_FSL_DDR 224 select SYS_FSL_DDR_LE 225 select SYS_FSL_DDR_VER_50 226 select SYS_FSL_EC1 227 select SYS_FSL_EC2 228 select SYS_FSL_ERRATUM_A050204 229 select SYS_FSL_ERRATUM_A011334 230 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND 231 select SYS_FSL_HAS_RGMII 232 select SYS_FSL_HAS_SEC 233 select SYS_FSL_HAS_CCN508 234 select SYS_FSL_HAS_DDR4 235 select SYS_FSL_SEC_COMPAT_5 236 select SYS_FSL_SEC_LE 237 select ARCH_EARLY_INIT_R 238 select BOARD_EARLY_INIT_F 239 select SYS_I2C_MXC 240 select RESV_RAM if GIC_V3_ITS 241 imply DISTRO_DEFAULTS 242 imply PANIC_HANG 243 imply SCSI 244 imply SCSI_AHCI 245 246config ARCH_LX2160A 247 bool 248 select ARMV8_SET_SMPEN 249 select FSL_LSCH3 250 select HAS_FSL_XHCI_USB if USB_HOST 251 select NXP_LSCH3_2 252 select SYS_HAS_SERDES 253 select SYS_FSL_SRDS_1 254 select SYS_FSL_SRDS_2 255 select SYS_NXP_SRDS_3 256 select SYS_FSL_DDR 257 select SYS_FSL_DDR_LE 258 select SYS_FSL_DDR_VER_50 259 select SYS_FSL_EC1 260 select SYS_FSL_EC2 261 select SYS_FSL_ERRATUM_A050204 262 select SYS_FSL_ERRATUM_A011334 263 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND 264 select SYS_FSL_HAS_RGMII 265 select SYS_FSL_HAS_SEC 266 select SYS_FSL_HAS_CCN508 267 select SYS_FSL_HAS_DDR4 268 select SYS_FSL_SEC_COMPAT_5 269 select SYS_FSL_SEC_LE 270 select ARCH_EARLY_INIT_R 271 select BOARD_EARLY_INIT_F 272 select SYS_I2C_MXC 273 select RESV_RAM if GIC_V3_ITS 274 imply DISTRO_DEFAULTS 275 imply PANIC_HANG 276 imply SCSI 277 imply SCSI_AHCI 278 279config FSL_LSCH2 280 bool 281 select SYS_FSL_HAS_CCI400 282 select SYS_FSL_HAS_SEC 283 select SYS_FSL_SEC_COMPAT_5 284 select SYS_FSL_SEC_BE 285 286config FSL_LSCH3 287 select ARCH_MISC_INIT 288 bool 289 290config NXP_LSCH3_2 291 bool 292 293menu "Layerscape architecture" 294 depends on FSL_LSCH2 || FSL_LSCH3 295 296config FSL_LAYERSCAPE 297 bool 298 299config HAS_FEATURE_GIC64K_ALIGN 300 bool 301 default y if ARCH_LS1043A 302 303config HAS_FEATURE_ENHANCED_MSI 304 bool 305 default y if ARCH_LS1043A 306 307menu "Layerscape PPA" 308config FSL_LS_PPA 309 bool "FSL Layerscape PPA firmware support" 310 depends on !ARMV8_PSCI 311 select ARMV8_SEC_FIRMWARE_SUPPORT 312 select SEC_FIRMWARE_ARMV8_PSCI 313 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 314 help 315 The FSL Primary Protected Application (PPA) is a software component 316 which is loaded during boot stage, and then remains resident in RAM 317 and runs in the TrustZone after boot. 318 Say y to enable it. 319 320config SPL_FSL_LS_PPA 321 bool "FSL Layerscape PPA firmware support for SPL build" 322 depends on !ARMV8_PSCI 323 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 324 select SEC_FIRMWARE_ARMV8_PSCI 325 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 326 help 327 The FSL Primary Protected Application (PPA) is a software component 328 which is loaded during boot stage, and then remains resident in RAM 329 and runs in the TrustZone after boot. This is to load PPA during SPL 330 stage instead of the RAM version of U-Boot. Once PPA is initialized, 331 the rest of U-Boot (including RAM version) runs at EL2. 332choice 333 prompt "FSL Layerscape PPA firmware loading-media select" 334 depends on FSL_LS_PPA 335 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 336 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 337 default SYS_LS_PPA_FW_IN_XIP 338 339config SYS_LS_PPA_FW_IN_XIP 340 bool "XIP" 341 help 342 Say Y here if the PPA firmware locate at XIP flash, such 343 as NOR or QSPI flash. 344 345config SYS_LS_PPA_FW_IN_MMC 346 bool "eMMC or SD Card" 347 help 348 Say Y here if the PPA firmware locate at eMMC/SD card. 349 350config SYS_LS_PPA_FW_IN_NAND 351 bool "NAND" 352 help 353 Say Y here if the PPA firmware locate at NAND flash. 354 355endchoice 356 357config LS_PPA_ESBC_HDR_SIZE 358 hex "Length of PPA ESBC header" 359 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 360 default 0x2000 361 help 362 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 363 NAND to memory to validate PPA image. 364 365endmenu 366 367config SYS_FSL_ERRATUM_A008997 368 bool "Workaround for USB PHY erratum A008997" 369 370config SYS_FSL_ERRATUM_A009007 371 bool 372 help 373 Workaround for USB PHY erratum A009007 374 375config SYS_FSL_ERRATUM_A009008 376 bool "Workaround for USB PHY erratum A009008" 377 378config SYS_FSL_ERRATUM_A009798 379 bool "Workaround for USB PHY erratum A009798" 380 381config SYS_FSL_ERRATUM_A050204 382 bool "Workaround for USB PHY erratum A050204" 383 help 384 USB3.0 Receiver needs to enable fixed equalization 385 for each of PHY instances in an SOC. This is similar 386 to erratum A-009007, but this one is for LX2160A and LX2162A, 387 and the register value is different. 388 389config SYS_FSL_ERRATUM_A010315 390 bool "Workaround for PCIe erratum A010315" 391 392config SYS_FSL_ERRATUM_A010539 393 bool "Workaround for PIN MUX erratum A010539" 394 395config MAX_CPUS 396 int "Maximum number of CPUs permitted for Layerscape" 397 default 2 if ARCH_LS1028A 398 default 4 if ARCH_LS1043A 399 default 4 if ARCH_LS1046A 400 default 16 if ARCH_LS2080A 401 default 8 if ARCH_LS1088A 402 default 16 if ARCH_LX2160A 403 default 16 if ARCH_LX2162A 404 default 1 405 help 406 Set this number to the maximum number of possible CPUs in the SoC. 407 SoCs may have multiple clusters with each cluster may have multiple 408 ports. If some ports are reserved but higher ports are used for 409 cores, count the reserved ports. This will allocate enough memory 410 in spin table to properly handle all cores. 411 412config EMC2305 413 bool "Fan controller" 414 help 415 Enable the EMC2305 fan controller for configuration of fan 416 speed. 417 418config NXP_ESBC 419 bool "NXP_ESBC" 420 help 421 Enable Freescale Secure Boot feature 422 423config QSPI_AHB_INIT 424 bool "Init the QSPI AHB bus" 425 help 426 The default setting for QSPI AHB bus just support 3bytes addressing. 427 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 428 bus for those flashes to support the full QSPI flash size. 429 430config FSPI_AHB_EN_4BYTE 431 bool "Enable 4-byte Fast Read command for AHB mode" 432 default n 433 help 434 The default setting for FlexSPI AHB bus just supports 3-byte addressing. 435 But some FlexSPI flash sizes are up to 64MBytes. 436 This flag enables fast read command for AHB mode and modifies required 437 LUT to support full FlexSPI flash. 438 439config SYS_CCI400_OFFSET 440 hex "Offset for CCI400 base" 441 depends on SYS_FSL_HAS_CCI400 442 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A 443 default 0x180000 if FSL_LSCH2 444 help 445 Offset for CCI400 base 446 CCI400 base addr = CCSRBAR + CCI400_OFFSET 447 448config SYS_FSL_IFC_BANK_COUNT 449 int "Maximum banks of Integrated flash controller" 450 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A 451 default 4 if ARCH_LS1043A 452 default 4 if ARCH_LS1046A 453 default 8 if ARCH_LS2080A || ARCH_LS1088A 454 455config SYS_FSL_HAS_CCI400 456 bool 457 458config SYS_FSL_HAS_CCN504 459 bool 460 461config SYS_FSL_HAS_CCN508 462 bool 463 464config SYS_FSL_HAS_DP_DDR 465 bool 466 467config SYS_FSL_SRDS_1 468 bool 469 470config SYS_FSL_SRDS_2 471 bool 472 473config SYS_NXP_SRDS_3 474 bool 475 476config SYS_HAS_SERDES 477 bool 478 479config FSL_TZASC_1 480 bool 481 482config FSL_TZASC_2 483 bool 484 485config FSL_TZASC_400 486 bool 487 488config FSL_TZPC_BP147 489 bool 490endmenu 491 492menu "Layerscape clock tree configuration" 493 depends on FSL_LSCH2 || FSL_LSCH3 494 495config SYS_FSL_CLK 496 bool "Enable clock tree initialization" 497 default y 498 499config CLUSTER_CLK_FREQ 500 int "Reference clock of core cluster" 501 depends on ARCH_LS1012A 502 default 100000000 503 help 504 This number is the reference clock frequency of core PLL. 505 For most platforms, the core PLL and Platform PLL have the same 506 reference clock, but for some platforms, LS1012A for instance, 507 they are provided sepatately. 508 509config SYS_FSL_PCLK_DIV 510 int "Platform clock divider" 511 default 1 if ARCH_LS1028A 512 default 1 if ARCH_LS1043A 513 default 1 if ARCH_LS1046A 514 default 1 if ARCH_LS1088A 515 default 2 516 help 517 This is the divider that is used to derive Platform clock from 518 Platform PLL, in another word: 519 Platform_clk = Platform_PLL_freq / this_divider 520 521config SYS_FSL_DSPI_CLK_DIV 522 int "DSPI clock divider" 523 default 1 if ARCH_LS1043A 524 default 2 525 help 526 This is the divider that is used to derive DSPI clock from Platform 527 clock, in another word DSPI_clk = Platform_clk / this_divider. 528 529config SYS_FSL_DUART_CLK_DIV 530 int "DUART clock divider" 531 default 1 if ARCH_LS1043A 532 default 4 if ARCH_LX2160A 533 default 4 if ARCH_LX2162A 534 default 2 535 help 536 This is the divider that is used to derive DUART clock from Platform 537 clock, in another word DUART_clk = Platform_clk / this_divider. 538 539config SYS_FSL_I2C_CLK_DIV 540 int "I2C clock divider" 541 default 1 if ARCH_LS1043A 542 default 4 if ARCH_LS1012A 543 default 4 if ARCH_LS1028A 544 default 8 if ARCH_LX2160A 545 default 8 if ARCH_LX2162A 546 default 8 if ARCH_LS1088A 547 default 2 548 help 549 This is the divider that is used to derive I2C clock from Platform 550 clock, in another word I2C_clk = Platform_clk / this_divider. 551 552config SYS_FSL_IFC_CLK_DIV 553 int "IFC clock divider" 554 default 1 if ARCH_LS1043A 555 default 4 if ARCH_LS1012A 556 default 4 if ARCH_LS1028A 557 default 8 if ARCH_LX2160A 558 default 8 if ARCH_LX2162A 559 default 8 if ARCH_LS1088A 560 default 2 561 help 562 This is the divider that is used to derive IFC clock from Platform 563 clock, in another word IFC_clk = Platform_clk / this_divider. 564 565config SYS_FSL_LPUART_CLK_DIV 566 int "LPUART clock divider" 567 default 1 if ARCH_LS1043A 568 default 2 569 help 570 This is the divider that is used to derive LPUART clock from Platform 571 clock, in another word LPUART_clk = Platform_clk / this_divider. 572 573config SYS_FSL_SDHC_CLK_DIV 574 int "SDHC clock divider" 575 default 1 if ARCH_LS1043A 576 default 1 if ARCH_LS1012A 577 default 2 578 help 579 This is the divider that is used to derive SDHC clock from Platform 580 clock, in another word SDHC_clk = Platform_clk / this_divider. 581 582config SYS_FSL_QMAN_CLK_DIV 583 int "QMAN clock divider" 584 default 1 if ARCH_LS1043A 585 default 2 586 help 587 This is the divider that is used to derive QMAN clock from Platform 588 clock, in another word QMAN_clk = Platform_clk / this_divider. 589endmenu 590 591config RESV_RAM 592 bool 593 help 594 Reserve memory from the top, tracked by gd->arch.resv_ram. This 595 reserved RAM can be used by special driver that resides in memory 596 after U-Boot exits. It's up to implementation to allocate and allow 597 access to this reserved memory. For example, the reserved RAM can 598 be at the high end of physical memory. The reserve RAM may be 599 excluded from memory bank(s) passed to OS, or marked as reserved. 600 601config SYS_FSL_EC1 602 bool 603 help 604 Ethernet controller 1, this is connected to 605 MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs 606 Provides DPAA2 capabilities 607 608config SYS_FSL_EC2 609 bool 610 help 611 Ethernet controller 2, this is connected to 612 MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs 613 Provides DPAA2 capabilities 614 615config SYS_FSL_ERRATUM_A008336 616 bool 617 618config SYS_FSL_ERRATUM_A008514 619 bool 620 621config SYS_FSL_ERRATUM_A008585 622 bool 623 624config SYS_FSL_ERRATUM_A008850 625 bool 626 627config SYS_FSL_ERRATUM_A009203 628 bool 629 630config SYS_FSL_ERRATUM_A009635 631 bool 632 633config SYS_FSL_ERRATUM_A009660 634 bool 635 636config SYS_FSL_ERRATUM_A050382 637 bool 638 639config SYS_FSL_HAS_RGMII 640 bool 641 depends on SYS_FSL_EC1 || SYS_FSL_EC2 642 643config SPL_LDSCRIPT 644 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 645 646config HAS_FSL_XHCI_USB 647 bool 648 help 649 For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use 650 pins, select it when the pins are assigned to USB. 651 652config SYS_FSL_BOOTROM_BASE 653 hex 654 depends on FSL_LSCH2 655 default 0 656 657config SYS_FSL_BOOTROM_SIZE 658 hex 659 depends on FSL_LSCH2 660 default 0x1000000 661