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9#include <common.h>
10#include <clock_legacy.h>
11#include <cpu_func.h>
12#include <asm/global_data.h>
13#include <linux/compiler.h>
14#include <fsl_ifc.h>
15#include <asm/processor.h>
16#include <asm/io.h>
17#include <asm/arch-fsl-layerscape/immap_lsch3.h>
18#include <asm/arch/clock.h>
19#include <asm/arch/soc.h>
20#include "cpu.h"
21
22DECLARE_GLOBAL_DATA_PTR;
23
24#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
25#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
26#endif
27
28
29void get_sys_info(struct sys_info *sys_info)
30{
31 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
32 struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
33 (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
34 (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
35 };
36 struct ccsr_clk_ctrl __iomem *clk_ctrl =
37 (void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR);
38 unsigned int cpu;
39 const u8 core_cplx_pll[16] = {
40 [0] = 0,
41 [1] = 0,
42 [2] = 0,
43 [4] = 1,
44 [5] = 1,
45 [6] = 1,
46 [8] = 2,
47 [9] = 2,
48 [10] = 2,
49 [12] = 3,
50 [13] = 3,
51 [14] = 3,
52 };
53
54 const u8 core_cplx_pll_div[16] = {
55 [0] = 1,
56 [1] = 2,
57 [2] = 4,
58 [4] = 1,
59 [5] = 2,
60 [6] = 4,
61 [8] = 1,
62 [9] = 2,
63 [10] = 4,
64 [12] = 1,
65 [13] = 2,
66 [14] = 4,
67 };
68
69 uint i, cluster;
70#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
71 uint rcw_tmp;
72#endif
73 uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
74 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
75 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
76 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
77 u32 c_pll_sel, cplx_pll;
78 void *offset;
79
80 sys_info->freq_systembus = sysclk;
81#ifdef CONFIG_DDR_CLK_FREQ
82 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
83#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
84 sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
85#endif
86#else
87 sys_info->freq_ddrbus = sysclk;
88#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
89 sys_info->freq_ddrbus2 = sysclk;
90#endif
91#endif
92
93
94 sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
95 FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
96 FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
97 sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
98 FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
99 FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
100#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
101 if (soc_has_dp_ddr()) {
102 sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
103 FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
104 FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
105 } else {
106 sys_info->freq_ddrbus2 = 0;
107 }
108#endif
109
110 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
111
112
113
114
115 offset = (void *)((size_t)clk_grp[i/3] +
116 offsetof(struct ccsr_clk_cluster_group,
117 pllngsr[i%3].gsr));
118 ratio[i] = (in_le32(offset) >> 1) & 0x3f;
119 freq_c_pll[i] = sysclk * ratio[i];
120 }
121
122 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
123 cluster = fsl_qoriq_core_to_cluster(cpu);
124 c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27)
125 & 0xf;
126 cplx_pll = core_cplx_pll[c_pll_sel];
127 cplx_pll += cc_group[cluster] - 1;
128 sys_info->freq_processor[cpu] =
129 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
130 }
131
132#if defined(CONFIG_FSL_IFC)
133 sys_info->freq_localbus = sys_info->freq_systembus /
134 CONFIG_SYS_FSL_IFC_CLK_DIV;
135#endif
136
137#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
138#define HWA_CGA_M2_CLK_SEL 0x00380000
139#define HWA_CGA_M2_CLK_SHIFT 19
140 rcw_tmp = in_le32(&gur->rcwsr[5]);
141 switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
142 case 1:
143 sys_info->freq_cga_m2 = freq_c_pll[1];
144 break;
145 case 2:
146 sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
147 break;
148 case 3:
149 sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
150 break;
151 case 4:
152 sys_info->freq_cga_m2 = freq_c_pll[1] / 4;
153 break;
154 case 6:
155 sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
156 break;
157 case 7:
158 sys_info->freq_cga_m2 = freq_c_pll[0] / 3;
159 break;
160 default:
161 printf("Error: Unknown peripheral clock select!\n");
162 break;
163 }
164#endif
165}
166
167int get_clocks(void)
168{
169 struct sys_info sys_info;
170#ifdef CONFIG_FSL_ESDHC
171 u32 clock = 0;
172#endif
173 get_sys_info(&sys_info);
174 gd->cpu_clk = sys_info.freq_processor[0];
175 gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
176 gd->mem_clk = sys_info.freq_ddrbus;
177#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
178 gd->arch.mem2_clk = sys_info.freq_ddrbus2;
179#endif
180
181#ifdef CONFIG_FSL_ESDHC
182#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
183 clock = sys_info.freq_cga_m2;
184#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2162A)
185 clock = sys_info.freq_systembus;
186#endif
187 gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
188 gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
189#endif
190
191 if (gd->cpu_clk != 0)
192 return 0;
193 else
194 return 1;
195}
196
197
198
199
200
201ulong get_bus_freq(ulong dummy)
202{
203 if (!gd->bus_clk)
204 get_clocks();
205
206 return gd->bus_clk;
207}
208
209
210
211
212
213ulong get_ddr_freq(ulong ctrl_num)
214{
215 if (!gd->mem_clk)
216 get_clocks();
217
218
219
220
221
222#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
223 if (ctrl_num >= 2)
224 return gd->arch.mem2_clk;
225#endif
226
227 return gd->mem_clk;
228}
229
230int get_i2c_freq(ulong dummy)
231{
232 return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
233}
234
235int get_dspi_freq(ulong dummy)
236{
237 return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
238}
239
240int get_serial_clock(void)
241{
242 return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
243}
244
245unsigned int mxc_get_clock(enum mxc_clock clk)
246{
247 switch (clk) {
248 case MXC_I2C_CLK:
249 return get_i2c_freq(0);
250 case MXC_DSPI_CLK:
251 return get_dspi_freq(0);
252 default:
253 printf("Unsupported clock\n");
254 }
255 return 0;
256}
257
