LXR uboot/arch/arm/mach-davinci/cpu.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2004 Texas Instruments.
   4 * Copyright (C) 2009 David Brownell
   5 */
   6
   7#include <common.h>
   8#include <init.h>
   9#include <asm/arch/hardware.h>
  10#include <asm/global_data.h>
  11#include <asm/io.h>
  12
  13DECLARE_GLOBAL_DATA_PTR;
  14
  15/* offsets from PLL controller base */
  16#define PLLC_PLLCTL     0x100
  17#define PLLC_PLLM       0x110
  18#define PLLC_PREDIV     0x114
  19#define PLLC_PLLDIV1    0x118
  20#define PLLC_PLLDIV2    0x11c
  21#define PLLC_PLLDIV3    0x120
  22#define PLLC_POSTDIV    0x128
  23#define PLLC_BPDIV      0x12c
  24#define PLLC_PLLDIV4    0x160
  25#define PLLC_PLLDIV5    0x164
  26#define PLLC_PLLDIV6    0x168
  27#define PLLC_PLLDIV7    0x16c
  28#define PLLC_PLLDIV8    0x170
  29#define PLLC_PLLDIV9    0x174
  30
  31unsigned int sysdiv[9] = {
  32        PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
  33        PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
  34};
  35
  36int clk_get(enum davinci_clk_ids id)
  37{
  38        int pre_div;
  39        int pllm;
  40        int post_div;
  41        int pll_out;
  42        unsigned int pll_base;
  43
  44        pll_out = CONFIG_SYS_OSCIN_FREQ;
  45
  46        if (id == DAVINCI_AUXCLK_CLKID)
  47                goto out;
  48
  49        if ((id >> 16) == 1)
  50                pll_base = (unsigned int)davinci_pllc1_regs;
  51        else
  52                pll_base = (unsigned int)davinci_pllc0_regs;
  53
  54        id &= 0xFFFF;
  55
  56        /*
  57         * Lets keep this simple. Combining operations can result in
  58         * unexpected approximations
  59         */
  60        pre_div = (readl(pll_base + PLLC_PREDIV) &
  61                DAVINCI_PLLC_DIV_MASK) + 1;
  62        pllm = readl(pll_base + PLLC_PLLM) + 1;
  63
  64        pll_out /= pre_div;
  65        pll_out *= pllm;
  66
  67        if (id == DAVINCI_PLLM_CLKID)
  68                goto out;
  69
  70        post_div = (readl(pll_base + PLLC_POSTDIV) &
  71                DAVINCI_PLLC_DIV_MASK) + 1;
  72
  73        pll_out /= post_div;
  74
  75        if (id == DAVINCI_PLLC_CLKID)
  76                goto out;
  77
  78        pll_out /= (readl(pll_base + sysdiv[id - 1]) &
  79                DAVINCI_PLLC_DIV_MASK) + 1;
  80
  81out:
  82        return pll_out;
  83}
  84
  85int set_cpu_clk_info(void)
  86{
  87        gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
  88        /* DDR PHY uses an x2 input clock */
  89        gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
  90                                (clk_get(DAVINCI_DDR_CLKID) / 1000000);
  91        gd->bd->bi_dsp_freq = 0;
  92        return 0;
  93}
  94