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7#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
8#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
9
10#ifndef __ASSEMBLY__
11
12
13struct exynos_spi {
14 unsigned int ch_cfg;
15 unsigned char reserved0[4];
16 unsigned int mode_cfg;
17 unsigned int cs_reg;
18 unsigned char reserved1[4];
19 unsigned int spi_sts;
20 unsigned int tx_data;
21 unsigned int rx_data;
22 unsigned int pkt_cnt;
23 unsigned char reserved2[4];
24 unsigned int swap_cfg;
25 unsigned int fb_clk;
26 unsigned char padding[0xffd0];
27};
28
29#define EXYNOS_SPI_MAX_FREQ 50000000
30
31#define SPI_TIMEOUT_MS 10
32#define SF_READ_DATA_CMD 0x3
33
34
35#define SPI_CH_HS_EN (1 << 6)
36#define SPI_CH_RST (1 << 5)
37#define SPI_SLAVE_MODE (1 << 4)
38#define SPI_CH_CPOL_L (1 << 3)
39#define SPI_CH_CPHA_B (1 << 2)
40#define SPI_RX_CH_ON (1 << 1)
41#define SPI_TX_CH_ON (1 << 0)
42
43
44#define SPI_MODE_CH_WIDTH_WORD (0x2 << 29)
45#define SPI_MODE_BUS_WIDTH_WORD (0x2 << 17)
46
47
48#define SPI_SLAVE_SIG_INACT (1 << 0)
49
50
51#define SPI_ST_TX_DONE (1 << 25)
52#define SPI_FIFO_LVL_MASK 0x1ff
53#define SPI_TX_LVL_OFFSET 6
54#define SPI_RX_LVL_OFFSET 15
55
56
57#define SPI_CLK_BYPASS (0 << 0)
58#define SPI_FB_DELAY_90 (1 << 0)
59#define SPI_FB_DELAY_180 (2 << 0)
60#define SPI_FB_DELAY_270 (3 << 0)
61
62
63#define SPI_PACKET_CNT_EN (1 << 16)
64
65
66#define SPI_TX_SWAP_EN (1 << 0)
67#define SPI_TX_BYTE_SWAP (1 << 2)
68#define SPI_TX_HWORD_SWAP (1 << 3)
69#define SPI_TX_BYTE_SWAP (1 << 2)
70#define SPI_RX_SWAP_EN (1 << 4)
71#define SPI_RX_BYTE_SWAP (1 << 6)
72#define SPI_RX_HWORD_SWAP (1 << 7)
73
74#endif
75#endif
76