1
2
3
4
5#include <common.h>
6#include <clk.h>
7#include <dm.h>
8#include <init.h>
9#include <asm/armv8/mmu.h>
10#include <asm/io.h>
11#include <asm/arch-rockchip/grf_px30.h>
12#include <asm/arch-rockchip/hardware.h>
13#include <asm/arch-rockchip/uart.h>
14#include <asm/arch-rockchip/clock.h>
15#include <asm/arch-rockchip/cru_px30.h>
16#include <dt-bindings/clock/px30-cru.h>
17
18static struct mm_region px30_mem_map[] = {
19 {
20 .virt = 0x0UL,
21 .phys = 0x0UL,
22 .size = 0xff000000UL,
23 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
24 PTE_BLOCK_INNER_SHARE
25 }, {
26 .virt = 0xff000000UL,
27 .phys = 0xff000000UL,
28 .size = 0x01000000UL,
29 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
30 PTE_BLOCK_NON_SHARE |
31 PTE_BLOCK_PXN | PTE_BLOCK_UXN
32 }, {
33
34 0,
35 }
36};
37
38struct mm_region *mem_map = px30_mem_map;
39
40#define PMU_PWRDN_CON 0xff000018
41#define PMUGRF_BASE 0xff010000
42#define GRF_BASE 0xff140000
43#define CRU_BASE 0xff2b0000
44#define VIDEO_PHY_BASE 0xff2e0000
45#define SERVICE_CORE_ADDR 0xff508000
46#define DDR_FW_BASE 0xff534000
47
48#define FW_DDR_CON 0x40
49
50#define QOS_PRIORITY 0x08
51
52#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3))
53
54
55enum {
56 GPIO1A3_SHIFT = 12,
57 GPIO1A3_MASK = 0xf << GPIO1A3_SHIFT,
58 GPIO1A3_GPIO = 0,
59 GPIO1A3_FLASH_D3,
60 GPIO1A3_EMMC_D3,
61 GPIO1A3_SFC_SIO3,
62
63 GPIO1A2_SHIFT = 8,
64 GPIO1A2_MASK = 0xf << GPIO1A2_SHIFT,
65 GPIO1A2_GPIO = 0,
66 GPIO1A2_FLASH_D2,
67 GPIO1A2_EMMC_D2,
68 GPIO1A2_SFC_SIO2,
69
70 GPIO1A1_SHIFT = 4,
71 GPIO1A1_MASK = 0xf << GPIO1A1_SHIFT,
72 GPIO1A1_GPIO = 0,
73 GPIO1A1_FLASH_D1,
74 GPIO1A1_EMMC_D1,
75 GPIO1A1_SFC_SIO1,
76
77 GPIO1A0_SHIFT = 0,
78 GPIO1A0_MASK = 0xf << GPIO1A0_SHIFT,
79 GPIO1A0_GPIO = 0,
80 GPIO1A0_FLASH_D0,
81 GPIO1A0_EMMC_D0,
82 GPIO1A0_SFC_SIO0,
83};
84
85
86enum {
87 GPIO1A4_SHIFT = 0,
88 GPIO1A4_MASK = 0xf << GPIO1A4_SHIFT,
89 GPIO1A4_GPIO = 0,
90 GPIO1A4_FLASH_D4,
91 GPIO1A4_EMMC_D4,
92 GPIO1A4_SFC_CSN0,
93};
94
95
96enum {
97 GPIO1B1_SHIFT = 4,
98 GPIO1B1_MASK = 0xf << GPIO1B1_SHIFT,
99 GPIO1B1_GPIO = 0,
100 GPIO1B1_FLASH_RDY,
101 GPIO1B1_EMMC_CLKOUT,
102 GPIO1B1_SFC_CLK,
103};
104
105
106enum {
107 GPIO1B7_SHIFT = 12,
108 GPIO1B7_MASK = 0xf << GPIO1B7_SHIFT,
109 GPIO1B7_GPIO = 0,
110 GPIO1B7_FLASH_RDN,
111 GPIO1B7_UART3_RXM1,
112 GPIO1B7_SPI0_CLK,
113
114 GPIO1B6_SHIFT = 8,
115 GPIO1B6_MASK = 0xf << GPIO1B6_SHIFT,
116 GPIO1B6_GPIO = 0,
117 GPIO1B6_FLASH_CS1,
118 GPIO1B6_UART3_TXM1,
119 GPIO1B6_SPI0_CSN,
120};
121
122
123enum {
124 GPIO1C1_SHIFT = 4,
125 GPIO1C1_MASK = 0xf << GPIO1C1_SHIFT,
126 GPIO1C1_GPIO = 0,
127 GPIO1C1_UART1_TX,
128
129 GPIO1C0_SHIFT = 0,
130 GPIO1C0_MASK = 0xf << GPIO1C0_SHIFT,
131 GPIO1C0_GPIO = 0,
132 GPIO1C0_UART1_RX,
133};
134
135
136enum {
137 GPIO1D3_SHIFT = 12,
138 GPIO1D3_MASK = 0xf << GPIO1D3_SHIFT,
139 GPIO1D3_GPIO = 0,
140 GPIO1D3_SDMMC_D1,
141 GPIO1D3_UART2_RXM0,
142
143 GPIO1D2_SHIFT = 8,
144 GPIO1D2_MASK = 0xf << GPIO1D2_SHIFT,
145 GPIO1D2_GPIO = 0,
146 GPIO1D2_SDMMC_D0,
147 GPIO1D2_UART2_TXM0,
148};
149
150
151enum {
152 GPIO1D7_SHIFT = 12,
153 GPIO1D7_MASK = 0xf << GPIO1D7_SHIFT,
154 GPIO1D7_GPIO = 0,
155 GPIO1D7_SDMMC_CMD,
156
157 GPIO1D6_SHIFT = 8,
158 GPIO1D6_MASK = 0xf << GPIO1D6_SHIFT,
159 GPIO1D6_GPIO = 0,
160 GPIO1D6_SDMMC_CLK,
161
162 GPIO1D5_SHIFT = 4,
163 GPIO1D5_MASK = 0xf << GPIO1D5_SHIFT,
164 GPIO1D5_GPIO = 0,
165 GPIO1D5_SDMMC_D3,
166
167 GPIO1D4_SHIFT = 0,
168 GPIO1D4_MASK = 0xf << GPIO1D4_SHIFT,
169 GPIO1D4_GPIO = 0,
170 GPIO1D4_SDMMC_D2,
171};
172
173
174enum {
175 GPIO2B6_SHIFT = 8,
176 GPIO2B6_MASK = 0xf << GPIO2B6_SHIFT,
177 GPIO2B6_GPIO = 0,
178 GPIO2B6_CIF_D1M0,
179 GPIO2B6_UART2_RXM1,
180
181 GPIO2B4_SHIFT = 0,
182 GPIO2B4_MASK = 0xf << GPIO2B4_SHIFT,
183 GPIO2B4_GPIO = 0,
184 GPIO2B4_CIF_D0M0,
185 GPIO2B4_UART2_TXM1,
186};
187
188
189enum {
190 GPIO3A2_SHIFT = 8,
191 GPIO3A2_MASK = 0xf << GPIO3A2_SHIFT,
192 GPIO3A2_GPIO = 0,
193 GPIO3A2_UART5_TX = 4,
194
195 GPIO3A1_SHIFT = 4,
196 GPIO3A1_MASK = 0xf << GPIO3A1_SHIFT,
197 GPIO3A1_GPIO = 0,
198 GPIO3A1_UART5_RX = 4,
199};
200
201
202enum {
203 GPIO0C1_SHIFT = 2,
204 GPIO0C1_MASK = 0x3 << GPIO0C1_SHIFT,
205 GPIO0C1_GPIO = 0,
206 GPIO0C1_PWM_3,
207 GPIO0C1_UART3_RXM0,
208 GPIO0C1_PMU_DEBUG4,
209
210 GPIO0C0_SHIFT = 0,
211 GPIO0C0_MASK = 0x3 << GPIO0C0_SHIFT,
212 GPIO0C0_GPIO = 0,
213 GPIO0C0_PWM_1,
214 GPIO0C0_UART3_TXM0,
215 GPIO0C0_PMU_DEBUG3,
216};
217
218int arch_cpu_init(void)
219{
220 static struct px30_grf * const grf = (void *)GRF_BASE;
221 u32 __maybe_unused val;
222
223#ifdef CONFIG_SPL_BUILD
224
225
226 writel(0x0, DDR_FW_BASE + FW_DDR_CON);
227
228
229 writel(QOS_PRIORITY_LEVEL(1, 1), SERVICE_CORE_ADDR + QOS_PRIORITY);
230
231#if !defined(CONFIG_DEBUG_UART_BOARD_INIT) || \
232 (CONFIG_DEBUG_UART_BASE != 0xff160000) || \
233 (CONFIG_DEBUG_UART_CHANNEL != 0)
234
235 rk_clrsetreg(&grf->gpio1dl_iomux,
236 GPIO1D3_MASK | GPIO1D2_MASK,
237 GPIO1D3_SDMMC_D1 << GPIO1D3_SHIFT |
238 GPIO1D2_SDMMC_D0 << GPIO1D2_SHIFT);
239 rk_clrsetreg(&grf->gpio1dh_iomux,
240 GPIO1D7_MASK | GPIO1D6_MASK | GPIO1D5_MASK | GPIO1D4_MASK,
241 GPIO1D7_SDMMC_CMD << GPIO1D7_SHIFT |
242 GPIO1D6_SDMMC_CLK << GPIO1D6_SHIFT |
243 GPIO1D5_SDMMC_D3 << GPIO1D5_SHIFT |
244 GPIO1D4_SDMMC_D2 << GPIO1D4_SHIFT);
245#endif
246
247#ifdef CONFIG_ROCKCHIP_SFC
248 rk_clrsetreg(&grf->gpio1al_iomux,
249 GPIO1A3_MASK | GPIO1A2_MASK | GPIO1A1_MASK | GPIO1A0_MASK,
250 GPIO1A3_SFC_SIO3 << GPIO1A3_SHIFT |
251 GPIO1A2_SFC_SIO2 << GPIO1A2_SHIFT |
252 GPIO1A1_SFC_SIO1 << GPIO1A1_SHIFT |
253 GPIO1A0_SFC_SIO0 << GPIO1A0_SHIFT);
254 rk_clrsetreg(&grf->gpio1ah_iomux, GPIO1A4_MASK,
255 GPIO1A4_SFC_CSN0 << GPIO1A4_SHIFT);
256 rk_clrsetreg(&grf->gpio1bl_iomux, GPIO1B1_MASK,
257 GPIO1B1_SFC_CLK << GPIO1B1_SHIFT);
258#endif
259
260#endif
261
262
263 rk_clrreg(PMU_PWRDN_CON, 1 << 13);
264
265
266 writel(0x82, VIDEO_PHY_BASE + 0x0000);
267 writel(0x05, VIDEO_PHY_BASE + 0x03ac);
268
269
270 rk_clrreg(&grf->cpu_con[1], 1 << 7);
271
272 return 0;
273}
274
275#ifdef CONFIG_DEBUG_UART_BOARD_INIT
276void board_debug_uart_init(void)
277{
278#if defined(CONFIG_DEBUG_UART_BASE) && \
279 (CONFIG_DEBUG_UART_BASE == 0xff168000) && \
280 (CONFIG_DEBUG_UART_CHANNEL != 1)
281 static struct px30_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
282#endif
283 static struct px30_grf * const grf = (void *)GRF_BASE;
284 static struct px30_cru * const cru = (void *)CRU_BASE;
285
286#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff158000)
287
288 rk_clrsetreg(&cru->clksel_con[34],
289 UART1_PLL_SEL_MASK | UART1_DIV_CON_MASK,
290 UART1_PLL_SEL_24M << UART1_PLL_SEL_SHIFT | 0);
291 rk_clrsetreg(&cru->clksel_con[35],
292 UART1_CLK_SEL_MASK,
293 UART1_CLK_SEL_UART1 << UART1_CLK_SEL_SHIFT);
294
295 rk_clrsetreg(&grf->gpio1cl_iomux,
296 GPIO1C1_MASK | GPIO1C0_MASK,
297 GPIO1C1_UART1_TX << GPIO1C1_SHIFT |
298 GPIO1C0_UART1_RX << GPIO1C0_SHIFT);
299#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff168000)
300
301 enum {
302 CON_IOMUX_UART3SEL_SHIFT = 9,
303 CON_IOMUX_UART3SEL_MASK = 1 << CON_IOMUX_UART3SEL_SHIFT,
304 CON_IOMUX_UART3SEL_M0 = 0,
305 CON_IOMUX_UART3SEL_M1,
306 };
307
308
309 rk_clrsetreg(&cru->clksel_con[40],
310 UART3_PLL_SEL_MASK | UART3_DIV_CON_MASK,
311 UART3_PLL_SEL_24M << UART3_PLL_SEL_SHIFT | 0);
312 rk_clrsetreg(&cru->clksel_con[41],
313 UART3_CLK_SEL_MASK,
314 UART3_CLK_SEL_UART3 << UART3_CLK_SEL_SHIFT);
315
316#if (CONFIG_DEBUG_UART_CHANNEL == 1)
317 rk_clrsetreg(&grf->iofunc_con0,
318 CON_IOMUX_UART3SEL_MASK,
319 CON_IOMUX_UART3SEL_M1 << CON_IOMUX_UART3SEL_SHIFT);
320
321 rk_clrsetreg(&grf->gpio1bh_iomux,
322 GPIO1B7_MASK | GPIO1B6_MASK,
323 GPIO1B7_UART3_RXM1 << GPIO1B7_SHIFT |
324 GPIO1B6_UART3_TXM1 << GPIO1B6_SHIFT);
325#else
326 rk_clrsetreg(&grf->iofunc_con0,
327 CON_IOMUX_UART3SEL_MASK,
328 CON_IOMUX_UART3SEL_M0 << CON_IOMUX_UART3SEL_SHIFT);
329
330 rk_clrsetreg(&pmugrf->gpio0cl_iomux,
331 GPIO0C1_MASK | GPIO0C0_MASK,
332 GPIO0C1_UART3_RXM0 << GPIO0C1_SHIFT |
333 GPIO0C0_UART3_TXM0 << GPIO0C0_SHIFT);
334#endif
335
336#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000)
337
338 rk_clrsetreg(&cru->clksel_con[46],
339 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK,
340 UART5_PLL_SEL_24M << UART5_PLL_SEL_SHIFT | 0);
341 rk_clrsetreg(&cru->clksel_con[47],
342 UART5_CLK_SEL_MASK,
343 UART5_CLK_SEL_UART5 << UART5_CLK_SEL_SHIFT);
344
345 rk_clrsetreg(&grf->gpio3al_iomux,
346 GPIO3A2_MASK | GPIO3A1_MASK,
347 GPIO3A2_UART5_TX << GPIO3A2_SHIFT |
348 GPIO3A1_UART5_RX << GPIO3A1_SHIFT);
349#else
350
351 enum {
352 CON_IOMUX_UART2SEL_SHIFT = 10,
353 CON_IOMUX_UART2SEL_MASK = 3 << CON_IOMUX_UART2SEL_SHIFT,
354 CON_IOMUX_UART2SEL_M0 = 0,
355 CON_IOMUX_UART2SEL_M1,
356 CON_IOMUX_UART2SEL_USBPHY,
357 };
358
359
360 rk_clrsetreg(&cru->clksel_con[37],
361 UART2_PLL_SEL_MASK | UART2_DIV_CON_MASK,
362 UART2_PLL_SEL_24M << UART2_PLL_SEL_SHIFT | 0);
363 rk_clrsetreg(&cru->clksel_con[38],
364 UART2_CLK_SEL_MASK,
365 UART2_CLK_SEL_UART2 << UART2_CLK_SEL_SHIFT);
366
367#if (CONFIG_DEBUG_UART_CHANNEL == 1)
368
369 rk_clrsetreg(&grf->iofunc_con0,
370 CON_IOMUX_UART2SEL_MASK,
371 CON_IOMUX_UART2SEL_M1 << CON_IOMUX_UART2SEL_SHIFT);
372
373 rk_clrsetreg(&grf->gpio2bh_iomux,
374 GPIO2B6_MASK | GPIO2B4_MASK,
375 GPIO2B6_UART2_RXM1 << GPIO2B6_SHIFT |
376 GPIO2B4_UART2_TXM1 << GPIO2B4_SHIFT);
377#else
378 rk_clrsetreg(&grf->iofunc_con0,
379 CON_IOMUX_UART2SEL_MASK,
380 CON_IOMUX_UART2SEL_M0 << CON_IOMUX_UART2SEL_SHIFT);
381
382 rk_clrsetreg(&grf->gpio1dl_iomux,
383 GPIO1D3_MASK | GPIO1D2_MASK,
384 GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT |
385 GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT);
386#endif
387
388#endif
389}
390#endif
391
