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8#ifndef __ASM_ARM_ARCH_PWM_H_
9#define __ASM_ARM_ARCH_PWM_H_
10
11#define PRESCALER_0 (8 - 1)
12#define PRESCALER_1 (16 - 1)
13
14
15#define MUX_DIV_1 0
16#define MUX_DIV_2 1
17#define MUX_DIV_4 2
18#define MUX_DIV_8 3
19#define MUX_DIV_16 4
20
21#define MUX_DIV_SHIFT(x) (x * 4)
22
23#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2)
24
25#define TCON_START(x) (1 << TCON_OFFSET(x))
26#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1))
27#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2))
28#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
29#define TCON4_AUTO_RELOAD (1 << 22)
30
31#ifndef __ASSEMBLY__
32struct s5p_timer {
33 unsigned int tcfg0;
34 unsigned int tcfg1;
35 unsigned int tcon;
36 unsigned int tcntb0;
37 unsigned int tcmpb0;
38 unsigned int tcnto0;
39 unsigned int tcntb1;
40 unsigned int tcmpb1;
41 unsigned int tcnto1;
42 unsigned int tcntb2;
43 unsigned int tcmpb2;
44 unsigned int tcnto2;
45 unsigned int tcntb3;
46 unsigned int res1;
47 unsigned int tcnto3;
48 unsigned int tcntb4;
49 unsigned int tcnto4;
50 unsigned int tintcstat;
51};
52#endif
53
54#endif
55