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6#ifndef _RESET_MANAGER_ARRIA10_H_
7#define _RESET_MANAGER_ARRIA10_H_
8
9#include <dt-bindings/reset/altr,rst-mgr-a10.h>
10#include <linux/bitops.h>
11
12void socfpga_watchdog_disable(void);
13void socfpga_reset_deassert_noc_ddr_scheduler(void);
14int socfpga_reset_deassert_bridges_handoff(void);
15void socfpga_reset_deassert_osc1wd0(void);
16int socfpga_bridges_reset(void);
17
18#define RSTMGR_A10_STATUS 0x00
19#define RSTMGR_A10_CTRL 0x0c
20#define RSTMGR_A10_MPUMODRST 0x20
21#define RSTMGR_A10_PER0MODRST 0x24
22#define RSTMGR_A10_PER1MODRST 0x28
23#define RSTMGR_A10_BRGMODRST 0x2c
24#define RSTMGR_A10_SYSMODRST 0x30
25
26#define RSTMGR_CTRL RSTMGR_A10_CTRL
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35
36#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
37#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
38#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
39#define RSTMGR_NAND RSTMGR_DEFINE(1, 5)
40#define RSTMGR_QSPI RSTMGR_DEFINE(1, 6)
41#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
42#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
43#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17)
44#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18)
45#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
46#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
47#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
48#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
49#define RSTMGR_SPTIMER0 RSTMGR_DEFINE(2, 4)
50#define RSTMGR_SPTIMER1 RSTMGR_DEFINE(2, 5)
51#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
52#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17)
53#define RSTMGR_DDRSCH RSTMGR_DEFINE(3, 6)
54
55#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK BIT(1)
56#define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK BIT(0)
57#define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK BIT(1)
58#define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK BIT(2)
59#define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK BIT(3)
60#define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK BIT(4)
61#define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK BIT(5)
62#define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK BIT(6)
63#define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK BIT(7)
64#define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK BIT(8)
65#define ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK BIT(9)
66#define ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK BIT(10)
67#define ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK BIT(11)
68#define ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK BIT(12)
69#define ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK BIT(13)
70#define ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK BIT(14)
71#define ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK BIT(15)
72#define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK BIT(16)
73#define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK BIT(17)
74#define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK BIT(18)
75#define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK BIT(19)
76#define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK BIT(20)
77#define ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK BIT(21)
78#define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK BIT(22)
79#define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK BIT(24)
80#define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK BIT(25)
81#define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK BIT(26)
82#define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK BIT(27)
83#define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK BIT(28)
84#define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK BIT(29)
85#define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK BIT(30)
86#define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK BIT(31)
87
88#define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK BIT(0)
89#define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK BIT(1)
90#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK BIT(2)
91#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET_MSK BIT(3)
92#define ALT_RSTMGR_PER1MODRST_SPTMR0_SET_MSK BIT(4)
93#define ALT_RSTMGR_PER1MODRST_SPTMR1_SET_MSK BIT(5)
94#define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK BIT(8)
95#define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK BIT(9)
96#define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK BIT(10)
97#define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK BIT(11)
98#define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK BIT(12)
99#define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK BIT(16)
100#define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK BIT(17)
101#define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK BIT(24)
102#define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK BIT(25)
103#define ALT_RSTMGR_PER1MODRST_GPIO2_SET_MSK BIT(26)
104
105#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK BIT(0)
106#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK BIT(1)
107#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK BIT(2)
108#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK BIT(3)
109#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK BIT(4)
110#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK BIT(5)
111#define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK BIT(6)
112
113#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK BIT(0)
114#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK BIT(1)
115#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK BIT(2)
116#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK BIT(3)
117
118#endif
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