LXR uboot/arch/m68k/cpu/mcf52x2/cpu.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2003
   4 * Josef Baumgartner <josef.baumgartner@telex.de>
   5 *
   6 * MCF5282 additionals
   7 * (C) Copyright 2005
   8 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
   9 *
  10 * MCF5275 additions
  11 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
  12 *
  13 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
  14 */
  15
  16#include <common.h>
  17#include <init.h>
  18#include <net.h>
  19#include <vsprintf.h>
  20#include <watchdog.h>
  21#include <command.h>
  22#include <asm/global_data.h>
  23#include <asm/immap.h>
  24#include <asm/io.h>
  25#include <netdev.h>
  26#include <linux/delay.h>
  27#include "cpu.h"
  28
  29DECLARE_GLOBAL_DATA_PTR;
  30
  31#ifdef  CONFIG_M5208
  32int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  33{
  34        rcm_t *rcm = (rcm_t *)(MMAP_RCM);
  35
  36        udelay(1000);
  37
  38        out_8(&rcm->rcr, RCM_RCR_SOFTRST);
  39
  40        /* we don't return! */
  41        return 0;
  42};
  43
  44#if defined(CONFIG_DISPLAY_CPUINFO)
  45int print_cpuinfo(void)
  46{
  47        char buf1[32], buf2[32];
  48
  49        printf("CPU:   Freescale Coldfire MCF5208\n"
  50               "       CPU CLK %s MHz BUS CLK %s MHz\n",
  51               strmhz(buf1, gd->cpu_clk),
  52               strmhz(buf2, gd->bus_clk));
  53        return 0;
  54};
  55#endif /* CONFIG_DISPLAY_CPUINFO */
  56
  57#if defined(CONFIG_WATCHDOG)
  58/* Called by macro WATCHDOG_RESET */
  59void watchdog_reset(void)
  60{
  61        wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  62
  63        out_be16(&wdt->sr, 0x5555);
  64        out_be16(&wdt->sr, 0xaaaa);
  65}
  66
  67int watchdog_disable(void)
  68{
  69        wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  70
  71        /* reset watchdog counter */
  72        out_be16(&wdt->sr, 0x5555);
  73        out_be16(&wdt->sr, 0xaaaa);
  74        /* disable watchdog timer */
  75        out_be16(&wdt->cr, 0);
  76
  77        puts("WATCHDOG:disabled\n");
  78        return (0);
  79}
  80
  81int watchdog_init(void)
  82{
  83        wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  84
  85        /* disable watchdog */
  86        out_be16(&wdt->cr, 0);
  87
  88        /* set timeout and enable watchdog */
  89        out_be16(&wdt->mr,
  90                (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
  91
  92        /* reset watchdog counter */
  93        out_be16(&wdt->sr, 0x5555);
  94        out_be16(&wdt->sr, 0xaaaa);
  95
  96        puts("WATCHDOG:enabled\n");
  97        return (0);
  98}
  99#endif                          /* #ifdef CONFIG_WATCHDOG */
 100#endif                          /* #ifdef CONFIG_M5208 */
 101
 102#ifdef  CONFIG_M5271
 103#if defined(CONFIG_DISPLAY_CPUINFO)
 104/*
 105 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
 106 * determine which one we are running on, based on the Chip Identification
 107 * Register (CIR).
 108 */
 109int print_cpuinfo(void)
 110{
 111        char buf[32];
 112        unsigned short cir;     /* Chip Identification Register */
 113        unsigned short pin;     /* Part identification number */
 114        unsigned char prn;      /* Part revision number */
 115        char *cpu_model;
 116
 117        cir = mbar_readShort(MCF_CCM_CIR);
 118        pin = cir >> MCF_CCM_CIR_PIN_LEN;
 119        prn = cir & MCF_CCM_CIR_PRN_MASK;
 120
 121        switch (pin) {
 122        case MCF_CCM_CIR_PIN_MCF5270:
 123                cpu_model = "5270";
 124                break;
 125        case MCF_CCM_CIR_PIN_MCF5271:
 126                cpu_model = "5271";
 127                break;
 128        default:
 129                cpu_model = NULL;
 130                break;
 131        }
 132
 133        if (cpu_model)
 134                printf("CPU:   Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
 135                       cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
 136        else
 137                printf("CPU:   Unknown - Freescale ColdFire MCF5271 family"
 138                       " (PIN: 0x%x) rev. %hu, at %s MHz\n",
 139                       pin, prn, strmhz(buf, CONFIG_SYS_CLK));
 140
 141        return 0;
 142}
 143#endif /* CONFIG_DISPLAY_CPUINFO */
 144
 145int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 146{
 147        /* Call the board specific reset actions first. */
 148        if(board_reset) {
 149                board_reset();
 150        }
 151
 152        mbar_writeByte(MCF_RCM_RCR,
 153                       MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
 154        return 0;
 155};
 156
 157#if defined(CONFIG_WATCHDOG)
 158void watchdog_reset(void)
 159{
 160        mbar_writeShort(MCF_WTM_WSR, 0x5555);
 161        mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
 162}
 163
 164int watchdog_disable(void)
 165{
 166        mbar_writeShort(MCF_WTM_WCR, 0);
 167        return (0);
 168}
 169
 170int watchdog_init(void)
 171{
 172        mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
 173        return (0);
 174}
 175#endif                          /* #ifdef CONFIG_WATCHDOG */
 176
 177#endif
 178
 179#ifdef  CONFIG_M5272
 180int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 181{
 182        wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
 183
 184        out_be16(&wdp->wdog_wrrr, 0);
 185        udelay(1000);
 186
 187        /* enable watchdog, set timeout to 0 and wait */
 188        out_be16(&wdp->wdog_wrrr, 1);
 189        while (1) ;
 190
 191        /* we don't return! */
 192        return 0;
 193};
 194
 195#if defined(CONFIG_DISPLAY_CPUINFO)
 196int print_cpuinfo(void)
 197{
 198        sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
 199        uchar msk;
 200        char *suf;
 201
 202        puts("CPU:   ");
 203        msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
 204        switch (msk) {
 205        case 0x2:
 206                suf = "1K75N";
 207                break;
 208        case 0x4:
 209                suf = "3K75N";
 210                break;
 211        default:
 212                suf = NULL;
 213                printf("Freescale MCF5272 (Mask:%01x)\n", msk);
 214                break;
 215        }
 216
 217        if (suf)
 218                printf("Freescale MCF5272 %s\n", suf);
 219        return 0;
 220};
 221#endif /* CONFIG_DISPLAY_CPUINFO */
 222
 223#if defined(CONFIG_WATCHDOG)
 224/* Called by macro WATCHDOG_RESET */
 225void watchdog_reset(void)
 226{
 227        wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 228
 229        out_be16(&wdt->wdog_wcr, 0);
 230}
 231
 232int watchdog_disable(void)
 233{
 234        wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 235
 236        /* reset watchdog counter */
 237        out_be16(&wdt->wdog_wcr, 0);
 238        /* disable watchdog interrupt */
 239        out_be16(&wdt->wdog_wirr, 0);
 240        /* disable watchdog timer */
 241        out_be16(&wdt->wdog_wrrr, 0);
 242
 243        puts("WATCHDOG:disabled\n");
 244        return (0);
 245}
 246
 247int watchdog_init(void)
 248{
 249        wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 250
 251        /* disable watchdog interrupt */
 252        out_be16(&wdt->wdog_wirr, 0);
 253
 254        /* set timeout and enable watchdog */
 255        out_be16(&wdt->wdog_wrrr,
 256                (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
 257
 258        /* reset watchdog counter */
 259        out_be16(&wdt->wdog_wcr, 0);
 260
 261        puts("WATCHDOG:enabled\n");
 262        return (0);
 263}
 264#endif                          /* #ifdef CONFIG_WATCHDOG */
 265
 266#endif                          /* #ifdef CONFIG_M5272 */
 267
 268#ifdef  CONFIG_M5275
 269int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 270{
 271        rcm_t *rcm = (rcm_t *)(MMAP_RCM);
 272
 273        udelay(1000);
 274
 275        out_8(&rcm->rcr, RCM_RCR_SOFTRST);
 276
 277        /* we don't return! */
 278        return 0;
 279};
 280
 281#if defined(CONFIG_DISPLAY_CPUINFO)
 282int print_cpuinfo(void)
 283{
 284        char buf[32];
 285
 286        printf("CPU:   Freescale Coldfire MCF5275 at %s MHz\n",
 287                        strmhz(buf, CONFIG_SYS_CLK));
 288        return 0;
 289};
 290#endif /* CONFIG_DISPLAY_CPUINFO */
 291
 292#if defined(CONFIG_WATCHDOG)
 293/* Called by macro WATCHDOG_RESET */
 294void watchdog_reset(void)
 295{
 296        wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 297
 298        out_be16(&wdt->wsr, 0x5555);
 299        out_be16(&wdt->wsr, 0xaaaa);
 300}
 301
 302int watchdog_disable(void)
 303{
 304        wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 305
 306        /* reset watchdog counter */
 307        out_be16(&wdt->wsr, 0x5555);
 308        out_be16(&wdt->wsr, 0xaaaa);
 309
 310        /* disable watchdog timer */
 311        out_be16(&wdt->wcr, 0);
 312
 313        puts("WATCHDOG:disabled\n");
 314        return (0);
 315}
 316
 317int watchdog_init(void)
 318{
 319        wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 320
 321        /* disable watchdog */
 322        out_be16(&wdt->wcr, 0);
 323
 324        /* set timeout and enable watchdog */
 325        out_be16(&wdt->wmr,
 326                (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
 327
 328        /* reset watchdog counter */
 329        out_be16(&wdt->wsr, 0x5555);
 330        out_be16(&wdt->wsr, 0xaaaa);
 331
 332        puts("WATCHDOG:enabled\n");
 333        return (0);
 334}
 335#endif                          /* #ifdef CONFIG_WATCHDOG */
 336
 337#endif                          /* #ifdef CONFIG_M5275 */
 338
 339#ifdef  CONFIG_M5282
 340#if defined(CONFIG_DISPLAY_CPUINFO)
 341int print_cpuinfo(void)
 342{
 343        unsigned char resetsource = MCFRESET_RSR;
 344
 345        printf("CPU:   Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
 346               MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
 347        printf("Reset:%s%s%s%s%s%s%s\n",
 348               (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
 349               (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
 350               (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
 351               (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
 352               (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
 353               (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
 354               (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
 355        return 0;
 356}
 357#endif /* CONFIG_DISPLAY_CPUINFO */
 358
 359int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 360{
 361        MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
 362        return 0;
 363};
 364#endif
 365
 366#ifdef CONFIG_M5249
 367#if defined(CONFIG_DISPLAY_CPUINFO)
 368int print_cpuinfo(void)
 369{
 370        char buf[32];
 371
 372        printf("CPU:   Freescale Coldfire MCF5249 at %s MHz\n",
 373               strmhz(buf, CONFIG_SYS_CLK));
 374        return 0;
 375}
 376#endif /* CONFIG_DISPLAY_CPUINFO */
 377
 378int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 379{
 380        /* enable watchdog, set timeout to 0 and wait */
 381        mbar_writeByte(MCFSIM_SYPCR, 0xc0);
 382        while (1) ;
 383
 384        /* we don't return! */
 385        return 0;
 386};
 387#endif
 388
 389#ifdef CONFIG_M5253
 390#if defined(CONFIG_DISPLAY_CPUINFO)
 391int print_cpuinfo(void)
 392{
 393        char buf[32];
 394
 395        unsigned char resetsource = mbar_readLong(SIM_RSR);
 396        printf("CPU:   Freescale Coldfire MCF5253 at %s MHz\n",
 397               strmhz(buf, CONFIG_SYS_CLK));
 398
 399        if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
 400                printf("Reset:%s%s\n",
 401                       (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
 402                       : "",
 403                       (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
 404                       "");
 405        }
 406        return 0;
 407}
 408#endif /* CONFIG_DISPLAY_CPUINFO */
 409
 410int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 411{
 412        /* enable watchdog, set timeout to 0 and wait */
 413        mbar_writeByte(SIM_SYPCR, 0xc0);
 414        while (1) ;
 415
 416        /* we don't return! */
 417        return 0;
 418};
 419#endif
 420
 421#if defined(CONFIG_MCFFEC)
 422/* Default initializations for MCFFEC controllers.  To override,
 423 * create a board-specific function called:
 424 *      int board_eth_init(struct bd_info *bis)
 425 */
 426
 427int cpu_eth_init(struct bd_info *bis)
 428{
 429        return mcffec_initialize(bis);
 430}
 431#endif
 432