1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2020 Marvell International Ltd. 4 * 5 * Configuration and status register (CSR) type definitions for 6 * Octeon asxx. 7 */ 8 9#ifndef __CVMX_ASXX_DEFS_H__ 10#define __CVMX_ASXX_DEFS_H__ 11 12#define CVMX_ASXX_GMII_RX_CLK_SET(offset) (0x00011800B0000180ull) 13#define CVMX_ASXX_GMII_RX_DAT_SET(offset) (0x00011800B0000188ull) 14#define CVMX_ASXX_INT_EN(offset) (0x00011800B0000018ull + ((offset) & 1) * 0x8000000ull) 15#define CVMX_ASXX_INT_REG(offset) (0x00011800B0000010ull + ((offset) & 1) * 0x8000000ull) 16#define CVMX_ASXX_MII_RX_DAT_SET(offset) (0x00011800B0000190ull) 17#define CVMX_ASXX_PRT_LOOP(offset) (0x00011800B0000040ull + ((offset) & 1) * 0x8000000ull) 18#define CVMX_ASXX_RLD_BYPASS(offset) (0x00011800B0000248ull + ((offset) & 1) * 0x8000000ull) 19#define CVMX_ASXX_RLD_BYPASS_SETTING(offset) (0x00011800B0000250ull + ((offset) & 1) * 0x8000000ull) 20#define CVMX_ASXX_RLD_COMP(offset) (0x00011800B0000220ull + ((offset) & 1) * 0x8000000ull) 21#define CVMX_ASXX_RLD_DATA_DRV(offset) (0x00011800B0000218ull + ((offset) & 1) * 0x8000000ull) 22#define CVMX_ASXX_RLD_FCRAM_MODE(offset) (0x00011800B0000210ull + ((offset) & 1) * 0x8000000ull) 23#define CVMX_ASXX_RLD_NCTL_STRONG(offset) (0x00011800B0000230ull + ((offset) & 1) * 0x8000000ull) 24#define CVMX_ASXX_RLD_NCTL_WEAK(offset) (0x00011800B0000240ull + ((offset) & 1) * 0x8000000ull) 25#define CVMX_ASXX_RLD_PCTL_STRONG(offset) (0x00011800B0000228ull + ((offset) & 1) * 0x8000000ull) 26#define CVMX_ASXX_RLD_PCTL_WEAK(offset) (0x00011800B0000238ull + ((offset) & 1) * 0x8000000ull) 27#define CVMX_ASXX_RLD_SETTING(offset) (0x00011800B0000258ull + ((offset) & 1) * 0x8000000ull) 28#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \ 29 (0x00011800B0000020ull + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) 30#define CVMX_ASXX_RX_PRT_EN(offset) (0x00011800B0000000ull + ((offset) & 1) * 0x8000000ull) 31#define CVMX_ASXX_RX_WOL(offset) (0x00011800B0000100ull + ((offset) & 1) * 0x8000000ull) 32#define CVMX_ASXX_RX_WOL_MSK(offset) (0x00011800B0000108ull + ((offset) & 1) * 0x8000000ull) 33#define CVMX_ASXX_RX_WOL_POWOK(offset) (0x00011800B0000118ull + ((offset) & 1) * 0x8000000ull) 34#define CVMX_ASXX_RX_WOL_SIG(offset) (0x00011800B0000110ull + ((offset) & 1) * 0x8000000ull) 35#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \ 36 (0x00011800B0000048ull + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) 37#define CVMX_ASXX_TX_COMP_BYP(offset) (0x00011800B0000068ull + ((offset) & 1) * 0x8000000ull) 38#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \ 39 (0x00011800B0000080ull + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8) 40#define CVMX_ASXX_TX_PRT_EN(offset) (0x00011800B0000008ull + ((offset) & 1) * 0x8000000ull) 41 42/** 43 * cvmx_asx#_gmii_rx_clk_set 44 * 45 * ASX_GMII_RX_CLK_SET = GMII Clock delay setting 46 * 47 */ 48union cvmx_asxx_gmii_rx_clk_set { 49 u64 u64; 50 struct cvmx_asxx_gmii_rx_clk_set_s { 51 u64 reserved_5_63 : 59; 52 u64 setting : 5; 53 } s; 54 struct cvmx_asxx_gmii_rx_clk_set_s cn30xx; 55 struct cvmx_asxx_gmii_rx_clk_set_s cn31xx; 56 struct cvmx_asxx_gmii_rx_clk_set_s cn50xx; 57}; 58 59typedef union cvmx_asxx_gmii_rx_clk_set cvmx_asxx_gmii_rx_clk_set_t; 60 61/** 62 * cvmx_asx#_gmii_rx_dat_set 63 * 64 * ASX_GMII_RX_DAT_SET = GMII Clock delay setting 65 * 66 */ 67union cvmx_asxx_gmii_rx_dat_set { 68 u64 u64; 69 struct cvmx_asxx_gmii_rx_dat_set_s { 70 u64 reserved_5_63 : 59; 71 u64 setting : 5; 72 } s; 73 struct cvmx_asxx_gmii_rx_dat_set_s cn30xx; 74 struct cvmx_asxx_gmii_rx_dat_set_s cn31xx; 75 struct cvmx_asxx_gmii_rx_dat_set_s cn50xx; 76}; 77 78typedef union cvmx_asxx_gmii_rx_dat_set cvmx_asxx_gmii_rx_dat_set_t; 79 80/** 81 * cvmx_asx#_int_en 82 * 83 * ASX_INT_EN = Interrupt Enable 84 * 85 */ 86union cvmx_asxx_int_en { 87 u64 u64; 88 struct cvmx_asxx_int_en_s { 89 u64 reserved_12_63 : 52; 90 u64 txpsh : 4; 91 u64 txpop : 4; 92 u64 ovrflw : 4; 93 } s; 94 struct cvmx_asxx_int_en_cn30xx { 95 u64 reserved_11_63 : 53; 96 u64 txpsh : 3; 97 u64 reserved_7_7 : 1; 98 u64 txpop : 3; 99 u64 reserved_3_3 : 1; 100 u64 ovrflw : 3; 101 } cn30xx; 102 struct cvmx_asxx_int_en_cn30xx cn31xx; 103 struct cvmx_asxx_int_en_s cn38xx; 104 struct cvmx_asxx_int_en_s cn38xxp2; 105 struct cvmx_asxx_int_en_cn30xx cn50xx; 106 struct cvmx_asxx_int_en_s cn58xx; 107 struct cvmx_asxx_int_en_s cn58xxp1; 108}; 109 110typedef union cvmx_asxx_int_en cvmx_asxx_int_en_t; 111 112/** 113 * cvmx_asx#_int_reg 114 * 115 * ASX_INT_REG = Interrupt Register 116 * 117 */ 118union cvmx_asxx_int_reg { 119 u64 u64; 120 struct cvmx_asxx_int_reg_s { 121 u64 reserved_12_63 : 52; 122 u64 txpsh : 4; 123 u64 txpop : 4; 124 u64 ovrflw : 4; 125 } s; 126 struct cvmx_asxx_int_reg_cn30xx { 127 u64 reserved_11_63 : 53; 128 u64 txpsh : 3; 129 u64 reserved_7_7 : 1; 130 u64 txpop : 3; 131 u64 reserved_3_3 : 1; 132 u64 ovrflw : 3; 133 } cn30xx; 134 struct cvmx_asxx_int_reg_cn30xx cn31xx; 135 struct cvmx_asxx_int_reg_s cn38xx; 136 struct cvmx_asxx_int_reg_s cn38xxp2; 137 struct cvmx_asxx_int_reg_cn30xx cn50xx; 138 struct cvmx_asxx_int_reg_s cn58xx; 139 struct cvmx_asxx_int_reg_s cn58xxp1; 140}; 141 142typedef union cvmx_asxx_int_reg cvmx_asxx_int_reg_t; 143 144/** 145 * cvmx_asx#_mii_rx_dat_set 146 * 147 * ASX_MII_RX_DAT_SET = GMII Clock delay setting 148 * 149 */ 150union cvmx_asxx_mii_rx_dat_set { 151 u64 u64; 152 struct cvmx_asxx_mii_rx_dat_set_s { 153 u64 reserved_5_63 : 59; 154 u64 setting : 5; 155 } s; 156 struct cvmx_asxx_mii_rx_dat_set_s cn30xx; 157 struct cvmx_asxx_mii_rx_dat_set_s cn50xx; 158}; 159 160typedef union cvmx_asxx_mii_rx_dat_set cvmx_asxx_mii_rx_dat_set_t; 161 162/** 163 * cvmx_asx#_prt_loop 164 * 165 * ASX_PRT_LOOP = Internal Loopback mode - TX FIFO output goes into RX FIFO (and maybe pins) 166 * 167 */ 168union cvmx_asxx_prt_loop { 169 u64 u64; 170 struct cvmx_asxx_prt_loop_s { 171 u64 reserved_8_63 : 56; 172 u64 ext_loop : 4; 173 u64 int_loop : 4; 174 } s; 175 struct cvmx_asxx_prt_loop_cn30xx { 176 u64 reserved_7_63 : 57; 177 u64 ext_loop : 3; 178 u64 reserved_3_3 : 1; 179 u64 int_loop : 3; 180 } cn30xx; 181 struct cvmx_asxx_prt_loop_cn30xx cn31xx; 182 struct cvmx_asxx_prt_loop_s cn38xx; 183 struct cvmx_asxx_prt_loop_s cn38xxp2; 184 struct cvmx_asxx_prt_loop_cn30xx cn50xx; 185 struct cvmx_asxx_prt_loop_s cn58xx; 186 struct cvmx_asxx_prt_loop_s cn58xxp1; 187}; 188 189typedef union cvmx_asxx_prt_loop cvmx_asxx_prt_loop_t; 190 191/** 192 * cvmx_asx#_rld_bypass 193 * 194 * ASX_RLD_BYPASS 195 * 196 */ 197union cvmx_asxx_rld_bypass { 198 u64 u64; 199 struct cvmx_asxx_rld_bypass_s { 200 u64 reserved_1_63 : 63; 201 u64 bypass : 1; 202 } s; 203 struct cvmx_asxx_rld_bypass_s cn38xx; 204 struct cvmx_asxx_rld_bypass_s cn38xxp2; 205 struct cvmx_asxx_rld_bypass_s cn58xx; 206 struct cvmx_asxx_rld_bypass_s cn58xxp1; 207}; 208 209typedef union cvmx_asxx_rld_bypass cvmx_asxx_rld_bypass_t; 210 211/** 212 * cvmx_asx#_rld_bypass_setting 213 * 214 * ASX_RLD_BYPASS_SETTING 215 * 216 */ 217union cvmx_asxx_rld_bypass_setting { 218 u64 u64; 219 struct cvmx_asxx_rld_bypass_setting_s { 220 u64 reserved_5_63 : 59; 221 u64 setting : 5; 222 } s; 223 struct cvmx_asxx_rld_bypass_setting_s cn38xx; 224 struct cvmx_asxx_rld_bypass_setting_s cn38xxp2; 225 struct cvmx_asxx_rld_bypass_setting_s cn58xx; 226 struct cvmx_asxx_rld_bypass_setting_s cn58xxp1; 227}; 228 229typedef union cvmx_asxx_rld_bypass_setting cvmx_asxx_rld_bypass_setting_t; 230 231/** 232 * cvmx_asx#_rld_comp 233 * 234 * ASX_RLD_COMP 235 * 236 */ 237union cvmx_asxx_rld_comp { 238 u64 u64; 239 struct cvmx_asxx_rld_comp_s { 240 u64 reserved_9_63 : 55; 241 u64 pctl : 5; 242 u64 nctl : 4; 243 } s; 244 struct cvmx_asxx_rld_comp_cn38xx { 245 u64 reserved_8_63 : 56; 246 u64 pctl : 4; 247 u64 nctl : 4; 248 } cn38xx; 249 struct cvmx_asxx_rld_comp_cn38xx cn38xxp2; 250 struct cvmx_asxx_rld_comp_s cn58xx; 251 struct cvmx_asxx_rld_comp_s cn58xxp1; 252}; 253 254typedef union cvmx_asxx_rld_comp cvmx_asxx_rld_comp_t; 255 256/** 257 * cvmx_asx#_rld_data_drv 258 * 259 * ASX_RLD_DATA_DRV 260 * 261 */ 262union cvmx_asxx_rld_data_drv { 263 u64 u64; 264 struct cvmx_asxx_rld_data_drv_s { 265 u64 reserved_8_63 : 56; 266 u64 pctl : 4; 267 u64 nctl : 4; 268 } s; 269 struct cvmx_asxx_rld_data_drv_s cn38xx; 270 struct cvmx_asxx_rld_data_drv_s cn38xxp2; 271 struct cvmx_asxx_rld_data_drv_s cn58xx; 272 struct cvmx_asxx_rld_data_drv_s cn58xxp1; 273}; 274 275typedef union cvmx_asxx_rld_data_drv cvmx_asxx_rld_data_drv_t; 276 277/** 278 * cvmx_asx#_rld_fcram_mode 279 * 280 * ASX_RLD_FCRAM_MODE 281 * 282 */ 283union cvmx_asxx_rld_fcram_mode { 284 u64 u64; 285 struct cvmx_asxx_rld_fcram_mode_s { 286 u64 reserved_1_63 : 63; 287 u64 mode : 1; 288 } s; 289 struct cvmx_asxx_rld_fcram_mode_s cn38xx; 290 struct cvmx_asxx_rld_fcram_mode_s cn38xxp2; 291}; 292 293typedef union cvmx_asxx_rld_fcram_mode cvmx_asxx_rld_fcram_mode_t; 294 295/** 296 * cvmx_asx#_rld_nctl_strong 297 * 298 * ASX_RLD_NCTL_STRONG 299 * 300 */ 301union cvmx_asxx_rld_nctl_strong { 302 u64 u64; 303 struct cvmx_asxx_rld_nctl_strong_s { 304 u64 reserved_5_63 : 59; 305 u64 nctl : 5; 306 } s; 307 struct cvmx_asxx_rld_nctl_strong_s cn38xx; 308 struct cvmx_asxx_rld_nctl_strong_s cn38xxp2; 309 struct cvmx_asxx_rld_nctl_strong_s cn58xx; 310 struct cvmx_asxx_rld_nctl_strong_s cn58xxp1; 311}; 312 313typedef union cvmx_asxx_rld_nctl_strong cvmx_asxx_rld_nctl_strong_t; 314 315/** 316 * cvmx_asx#_rld_nctl_weak 317 * 318 * ASX_RLD_NCTL_WEAK 319 * 320 */ 321union cvmx_asxx_rld_nctl_weak { 322 u64 u64; 323 struct cvmx_asxx_rld_nctl_weak_s { 324 u64 reserved_5_63 : 59; 325 u64 nctl : 5; 326 } s; 327 struct cvmx_asxx_rld_nctl_weak_s cn38xx; 328 struct cvmx_asxx_rld_nctl_weak_s cn38xxp2; 329 struct cvmx_asxx_rld_nctl_weak_s cn58xx; 330 struct cvmx_asxx_rld_nctl_weak_s cn58xxp1; 331}; 332 333typedef union cvmx_asxx_rld_nctl_weak cvmx_asxx_rld_nctl_weak_t; 334 335/** 336 * cvmx_asx#_rld_pctl_strong 337 * 338 * ASX_RLD_PCTL_STRONG 339 * 340 */ 341union cvmx_asxx_rld_pctl_strong { 342 u64 u64; 343 struct cvmx_asxx_rld_pctl_strong_s { 344 u64 reserved_5_63 : 59; 345 u64 pctl : 5; 346 } s; 347 struct cvmx_asxx_rld_pctl_strong_s cn38xx; 348 struct cvmx_asxx_rld_pctl_strong_s cn38xxp2; 349 struct cvmx_asxx_rld_pctl_strong_s cn58xx; 350 struct cvmx_asxx_rld_pctl_strong_s cn58xxp1; 351}; 352 353typedef union cvmx_asxx_rld_pctl_strong cvmx_asxx_rld_pctl_strong_t; 354 355/** 356 * cvmx_asx#_rld_pctl_weak 357 * 358 * ASX_RLD_PCTL_WEAK 359 * 360 */ 361union cvmx_asxx_rld_pctl_weak { 362 u64 u64; 363 struct cvmx_asxx_rld_pctl_weak_s { 364 u64 reserved_5_63 : 59; 365 u64 pctl : 5; 366 } s; 367 struct cvmx_asxx_rld_pctl_weak_s cn38xx; 368 struct cvmx_asxx_rld_pctl_weak_s cn38xxp2; 369 struct cvmx_asxx_rld_pctl_weak_s cn58xx; 370 struct cvmx_asxx_rld_pctl_weak_s cn58xxp1; 371}; 372 373typedef union cvmx_asxx_rld_pctl_weak cvmx_asxx_rld_pctl_weak_t; 374 375/** 376 * cvmx_asx#_rld_setting 377 * 378 * ASX_RLD_SETTING 379 * 380 */ 381union cvmx_asxx_rld_setting { 382 u64 u64; 383 struct cvmx_asxx_rld_setting_s { 384 u64 reserved_13_63 : 51; 385 u64 dfaset : 5; 386 u64 dfalag : 1; 387 u64 dfalead : 1; 388 u64 dfalock : 1; 389 u64 setting : 5; 390 } s; 391 struct cvmx_asxx_rld_setting_cn38xx { 392 u64 reserved_5_63 : 59; 393 u64 setting : 5; 394 } cn38xx; 395 struct cvmx_asxx_rld_setting_cn38xx cn38xxp2; 396 struct cvmx_asxx_rld_setting_s cn58xx; 397 struct cvmx_asxx_rld_setting_s cn58xxp1; 398}; 399 400typedef union cvmx_asxx_rld_setting cvmx_asxx_rld_setting_t; 401 402/** 403 * cvmx_asx#_rx_clk_set# 404 * 405 * ASX_RX_CLK_SET = RGMII Clock delay setting 406 * 407 * 408 * Notes: 409 * Setting to place on the open-loop RXC (RGMII receive clk) 410 * delay line, which can delay the received clock. This 411 * can be used if the board and/or transmitting device 412 * has not otherwise delayed the clock. 413 * 414 * A value of SETTING=0 disables the delay line. The delay 415 * line should be disabled unless the transmitter or board 416 * does not delay the clock. 417 * 418 * Note that this delay line provides only a coarse control 419 * over the delay. Generally, it can only reliably provide 420 * a delay in the range 1.25-2.5ns, which may not be adequate 421 * for some system applications. 422 * 423 * The open loop delay line selects 424 * from among a series of tap positions. Each incremental 425 * tap position adds a delay of 50ps to 135ps per tap, depending 426 * on the chip, its temperature, and the voltage. 427 * To achieve from 1.25-2.5ns of delay on the received 428 * clock, a fixed value of SETTING=24 may work. 429 * For more precision, we recommend the following settings 430 * based on the chip voltage: 431 * 432 * VDD SETTING 433 * ----------------------------- 434 * 1.0 18 435 * 1.05 19 436 * 1.1 21 437 * 1.15 22 438 * 1.2 23 439 * 1.25 24 440 * 1.3 25 441 */ 442union cvmx_asxx_rx_clk_setx { 443 u64 u64; 444 struct cvmx_asxx_rx_clk_setx_s { 445 u64 reserved_5_63 : 59; 446 u64 setting : 5; 447 } s; 448 struct cvmx_asxx_rx_clk_setx_s cn30xx; 449 struct cvmx_asxx_rx_clk_setx_s cn31xx; 450 struct cvmx_asxx_rx_clk_setx_s cn38xx; 451 struct cvmx_asxx_rx_clk_setx_s cn38xxp2; 452 struct cvmx_asxx_rx_clk_setx_s cn50xx; 453 struct cvmx_asxx_rx_clk_setx_s cn58xx; 454 struct cvmx_asxx_rx_clk_setx_s cn58xxp1; 455}; 456 457typedef union cvmx_asxx_rx_clk_setx cvmx_asxx_rx_clk_setx_t; 458 459/** 460 * cvmx_asx#_rx_prt_en 461 * 462 * ASX_RX_PRT_EN = RGMII Port Enable 463 * 464 */ 465union cvmx_asxx_rx_prt_en { 466 u64 u64; 467 struct cvmx_asxx_rx_prt_en_s { 468 u64 reserved_4_63 : 60; 469 u64 prt_en : 4; 470 } s; 471 struct cvmx_asxx_rx_prt_en_cn30xx { 472 u64 reserved_3_63 : 61; 473 u64 prt_en : 3; 474 } cn30xx; 475 struct cvmx_asxx_rx_prt_en_cn30xx cn31xx; 476 struct cvmx_asxx_rx_prt_en_s cn38xx; 477 struct cvmx_asxx_rx_prt_en_s cn38xxp2; 478 struct cvmx_asxx_rx_prt_en_cn30xx cn50xx; 479 struct cvmx_asxx_rx_prt_en_s cn58xx; 480 struct cvmx_asxx_rx_prt_en_s cn58xxp1; 481}; 482 483typedef union cvmx_asxx_rx_prt_en cvmx_asxx_rx_prt_en_t; 484 485/** 486 * cvmx_asx#_rx_wol 487 * 488 * ASX_RX_WOL = RGMII RX Wake on LAN status register 489 * 490 */ 491union cvmx_asxx_rx_wol { 492 u64 u64; 493 struct cvmx_asxx_rx_wol_s { 494 u64 reserved_2_63 : 62; 495 u64 status : 1; 496 u64 enable : 1; 497 } s; 498 struct cvmx_asxx_rx_wol_s cn38xx; 499 struct cvmx_asxx_rx_wol_s cn38xxp2; 500}; 501 502typedef union cvmx_asxx_rx_wol cvmx_asxx_rx_wol_t; 503 504/** 505 * cvmx_asx#_rx_wol_msk 506 * 507 * ASX_RX_WOL_MSK = RGMII RX Wake on LAN byte mask 508 * 509 */ 510union cvmx_asxx_rx_wol_msk { 511 u64 u64; 512 struct cvmx_asxx_rx_wol_msk_s { 513 u64 msk : 64; 514 } s; 515 struct cvmx_asxx_rx_wol_msk_s cn38xx; 516 struct cvmx_asxx_rx_wol_msk_s cn38xxp2; 517}; 518 519typedef union cvmx_asxx_rx_wol_msk cvmx_asxx_rx_wol_msk_t; 520 521/** 522 * cvmx_asx#_rx_wol_powok 523 * 524 * ASX_RX_WOL_POWOK = RGMII RX Wake on LAN Power OK 525 * 526 */ 527union cvmx_asxx_rx_wol_powok { 528 u64 u64; 529 struct cvmx_asxx_rx_wol_powok_s { 530 u64 reserved_1_63 : 63; 531 u64 powerok : 1; 532 } s; 533 struct cvmx_asxx_rx_wol_powok_s cn38xx; 534 struct cvmx_asxx_rx_wol_powok_s cn38xxp2; 535}; 536 537typedef union cvmx_asxx_rx_wol_powok cvmx_asxx_rx_wol_powok_t; 538 539/** 540 * cvmx_asx#_rx_wol_sig 541 * 542 * ASX_RX_WOL_SIG = RGMII RX Wake on LAN CRC signature 543 * 544 */ 545union cvmx_asxx_rx_wol_sig { 546 u64 u64; 547 struct cvmx_asxx_rx_wol_sig_s { 548 u64 reserved_32_63 : 32; 549 u64 sig : 32; 550 } s; 551 struct cvmx_asxx_rx_wol_sig_s cn38xx; 552 struct cvmx_asxx_rx_wol_sig_s cn38xxp2; 553}; 554 555typedef union cvmx_asxx_rx_wol_sig cvmx_asxx_rx_wol_sig_t; 556 557/** 558 * cvmx_asx#_tx_clk_set# 559 * 560 * ASX_TX_CLK_SET = RGMII Clock delay setting 561 * 562 * 563 * Notes: 564 * Setting to place on the open-loop TXC (RGMII transmit clk) 565 * delay line, which can delay the transmited clock. This 566 * can be used if the board and/or transmitting device 567 * has not otherwise delayed the clock. 568 * 569 * A value of SETTING=0 disables the delay line. The delay 570 * line should be disabled unless the transmitter or board 571 * does not delay the clock. 572 * 573 * Note that this delay line provides only a coarse control 574 * over the delay. Generally, it can only reliably provide 575 * a delay in the range 1.25-2.5ns, which may not be adequate 576 * for some system applications. 577 * 578 * The open loop delay line selects 579 * from among a series of tap positions. Each incremental 580 * tap position adds a delay of 50ps to 135ps per tap, depending 581 * on the chip, its temperature, and the voltage. 582 * To achieve from 1.25-2.5ns of delay on the received 583 * clock, a fixed value of SETTING=24 may work. 584 * For more precision, we recommend the following settings 585 * based on the chip voltage: 586 * 587 * VDD SETTING 588 * ----------------------------- 589 * 1.0 18 590 * 1.05 19 591 * 1.1 21 592 * 1.15 22 593 * 1.2 23 594 * 1.25 24 595 * 1.3 25 596 */ 597union cvmx_asxx_tx_clk_setx { 598 u64 u64; 599 struct cvmx_asxx_tx_clk_setx_s { 600 u64 reserved_5_63 : 59; 601 u64 setting : 5; 602 } s; 603 struct cvmx_asxx_tx_clk_setx_s cn30xx; 604 struct cvmx_asxx_tx_clk_setx_s cn31xx; 605 struct cvmx_asxx_tx_clk_setx_s cn38xx; 606 struct cvmx_asxx_tx_clk_setx_s cn38xxp2; 607 struct cvmx_asxx_tx_clk_setx_s cn50xx; 608 struct cvmx_asxx_tx_clk_setx_s cn58xx; 609 struct cvmx_asxx_tx_clk_setx_s cn58xxp1; 610}; 611 612typedef union cvmx_asxx_tx_clk_setx cvmx_asxx_tx_clk_setx_t; 613 614/** 615 * cvmx_asx#_tx_comp_byp 616 * 617 * ASX_TX_COMP_BYP = RGMII Clock delay setting 618 * 619 */ 620union cvmx_asxx_tx_comp_byp { 621 u64 u64; 622 struct cvmx_asxx_tx_comp_byp_s { 623 u64 reserved_0_63 : 64; 624 } s; 625 struct cvmx_asxx_tx_comp_byp_cn30xx { 626 u64 reserved_9_63 : 55; 627 u64 bypass : 1; 628 u64 pctl : 4; 629 u64 nctl : 4; 630 } cn30xx; 631 struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx; 632 struct cvmx_asxx_tx_comp_byp_cn38xx { 633 u64 reserved_8_63 : 56; 634 u64 pctl : 4; 635 u64 nctl : 4; 636 } cn38xx; 637 struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2; 638 struct cvmx_asxx_tx_comp_byp_cn50xx { 639 u64 reserved_17_63 : 47; 640 u64 bypass : 1; 641 u64 reserved_13_15 : 3; 642 u64 pctl : 5; 643 u64 reserved_5_7 : 3; 644 u64 nctl : 5; 645 } cn50xx; 646 struct cvmx_asxx_tx_comp_byp_cn58xx { 647 u64 reserved_13_63 : 51; 648 u64 pctl : 5; 649 u64 reserved_5_7 : 3; 650 u64 nctl : 5; 651 } cn58xx; 652 struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1; 653}; 654 655typedef union cvmx_asxx_tx_comp_byp cvmx_asxx_tx_comp_byp_t; 656 657/** 658 * cvmx_asx#_tx_hi_water# 659 * 660 * ASX_TX_HI_WATER = RGMII TX FIFO Hi WaterMark 661 * 662 */ 663union cvmx_asxx_tx_hi_waterx { 664 u64 u64; 665 struct cvmx_asxx_tx_hi_waterx_s { 666 u64 reserved_4_63 : 60; 667 u64 mark : 4; 668 } s; 669 struct cvmx_asxx_tx_hi_waterx_cn30xx { 670 u64 reserved_3_63 : 61; 671 u64 mark : 3; 672 } cn30xx; 673 struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx; 674 struct cvmx_asxx_tx_hi_waterx_s cn38xx; 675 struct cvmx_asxx_tx_hi_waterx_s cn38xxp2; 676 struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx; 677 struct cvmx_asxx_tx_hi_waterx_s cn58xx; 678 struct cvmx_asxx_tx_hi_waterx_s cn58xxp1; 679}; 680 681typedef union cvmx_asxx_tx_hi_waterx cvmx_asxx_tx_hi_waterx_t; 682 683/** 684 * cvmx_asx#_tx_prt_en 685 * 686 * ASX_TX_PRT_EN = RGMII Port Enable 687 * 688 */ 689union cvmx_asxx_tx_prt_en { 690 u64 u64; 691 struct cvmx_asxx_tx_prt_en_s { 692 u64 reserved_4_63 : 60; 693 u64 prt_en : 4; 694 } s; 695 struct cvmx_asxx_tx_prt_en_cn30xx { 696 u64 reserved_3_63 : 61; 697 u64 prt_en : 3; 698 } cn30xx; 699 struct cvmx_asxx_tx_prt_en_cn30xx cn31xx; 700 struct cvmx_asxx_tx_prt_en_s cn38xx; 701 struct cvmx_asxx_tx_prt_en_s cn38xxp2; 702 struct cvmx_asxx_tx_prt_en_cn30xx cn50xx; 703 struct cvmx_asxx_tx_prt_en_s cn58xx; 704 struct cvmx_asxx_tx_prt_en_s cn58xxp1; 705}; 706 707typedef union cvmx_asxx_tx_prt_en cvmx_asxx_tx_prt_en_t; 708 709#endif 710