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7#include <common.h>
8#include <command.h>
9#include <cpu_func.h>
10#include <asm/cache.h>
11#include <asm/io.h>
12#include <asm/processor.h>
13#include <asm/system.h>
14
15#define CACHE_VALID 1
16#define CACHE_UPDATED 2
17
18static inline void cache_wback_all(void)
19{
20 unsigned long addr, data, i, j;
21
22 for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) {
23 for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
24 addr = CACHE_OC_ADDRESS_ARRAY
25 | (j << CACHE_OC_WAY_SHIFT)
26 | (i << CACHE_OC_ENTRY_SHIFT);
27 data = inl(addr);
28 if (data & CACHE_UPDATED) {
29 data &= ~CACHE_UPDATED;
30 outl(data, addr);
31 }
32 }
33 }
34}
35
36#define CACHE_ENABLE 0
37#define CACHE_DISABLE 1
38
39static int cache_control(unsigned int cmd)
40{
41 unsigned long ccr;
42
43 jump_to_P2();
44 ccr = inl(CCR);
45
46 if (ccr & CCR_CACHE_ENABLE)
47 cache_wback_all();
48
49 if (cmd == CACHE_DISABLE)
50 outl(CCR_CACHE_STOP, CCR);
51 else
52 outl(CCR_CACHE_INIT, CCR);
53 back_to_P1();
54
55 return 0;
56}
57
58void flush_dcache_range(unsigned long start, unsigned long end)
59{
60 u32 v;
61
62 start &= ~(L1_CACHE_BYTES - 1);
63 for (v = start; v < end; v += L1_CACHE_BYTES) {
64 asm volatile ("ocbp %0" :
65 : "m" (__m(v)));
66 }
67}
68
69void invalidate_dcache_range(unsigned long start, unsigned long end)
70{
71 u32 v;
72
73 start &= ~(L1_CACHE_BYTES - 1);
74 for (v = start; v < end; v += L1_CACHE_BYTES) {
75 asm volatile ("ocbi %0" :
76 : "m" (__m(v)));
77 }
78}
79
80void flush_cache(unsigned long addr, unsigned long size)
81{
82 flush_dcache_range(addr , addr + size);
83}
84
85void icache_enable(void)
86{
87 cache_control(CACHE_ENABLE);
88}
89
90void icache_disable(void)
91{
92 cache_control(CACHE_DISABLE);
93}
94
95int icache_status(void)
96{
97 return 0;
98}
99
100void dcache_enable(void)
101{
102}
103
104void dcache_disable(void)
105{
106}
107
108int dcache_status(void)
109{
110 return 0;
111}
112
