LXR uboot/board/atmel/sama5d2_ptc_ek/sama5d2_ptc

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2017 Microchip Corporation
   4 *                    Wenyou Yang <wenyou.yang@microchip.com>
   5 */
   6
   7#include <common.h>
   8#include <debug_uart.h>
   9#include <dm.h>
  10#include <i2c.h>
  11#include <init.h>
  12#include <nand.h>
  13#include <version.h>
  14#include <asm/global_data.h>
  15#include <asm/io.h>
  16#include <asm/arch/at91_common.h>
  17#include <asm/arch/atmel_pio4.h>
  18#include <asm/arch/atmel_mpddrc.h>
  19#include <asm/arch/atmel_sdhci.h>
  20#include <asm/arch/clk.h>
  21#include <asm/arch/gpio.h>
  22#include <asm/arch/sama5d2.h>
  23#include <asm/arch/sama5d2_smc.h>
  24
  25extern void at91_pda_detect(void);
  26
  27DECLARE_GLOBAL_DATA_PTR;
  28
  29#ifdef CONFIG_NAND_ATMEL
  30static void board_nand_hw_init(void)
  31{
  32        struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  33
  34        at91_periph_clk_enable(ATMEL_ID_HSMC);
  35
  36        /* Configure SMC CS3 for NAND */
  37        writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  38               AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
  39               &smc->cs[3].setup);
  40        writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(4) |
  41               AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
  42               &smc->cs[3].pulse);
  43        writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(5),
  44               &smc->cs[3].cycle);
  45        writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
  46               AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
  47               AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3) |
  48               AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  49        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  50               AT91_SMC_MODE_EXNW_DISABLE |
  51               AT91_SMC_MODE_DBW_8 |
  52               AT91_SMC_MODE_TDF_CYCLE(3),
  53               &smc->cs[3].mode);
  54
  55        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 22, ATMEL_PIO_DRVSTR_ME);       /* D0 */
  56        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 23, ATMEL_PIO_DRVSTR_ME);       /* D1 */
  57        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 24, ATMEL_PIO_DRVSTR_ME);       /* D2 */
  58        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 25, ATMEL_PIO_DRVSTR_ME);       /* D3 */
  59        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 26, ATMEL_PIO_DRVSTR_ME);       /* D4 */
  60        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 27, ATMEL_PIO_DRVSTR_ME);       /* D5 */
  61        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 28, ATMEL_PIO_DRVSTR_ME);       /* D6 */
  62        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 29, ATMEL_PIO_DRVSTR_ME);       /* D7 */
  63        atmel_pio4_set_b_periph(AT91_PIO_PORTB, 2, 0);  /* RE */
  64        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 30, 0); /* WE */
  65        atmel_pio4_set_b_periph(AT91_PIO_PORTA, 31, ATMEL_PIO_PUEN_MASK);       /* NCS */
  66        atmel_pio4_set_b_periph(AT91_PIO_PORTC, 8, ATMEL_PIO_PUEN_MASK);        /* RDY */
  67        atmel_pio4_set_b_periph(AT91_PIO_PORTB, 0, ATMEL_PIO_PUEN_MASK);        /* ALE */
  68        atmel_pio4_set_b_periph(AT91_PIO_PORTB, 1, ATMEL_PIO_PUEN_MASK);        /* CLE */
  69}
  70#endif
  71
  72#ifdef CONFIG_BOARD_LATE_INIT
  73int board_late_init(void)
  74{
  75        at91_pda_detect();
  76        return 0;
  77}
  78#endif
  79
  80#ifdef CONFIG_CMD_USB
  81static void board_usb_hw_init(void)
  82{
  83        atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, ATMEL_PIO_PUEN_MASK);
  84}
  85#endif
  86
  87#ifdef CONFIG_DEBUG_UART_BOARD_INIT
  88static void board_uart0_hw_init(void)
  89{
  90        atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK);       /* URXD0 */
  91        atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
  92
  93        at91_periph_clk_enable(ATMEL_ID_UART0);
  94}
  95
  96void board_debug_uart_init(void)
  97{
  98        board_uart0_hw_init();
  99}
 100#endif
 101
 102#ifdef CONFIG_BOARD_EARLY_INIT_F
 103int board_early_init_f(void)
 104{
 105#ifdef CONFIG_DEBUG_UART
 106        debug_uart_init();
 107#endif
 108        return 0;
 109}
 110#endif
 111
 112int board_init(void)
 113{
 114        /* address of boot parameters */
 115        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 116
 117#ifdef CONFIG_NAND_ATMEL
 118        board_nand_hw_init();
 119#endif
 120#ifdef CONFIG_CMD_USB
 121        board_usb_hw_init();
 122#endif
 123        return 0;
 124}
 125
 126int dram_init(void)
 127{
 128        gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 129                                    CONFIG_SYS_SDRAM_SIZE);
 130        return 0;
 131}
 132
 133#define AT24MAC_MAC_OFFSET      0xfa
 134
 135#ifdef CONFIG_MISC_INIT_R
 136int misc_init_r(void)
 137{
 138#ifdef CONFIG_I2C_EEPROM
 139        at91_set_ethaddr(AT24MAC_MAC_OFFSET);
 140#endif
 141        return 0;
 142}
 143#endif
 144