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7#include <common.h>
8#include <init.h>
9#include <asm/global_data.h>
10#include <asm/io.h>
11#include <asm/arch/at91_common.h>
12#include <asm/arch/at91_rstc.h>
13#include <asm/arch/atmel_mpddrc.h>
14#include <asm/arch/gpio.h>
15#include <asm/arch/clk.h>
16#include <asm/arch/sama5d3_smc.h>
17#include <asm/arch/sama5d4.h>
18#include <debug_uart.h>
19
20DECLARE_GLOBAL_DATA_PTR;
21
22extern void at91_pda_detect(void);
23
24#ifdef CONFIG_NAND_ATMEL
25static void sama5d4_xplained_nand_hw_init(void)
26{
27 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
28
29 at91_periph_clk_enable(ATMEL_ID_SMC);
30
31
32 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
33 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
34 &smc->cs[3].setup);
35 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
36 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
37 &smc->cs[3].pulse);
38 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
39 &smc->cs[3].cycle);
40 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
41 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
42 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)|
43 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
44 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
45 AT91_SMC_MODE_EXNW_DISABLE |
46 AT91_SMC_MODE_DBW_8 |
47 AT91_SMC_MODE_TDF_CYCLE(3),
48 &smc->cs[3].mode);
49
50 at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0);
51 at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0);
52 at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0);
53 at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0);
54 at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0);
55 at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0);
56 at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0);
57 at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0);
58 at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0);
59 at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0);
60 at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1);
61 at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1);
62 at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1);
63 at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1);
64}
65#endif
66
67#ifdef CONFIG_CMD_USB
68static void sama5d4_xplained_usb_hw_init(void)
69{
70 at91_set_pio_output(AT91_PIO_PORTE, 11, 1);
71 at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
72}
73#endif
74
75#ifdef CONFIG_BOARD_LATE_INIT
76int board_late_init(void)
77{
78 at91_pda_detect();
79#ifdef CONFIG_DM_VIDEO
80 at91_video_show_board_info();
81#endif
82 return 0;
83}
84#endif
85
86#ifdef CONFIG_DEBUG_UART_BOARD_INIT
87static void sama5d4_xplained_serial3_hw_init(void)
88{
89 at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1);
90 at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0);
91
92
93 at91_periph_clk_enable(ATMEL_ID_USART3);
94}
95
96void board_debug_uart_init(void)
97{
98 sama5d4_xplained_serial3_hw_init();
99}
100#endif
101
102#ifdef CONFIG_BOARD_EARLY_INIT_F
103int board_early_init_f(void)
104{
105#ifdef CONFIG_DEBUG_UART
106 debug_uart_init();
107#endif
108 return 0;
109}
110#endif
111
112#define AT24MAC_MAC_OFFSET 0x9a
113
114#ifdef CONFIG_MISC_INIT_R
115int misc_init_r(void)
116{
117#ifdef CONFIG_I2C_EEPROM
118 at91_set_ethaddr(AT24MAC_MAC_OFFSET);
119#endif
120 return 0;
121}
122#endif
123
124int board_init(void)
125{
126
127 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
128
129#ifdef CONFIG_NAND_ATMEL
130 sama5d4_xplained_nand_hw_init();
131#endif
132#ifdef CONFIG_CMD_USB
133 sama5d4_xplained_usb_hw_init();
134#endif
135
136 return 0;
137}
138
139int dram_init(void)
140{
141 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
142 CONFIG_SYS_SDRAM_SIZE);
143 return 0;
144}
145
146
147#ifdef CONFIG_SPL_BUILD
148void spl_board_init(void)
149{
150#if CONFIG_NAND_BOOT
151 sama5d4_xplained_nand_hw_init();
152#endif
153}
154
155static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
156{
157 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
158
159 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
160 ATMEL_MPDDRC_CR_NR_ROW_14 |
161 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
162 ATMEL_MPDDRC_CR_NB_8BANKS |
163 ATMEL_MPDDRC_CR_NDQS_DISABLED |
164 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
165 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
166
167 ddr2->rtr = 0x2b0;
168
169 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
170 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
171 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
172 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
173 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
174 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
175 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
176 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
177
178 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
179 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
180 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
181 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
182
183 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
184 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
185 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
186 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
187 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
188}
189
190void mem_init(void)
191{
192 struct atmel_mpddrc_config ddr2;
193
194 ddr2_conf(&ddr2);
195
196
197 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
198 at91_system_clk_enable(AT91_PMC_DDR);
199
200
201 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
202}
203
204void at91_pmc_init(void)
205{
206 u32 tmp;
207
208 tmp = AT91_PMC_PLLAR_29 |
209 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
210 AT91_PMC_PLLXR_MUL(87) |
211 AT91_PMC_PLLXR_DIV(1);
212 at91_plla_init(tmp);
213
214 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
215
216 tmp = AT91_PMC_MCKR_H32MXDIV |
217 AT91_PMC_MCKR_PLLADIV_2 |
218 AT91_PMC_MCKR_MDIV_3 |
219 AT91_PMC_MCKR_CSS_PLLA;
220 at91_mck_init(tmp);
221}
222#endif
223
