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7#include <common.h>
8#include <command.h>
9#include <env.h>
10#include <fdt_support.h>
11#include <i2c.h>
12#include <image.h>
13#include <init.h>
14#include <netdev.h>
15#include <asm/global_data.h>
16#include <linux/compiler.h>
17#include <asm/mmu.h>
18#include <asm/processor.h>
19#include <asm/immap_85xx.h>
20#include <asm/fsl_law.h>
21#include <asm/fsl_serdes.h>
22#include <asm/fsl_liodn.h>
23#include <fm_eth.h>
24#include "t102xrdb.h"
25#ifdef CONFIG_TARGET_T1024RDB
26#include "cpld.h"
27#elif defined(CONFIG_TARGET_T1023RDB)
28#include <i2c.h>
29#include <mmc.h>
30#endif
31#include "../common/sleep.h"
32
33DECLARE_GLOBAL_DATA_PTR;
34
35#ifdef CONFIG_TARGET_T1023RDB
36enum {
37 GPIO1_SD_SEL = 0x00020000,
38 GPIO1_EMMC_SEL,
39 GPIO3_GET_VERSION,
40 GPIO3_BRD_VER_MASK = 0x0c000000,
41 GPIO3_OFFSET = 0x2000,
42 I2C_GET_BANK,
43 I2C_SET_BANK0,
44 I2C_SET_BANK4,
45};
46#endif
47
48int checkboard(void)
49{
50 struct cpu_type *cpu = gd->arch.cpu;
51 static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
52 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
53 u32 srds_s1;
54
55 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
56 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
57
58 printf("Board: %sRDB, ", cpu->name);
59#if defined(CONFIG_TARGET_T1024RDB)
60 printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
61 CPLD_READ(hw_ver), CPLD_READ(sw_ver));
62#elif defined(CONFIG_TARGET_T1023RDB)
63 printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
64#endif
65 printf("boot from ");
66
67#ifdef CONFIG_SDCARD
68 puts("SD/MMC\n");
69#elif CONFIG_SPIFLASH
70 puts("SPI\n");
71#elif defined(CONFIG_TARGET_T1024RDB)
72 u8 reg;
73
74 reg = CPLD_READ(flash_csr);
75
76 if (reg & CPLD_BOOT_SEL) {
77 puts("NAND\n");
78 } else {
79 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
80 printf("NOR vBank%d\n", reg);
81 }
82#elif defined(CONFIG_TARGET_T1023RDB)
83#ifdef CONFIG_MTD_RAW_NAND
84 puts("NAND\n");
85#else
86 printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
87#endif
88#endif
89
90 puts("SERDES Reference Clocks:\n");
91 if (srds_s1 == 0x95)
92 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
93 else
94 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
95
96 return 0;
97}
98
99#ifdef CONFIG_TARGET_T1024RDB
100static void board_mux_lane(void)
101{
102 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
103 u32 srds_prtcl_s1;
104 u8 reg = CPLD_READ(misc_ctl_status);
105
106 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
107 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
108 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
109
110 if (srds_prtcl_s1 == 0x95) {
111
112 CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
113 } else {
114
115 CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
116 }
117 CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
118}
119#endif
120
121int board_early_init_f(void)
122{
123#if defined(CONFIG_DEEP_SLEEP)
124 if (is_warm_boot())
125 fsl_dp_disable_console();
126#endif
127
128 return 0;
129}
130
131int board_early_init_r(void)
132{
133#ifdef CONFIG_SYS_FLASH_BASE
134 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
135 int flash_esel = find_tlb_idx((void *)flashbase, 1);
136
137
138
139
140
141
142 flush_dcache();
143 invalidate_icache();
144 if (flash_esel == -1) {
145
146 puts("Error: Could not find TLB for FLASH BASE\n");
147 flash_esel = 2;
148 } else {
149
150 disable_tlb(flash_esel);
151 }
152
153 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
154 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
155 0, flash_esel, BOOKE_PAGESZ_256M, 1);
156#endif
157
158#ifdef CONFIG_TARGET_T1024RDB
159 board_mux_lane();
160#endif
161
162 return 0;
163}
164
165unsigned long get_board_sys_clk(void)
166{
167 return CONFIG_SYS_CLK_FREQ;
168}
169
170unsigned long get_board_ddr_clk(void)
171{
172 return CONFIG_DDR_CLK_FREQ;
173}
174
175#ifdef CONFIG_TARGET_T1024RDB
176void board_reset(void)
177{
178 CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
179}
180#endif
181
182int misc_init_r(void)
183{
184 return 0;
185}
186
187int ft_board_setup(void *blob, struct bd_info *bd)
188{
189 phys_addr_t base;
190 phys_size_t size;
191
192 ft_cpu_setup(blob, bd);
193
194 base = env_get_bootm_low();
195 size = env_get_bootm_size();
196
197 fdt_fixup_memory(blob, (u64)base, (u64)size);
198
199#ifdef CONFIG_PCI
200 pci_of_setup(blob, bd);
201#endif
202
203 fdt_fixup_liodn(blob);
204 fsl_fdt_fixup_dr_usb(blob, bd);
205
206#ifdef CONFIG_SYS_DPAA_FMAN
207#ifndef CONFIG_DM_ETH
208 fdt_fixup_fman_ethernet(blob);
209#endif
210 fdt_fixup_board_enet(blob);
211#endif
212
213#ifdef CONFIG_TARGET_T1023RDB
214 if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
215 fdt_enable_nor(blob);
216#endif
217
218 return 0;
219}
220
221#ifdef CONFIG_TARGET_T1023RDB
222
223static void fdt_enable_nor(void *blob)
224{
225 int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
226
227 if (nodeoff >= 0)
228 fdt_status_okay(blob, nodeoff);
229 else
230 printf("WARNING unable to set status for NOR\n");
231}
232
233int board_mmc_getcd(struct mmc *mmc)
234{
235 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
236 u32 val = in_be32(&pgpio->gpdat);
237
238
239 val &= GPIO1_SD_SEL;
240
241 return val ? -1 : 1;
242}
243
244int board_mmc_getwp(struct mmc *mmc)
245{
246 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
247 u32 val = in_be32(&pgpio->gpdat);
248
249 val &= GPIO1_SD_SEL;
250
251 return val ? -1 : 0;
252}
253
254static u32 t1023rdb_ctrl(u32 ctrl_type)
255{
256 ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
257 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
258 u32 val;
259 u8 tmp;
260 int bus_num = I2C_PCA6408_BUS_NUM;
261
262#if CONFIG_IS_ENABLED(DM_I2C)
263 struct udevice *dev;
264 int ret;
265
266 ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA6408_ADDR,
267 1, &dev);
268 if (ret) {
269 printf("%s: Cannot find udev for a bus %d\n", __func__,
270 bus_num);
271 return ret;
272 }
273 switch (ctrl_type) {
274 case GPIO1_SD_SEL:
275 val = in_be32(&pgpio->gpdat);
276 val |= GPIO1_SD_SEL;
277 out_be32(&pgpio->gpdat, val);
278 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
279 break;
280 case GPIO1_EMMC_SEL:
281 val = in_be32(&pgpio->gpdat);
282 val &= ~GPIO1_SD_SEL;
283 out_be32(&pgpio->gpdat, val);
284 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
285 break;
286 case GPIO3_GET_VERSION:
287 pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
288 + GPIO3_OFFSET);
289 val = in_be32(&pgpio->gpdat);
290 val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
291 if (val == 0x3)
292 val = 0;
293 return val;
294 case I2C_GET_BANK:
295 dm_i2c_read(dev, 0, &tmp, 1);
296 tmp &= 0x7;
297 tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
298 return tmp;
299 case I2C_SET_BANK0:
300 tmp = 0x0;
301 dm_i2c_write(dev, 1, &tmp, 1);
302 tmp = 0xf8;
303 dm_i2c_write(dev, 3, &tmp, 1);
304
305 out_be32(&gur->rstcr, 0x2);
306 break;
307 case I2C_SET_BANK4:
308 tmp = 0x1;
309 dm_i2c_write(dev, 1, &tmp, 1);
310 tmp = 0xf8;
311 dm_i2c_write(dev, 3, &tmp, 1);
312 out_be32(&gur->rstcr, 0x2);
313 break;
314 default:
315 break;
316 }
317#else
318 u32 orig_bus;
319
320 orig_bus = i2c_get_bus_num();
321
322 switch (ctrl_type) {
323 case GPIO1_SD_SEL:
324 val = in_be32(&pgpio->gpdat);
325 val |= GPIO1_SD_SEL;
326 out_be32(&pgpio->gpdat, val);
327 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
328 break;
329 case GPIO1_EMMC_SEL:
330 val = in_be32(&pgpio->gpdat);
331 val &= ~GPIO1_SD_SEL;
332 out_be32(&pgpio->gpdat, val);
333 setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
334 break;
335 case GPIO3_GET_VERSION:
336 pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
337 + GPIO3_OFFSET);
338 val = in_be32(&pgpio->gpdat);
339 val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
340 if (val == 0x3)
341 val = 0;
342 return val;
343 case I2C_GET_BANK:
344 i2c_set_bus_num(bus_num);
345 i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
346 tmp &= 0x7;
347 tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
348 i2c_set_bus_num(orig_bus);
349 return tmp;
350 case I2C_SET_BANK0:
351 i2c_set_bus_num(bus_num);
352 tmp = 0x0;
353 i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
354 tmp = 0xf8;
355 i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
356
357 out_be32(&gur->rstcr, 0x2);
358 break;
359 case I2C_SET_BANK4:
360 i2c_set_bus_num(bus_num);
361 tmp = 0x1;
362 i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
363 tmp = 0xf8;
364 i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
365 out_be32(&gur->rstcr, 0x2);
366 break;
367 default:
368 break;
369 }
370#endif
371 return 0;
372}
373
374static int switch_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
375 char *const argv[])
376{
377 if (argc < 2)
378 return CMD_RET_USAGE;
379 if (!strcmp(argv[1], "bank0"))
380 t1023rdb_ctrl(I2C_SET_BANK0);
381 else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
382 t1023rdb_ctrl(I2C_SET_BANK4);
383 else if (!strcmp(argv[1], "sd"))
384 t1023rdb_ctrl(GPIO1_SD_SEL);
385 else if (!strcmp(argv[1], "emmc"))
386 t1023rdb_ctrl(GPIO1_EMMC_SEL);
387 else
388 return CMD_RET_USAGE;
389 return 0;
390}
391
392U_BOOT_CMD(
393 switch, 2, 0, switch_cmd,
394 "for bank0/bank4/sd/emmc switch control in runtime",
395 "command (e.g. switch bank4)"
396);
397#endif
398
