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6
7#include <common.h>
8#include <command.h>
9#include <cpu_func.h>
10#include <debug_uart.h>
11#include <dfu.h>
12#include <env.h>
13#include <env_internal.h>
14#include <init.h>
15#include <image.h>
16#include <lmb.h>
17#include <log.h>
18#include <net.h>
19#include <sata.h>
20#include <ahci.h>
21#include <scsi.h>
22#include <malloc.h>
23#include <memalign.h>
24#include <wdt.h>
25#include <asm/arch/clk.h>
26#include <asm/arch/hardware.h>
27#include <asm/arch/sys_proto.h>
28#include <asm/arch/psu_init_gpl.h>
29#include <asm/cache.h>
30#include <asm/global_data.h>
31#include <asm/io.h>
32#include <asm/ptrace.h>
33#include <dm/device.h>
34#include <dm/uclass.h>
35#include <usb.h>
36#include <dwc3-uboot.h>
37#include <zynqmppl.h>
38#include <zynqmp_firmware.h>
39#include <g_dnl.h>
40#include <linux/bitops.h>
41#include <linux/delay.h>
42#include <linux/sizes.h>
43#include "../common/board.h"
44
45#include "pm_cfg_obj.h"
46
47#define ZYNQMP_VERSION_SIZE 7
48#define EFUSE_VCU_DIS_MASK 0x100
49#define EFUSE_VCU_DIS_SHIFT 8
50#define EFUSE_GPU_DIS_MASK 0x20
51#define EFUSE_GPU_DIS_SHIFT 5
52#define IDCODE2_PL_INIT_MASK 0x200
53#define IDCODE2_PL_INIT_SHIFT 9
54
55DECLARE_GLOBAL_DATA_PTR;
56
57#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
58static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
59
60enum {
61 ZYNQMP_VARIANT_EG = BIT(0U),
62 ZYNQMP_VARIANT_EV = BIT(1U),
63 ZYNQMP_VARIANT_CG = BIT(2U),
64 ZYNQMP_VARIANT_DR = BIT(3U),
65};
66
67static const struct {
68 u32 id;
69 u8 device;
70 u8 variants;
71} zynqmp_devices[] = {
72 {
73 .id = 0x04711093,
74 .device = 2,
75 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
76 },
77 {
78 .id = 0x04710093,
79 .device = 3,
80 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
81 },
82 {
83 .id = 0x04721093,
84 .device = 4,
85 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
86 ZYNQMP_VARIANT_EV,
87 },
88 {
89 .id = 0x04720093,
90 .device = 5,
91 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
92 ZYNQMP_VARIANT_EV,
93 },
94 {
95 .id = 0x04739093,
96 .device = 6,
97 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
98 },
99 {
100 .id = 0x04730093,
101 .device = 7,
102 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
103 ZYNQMP_VARIANT_EV,
104 },
105 {
106 .id = 0x04738093,
107 .device = 9,
108 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
109 },
110 {
111 .id = 0x04740093,
112 .device = 11,
113 .variants = ZYNQMP_VARIANT_EG,
114 },
115 {
116 .id = 0x04750093,
117 .device = 15,
118 .variants = ZYNQMP_VARIANT_EG,
119 },
120 {
121 .id = 0x04759093,
122 .device = 17,
123 .variants = ZYNQMP_VARIANT_EG,
124 },
125 {
126 .id = 0x04758093,
127 .device = 19,
128 .variants = ZYNQMP_VARIANT_EG,
129 },
130 {
131 .id = 0x047E1093,
132 .device = 21,
133 .variants = ZYNQMP_VARIANT_DR,
134 },
135 {
136 .id = 0x047E3093,
137 .device = 23,
138 .variants = ZYNQMP_VARIANT_DR,
139 },
140 {
141 .id = 0x047E5093,
142 .device = 25,
143 .variants = ZYNQMP_VARIANT_DR,
144 },
145 {
146 .id = 0x047E4093,
147 .device = 27,
148 .variants = ZYNQMP_VARIANT_DR,
149 },
150 {
151 .id = 0x047E0093,
152 .device = 28,
153 .variants = ZYNQMP_VARIANT_DR,
154 },
155 {
156 .id = 0x047E2093,
157 .device = 29,
158 .variants = ZYNQMP_VARIANT_DR,
159 },
160 {
161 .id = 0x047E6093,
162 .device = 39,
163 .variants = ZYNQMP_VARIANT_DR,
164 },
165 {
166 .id = 0x047FD093,
167 .device = 43,
168 .variants = ZYNQMP_VARIANT_DR,
169 },
170 {
171 .id = 0x047F8093,
172 .device = 46,
173 .variants = ZYNQMP_VARIANT_DR,
174 },
175 {
176 .id = 0x047FF093,
177 .device = 47,
178 .variants = ZYNQMP_VARIANT_DR,
179 },
180 {
181 .id = 0x047FB093,
182 .device = 48,
183 .variants = ZYNQMP_VARIANT_DR,
184 },
185 {
186 .id = 0x047FE093,
187 .device = 49,
188 .variants = ZYNQMP_VARIANT_DR,
189 },
190 {
191 .id = 0x046d0093,
192 .device = 67,
193 .variants = ZYNQMP_VARIANT_DR,
194 },
195};
196
197static const struct {
198 u32 id;
199 char *name;
200} zynqmp_svd_devices[] = {
201 {
202 .id = 0x04714093,
203 .name = "xck24"
204 },
205 {
206 .id = 0x04724093,
207 .name = "xck26",
208 },
209};
210
211static char *zynqmp_detect_svd_name(u32 idcode)
212{
213 u32 i;
214
215 for (i = 0; i < ARRAY_SIZE(zynqmp_svd_devices); i++) {
216 if (zynqmp_svd_devices[i].id == (idcode & 0x0FFFFFFF))
217 return zynqmp_svd_devices[i].name;
218 }
219
220 return "unknown";
221}
222
223static char *zynqmp_get_silicon_idcode_name(void)
224{
225 u32 i;
226 u32 idcode, idcode2;
227 char name[ZYNQMP_VERSION_SIZE];
228 u32 ret_payload[PAYLOAD_ARG_CNT];
229 int ret;
230
231 ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
232 if (ret) {
233 debug("%s: Getting chipid failed\n", __func__);
234 return "unknown";
235 }
236
237
238
239
240
241
242
243
244
245
246 idcode = ret_payload[1];
247 idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
248 debug("%s, IDCODE: 0x%0x, IDCODE2: 0x%0x\r\n", __func__, idcode,
249 idcode2);
250
251 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
252 if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF))
253 break;
254 }
255
256 if (i >= ARRAY_SIZE(zynqmp_devices))
257 return zynqmp_detect_svd_name(idcode);
258
259
260 ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d",
261 zynqmp_devices[i].device);
262 if (ret < 0)
263 return "unknown";
264
265 if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
266
267 if (idcode2 & IDCODE2_PL_INIT_MASK) {
268 u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
269 EFUSE_VCU_DIS_SHIFT) << 1 |
270 ((idcode2 & EFUSE_GPU_DIS_MASK) >>
271 EFUSE_GPU_DIS_SHIFT);
272
273
274
275
276
277
278 switch (family) {
279 case 0x00:
280 strncat(name, "ev", 2);
281 break;
282 case 0x10:
283 strncat(name, "eg", 2);
284 break;
285 case 0x11:
286 strncat(name, "cg", 2);
287 break;
288 default:
289
290 break;
291 }
292 } else {
293
294
295
296
297
298 strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" :
299 "e", 2);
300 }
301 } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) {
302
303 strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2);
304 } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) {
305 strncat(name, "eg", 2);
306 } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) {
307 strncat(name, "dr", 2);
308 } else {
309 debug("Variant not identified\n");
310 }
311
312 return strdup(name);
313}
314#endif
315
316int board_early_init_f(void)
317{
318#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
319 int ret;
320
321 ret = psu_init();
322 if (ret)
323 return ret;
324
325
326
327
328
329
330
331
332
333 writel(ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL,
334 ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS);
335
336
337 udelay(1000000);
338#endif
339
340#ifdef CONFIG_DEBUG_UART
341
342 debug_uart_init();
343 puts("Debug uart enabled\n");
344#endif
345
346 return 0;
347}
348
349static int multi_boot(void)
350{
351 u32 multiboot = 0;
352 int ret;
353
354 ret = zynqmp_mmio_read((ulong)&csu_base->multi_boot, &multiboot);
355 if (ret)
356 return -EINVAL;
357
358 return multiboot;
359}
360
361#define PS_SYSMON_ANALOG_BUS_VAL 0x3210
362#define PS_SYSMON_ANALOG_BUS_REG 0xFFA50914
363
364int board_init(void)
365{
366#if defined(CONFIG_ZYNQMP_FIRMWARE)
367 struct udevice *dev;
368
369 uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
370 if (!dev)
371 panic("PMU Firmware device not found - Enable it");
372#endif
373
374#if defined(CONFIG_SPL_BUILD)
375
376 if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
377 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
378 zynqmp_pm_cfg_obj_size);
379 printf("Silicon version:\t%d\n", zynqmp_get_silicon_version());
380#else
381 if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
382 xilinx_read_eeprom();
383#endif
384
385 printf("EL Level:\tEL%d\n", current_el());
386
387
388 writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
389
390#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
391 zynqmppl.name = zynqmp_get_silicon_idcode_name();
392 printf("Chip ID:\t%s\n", zynqmppl.name);
393 fpga_init();
394 fpga_add(fpga_xilinx, &zynqmppl);
395#endif
396
397 if (current_el() == 3)
398 printf("Multiboot:\t%d\n", multi_boot());
399
400 return 0;
401}
402
403int board_early_init_r(void)
404{
405 u32 val;
406
407 if (current_el() != 3)
408 return 0;
409
410 val = readl(&crlapb_base->timestamp_ref_ctrl);
411 val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
412
413 if (!val) {
414 val = readl(&crlapb_base->timestamp_ref_ctrl);
415 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
416 writel(val, &crlapb_base->timestamp_ref_ctrl);
417
418
419 writel(zynqmp_get_system_timer_freq(),
420 &iou_scntr_secure->base_frequency_id_register);
421
422 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
423 &iou_scntr_secure->counter_control_register);
424 }
425 return 0;
426}
427
428unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
429 char *const argv[])
430{
431 int ret = 0;
432
433 if (current_el() > 1) {
434 smp_kick_all_cpus();
435 dcache_disable();
436 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
437 ES_TO_AARCH64);
438 } else {
439 printf("FAIL: current EL is not above EL1\n");
440 ret = EINVAL;
441 }
442 return ret;
443}
444
445#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
446int dram_init_banksize(void)
447{
448 int ret;
449
450 ret = fdtdec_setup_memory_banksize();
451 if (ret)
452 return ret;
453
454 mem_map_fill();
455
456 return 0;
457}
458
459int dram_init(void)
460{
461 if (fdtdec_setup_mem_size_base() != 0)
462 return -EINVAL;
463
464 return 0;
465}
466
467ulong board_get_usable_ram_top(ulong total_size)
468{
469 phys_size_t size;
470 phys_addr_t reg;
471 struct lmb lmb;
472
473 if (!IS_ALIGNED((ulong)gd->fdt_blob, 0x8))
474 panic("Not 64bit aligned DT location: %p\n", gd->fdt_blob);
475
476
477 lmb_init(&lmb);
478 lmb_add(&lmb, gd->ram_base, gd->ram_size);
479 boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
480 size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
481 reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
482
483 if (!reg)
484 reg = gd->ram_top - size;
485
486 return reg + size;
487}
488#else
489int dram_init_banksize(void)
490{
491 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
492 gd->bd->bi_dram[0].size = get_effective_memsize();
493
494 mem_map_fill();
495
496 return 0;
497}
498
499int dram_init(void)
500{
501 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
502 CONFIG_SYS_SDRAM_SIZE);
503
504 return 0;
505}
506#endif
507
508#if !CONFIG_IS_ENABLED(SYSRESET)
509void reset_cpu(void)
510{
511}
512#endif
513
514static u8 __maybe_unused zynqmp_get_bootmode(void)
515{
516 u8 bootmode;
517 u32 reg = 0;
518 int ret;
519
520 ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
521 if (ret)
522 return -EINVAL;
523
524 debug("HW boot mode: %x\n", reg & BOOT_MODES_MASK);
525 debug("ALT boot mode: %x\n", reg >> BOOT_MODE_ALT_SHIFT);
526
527 if (reg >> BOOT_MODE_ALT_SHIFT)
528 reg >>= BOOT_MODE_ALT_SHIFT;
529
530 bootmode = reg & BOOT_MODES_MASK;
531
532 return bootmode;
533}
534
535#if defined(CONFIG_BOARD_LATE_INIT)
536static const struct {
537 u32 bit;
538 const char *name;
539} reset_reasons[] = {
540 { RESET_REASON_DEBUG_SYS, "DEBUG" },
541 { RESET_REASON_SOFT, "SOFT" },
542 { RESET_REASON_SRST, "SRST" },
543 { RESET_REASON_PSONLY, "PS-ONLY" },
544 { RESET_REASON_PMU, "PMU" },
545 { RESET_REASON_INTERNAL, "INTERNAL" },
546 { RESET_REASON_EXTERNAL, "EXTERNAL" },
547 {}
548};
549
550static int reset_reason(void)
551{
552 u32 reg;
553 int i, ret;
554 const char *reason = NULL;
555
556 ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, ®);
557 if (ret)
558 return -EINVAL;
559
560 puts("Reset reason:\t");
561
562 for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
563 if (reg & reset_reasons[i].bit) {
564 reason = reset_reasons[i].name;
565 printf("%s ", reset_reasons[i].name);
566 break;
567 }
568 }
569
570 puts("\n");
571
572 env_set("reset_reason", reason);
573
574 return 0;
575}
576
577static int set_fdtfile(void)
578{
579 char *compatible, *fdtfile;
580 const char *suffix = ".dtb";
581 const char *vendor = "xilinx/";
582 int fdt_compat_len;
583
584 if (env_get("fdtfile"))
585 return 0;
586
587 compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible",
588 &fdt_compat_len);
589 if (compatible && fdt_compat_len) {
590 char *name;
591
592 debug("Compatible: %s\n", compatible);
593
594 name = strchr(compatible, ',');
595 if (!name)
596 return -EINVAL;
597
598 name++;
599
600 fdtfile = calloc(1, strlen(vendor) + strlen(name) +
601 strlen(suffix) + 1);
602 if (!fdtfile)
603 return -ENOMEM;
604
605 sprintf(fdtfile, "%s%s%s", vendor, name, suffix);
606
607 env_set("fdtfile", fdtfile);
608 free(fdtfile);
609 }
610
611 return 0;
612}
613
614int board_late_init(void)
615{
616 u8 bootmode;
617 struct udevice *dev;
618 int bootseq = -1;
619 int bootseq_len = 0;
620 int env_targets_len = 0;
621 const char *mode;
622 char *new_targets;
623 char *env_targets;
624 int ret;
625
626#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
627 usb_ether_init();
628#endif
629
630 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
631 debug("Saved variables - Skipping\n");
632 return 0;
633 }
634
635 if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
636 return 0;
637
638 ret = set_fdtfile();
639 if (ret)
640 return ret;
641
642 bootmode = zynqmp_get_bootmode();
643
644 puts("Bootmode: ");
645 switch (bootmode) {
646 case USB_MODE:
647 puts("USB_MODE\n");
648 mode = "usb_dfu0 usb_dfu1";
649 env_set("modeboot", "usb_dfu_spl");
650 break;
651 case JTAG_MODE:
652 puts("JTAG_MODE\n");
653 mode = "jtag pxe dhcp";
654 env_set("modeboot", "jtagboot");
655 break;
656 case QSPI_MODE_24BIT:
657 case QSPI_MODE_32BIT:
658 mode = "qspi0";
659 puts("QSPI_MODE\n");
660 env_set("modeboot", "qspiboot");
661 break;
662 case EMMC_MODE:
663 puts("EMMC_MODE\n");
664 if (uclass_get_device_by_name(UCLASS_MMC,
665 "mmc@ff160000", &dev) &&
666 uclass_get_device_by_name(UCLASS_MMC,
667 "sdhci@ff160000", &dev)) {
668 puts("Boot from EMMC but without SD0 enabled!\n");
669 return -1;
670 }
671 debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
672
673 mode = "mmc";
674 bootseq = dev_seq(dev);
675 break;
676 case SD_MODE:
677 puts("SD_MODE\n");
678 if (uclass_get_device_by_name(UCLASS_MMC,
679 "mmc@ff160000", &dev) &&
680 uclass_get_device_by_name(UCLASS_MMC,
681 "sdhci@ff160000", &dev)) {
682 puts("Boot from SD0 but without SD0 enabled!\n");
683 return -1;
684 }
685 debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
686
687 mode = "mmc";
688 bootseq = dev_seq(dev);
689 env_set("modeboot", "sdboot");
690 break;
691 case SD1_LSHFT_MODE:
692 puts("LVL_SHFT_");
693
694 case SD_MODE1:
695 puts("SD_MODE1\n");
696 if (uclass_get_device_by_name(UCLASS_MMC,
697 "mmc@ff170000", &dev) &&
698 uclass_get_device_by_name(UCLASS_MMC,
699 "sdhci@ff170000", &dev)) {
700 puts("Boot from SD1 but without SD1 enabled!\n");
701 return -1;
702 }
703 debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
704
705 mode = "mmc";
706 bootseq = dev_seq(dev);
707 env_set("modeboot", "sdboot");
708 break;
709 case NAND_MODE:
710 puts("NAND_MODE\n");
711 mode = "nand0";
712 env_set("modeboot", "nandboot");
713 break;
714 default:
715 mode = "";
716 printf("Invalid Boot Mode:0x%x\n", bootmode);
717 break;
718 }
719
720 if (bootseq >= 0) {
721 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
722 debug("Bootseq len: %x\n", bootseq_len);
723 env_set_hex("bootseq", bootseq);
724 }
725
726
727
728
729
730 env_targets = env_get("boot_targets");
731 if (env_targets)
732 env_targets_len = strlen(env_targets);
733
734 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
735 bootseq_len);
736 if (!new_targets)
737 return -ENOMEM;
738
739 if (bootseq >= 0)
740 sprintf(new_targets, "%s%x %s", mode, bootseq,
741 env_targets ? env_targets : "");
742 else
743 sprintf(new_targets, "%s %s", mode,
744 env_targets ? env_targets : "");
745
746 env_set("boot_targets", new_targets);
747 free(new_targets);
748
749 reset_reason();
750
751 return board_late_init_xilinx();
752}
753#endif
754
755int checkboard(void)
756{
757 puts("Board: Xilinx ZynqMP\n");
758 return 0;
759}
760
761int mmc_get_env_dev(void)
762{
763 struct udevice *dev;
764 int bootseq = 0;
765
766 switch (zynqmp_get_bootmode()) {
767 case EMMC_MODE:
768 case SD_MODE:
769 if (uclass_get_device_by_name(UCLASS_MMC,
770 "mmc@ff160000", &dev) &&
771 uclass_get_device_by_name(UCLASS_MMC,
772 "sdhci@ff160000", &dev)) {
773 return -1;
774 }
775 bootseq = dev_seq(dev);
776 break;
777 case SD1_LSHFT_MODE:
778 case SD_MODE1:
779 if (uclass_get_device_by_name(UCLASS_MMC,
780 "mmc@ff170000", &dev) &&
781 uclass_get_device_by_name(UCLASS_MMC,
782 "sdhci@ff170000", &dev)) {
783 return -1;
784 }
785 bootseq = dev_seq(dev);
786 break;
787 default:
788 break;
789 }
790
791 debug("bootseq %d\n", bootseq);
792
793 return bootseq;
794}
795
796enum env_location env_get_location(enum env_operation op, int prio)
797{
798 u32 bootmode = zynqmp_get_bootmode();
799
800 if (prio)
801 return ENVL_UNKNOWN;
802
803 switch (bootmode) {
804 case EMMC_MODE:
805 case SD_MODE:
806 case SD1_LSHFT_MODE:
807 case SD_MODE1:
808 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
809 return ENVL_FAT;
810 if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
811 return ENVL_EXT4;
812 return ENVL_NOWHERE;
813 case NAND_MODE:
814 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
815 return ENVL_NAND;
816 if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
817 return ENVL_UBI;
818 return ENVL_NOWHERE;
819 case QSPI_MODE_24BIT:
820 case QSPI_MODE_32BIT:
821 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
822 return ENVL_SPI_FLASH;
823 return ENVL_NOWHERE;
824 case JTAG_MODE:
825 default:
826 return ENVL_NOWHERE;
827 }
828}
829
830#if defined(CONFIG_SET_DFU_ALT_INFO)
831
832#define DFU_ALT_BUF_LEN SZ_1K
833
834void set_dfu_alt_info(char *interface, char *devstr)
835{
836 u8 multiboot;
837 int bootseq = 0;
838
839 ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
840
841 if (env_get("dfu_alt_info"))
842 return;
843
844 memset(buf, 0, sizeof(buf));
845
846 multiboot = multi_boot();
847 debug("Multiboot: %d\n", multiboot);
848
849 switch (zynqmp_get_bootmode()) {
850 case EMMC_MODE:
851 case SD_MODE:
852 case SD1_LSHFT_MODE:
853 case SD_MODE1:
854 bootseq = mmc_get_env_dev();
855 if (!multiboot)
856 snprintf(buf, DFU_ALT_BUF_LEN,
857 "mmc %d:1=boot.bin fat %d 1;"
858 "u-boot.itb fat %d 1",
859 bootseq, bootseq, bootseq);
860 else
861 snprintf(buf, DFU_ALT_BUF_LEN,
862 "mmc %d:1=boot%04d.bin fat %d 1;"
863 "u-boot.itb fat %d 1",
864 bootseq, multiboot, bootseq, bootseq);
865 break;
866 case QSPI_MODE_24BIT:
867 case QSPI_MODE_32BIT:
868 snprintf(buf, DFU_ALT_BUF_LEN,
869 "sf 0:0=boot.bin raw %x 0x1500000;"
870 "u-boot.itb raw 0x%x 0x500000",
871 multiboot * SZ_32K, CONFIG_SYS_SPI_U_BOOT_OFFS);
872 break;
873 default:
874 return;
875 }
876
877 env_set("dfu_alt_info", buf);
878 puts("DFU alt info setting: done\n");
879}
880#endif
881
