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13#include <common.h>
14#include <clk-uclass.h>
15#include <dm.h>
16#include <linux/bitops.h>
17
18#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
19
20#include "renesas-cpg-mssr.h"
21#include "rcar-gen3-cpg.h"
22
23#define CPG_SD0CKCR 0x0074
24
25enum r8a77970_clk_types {
26 CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE,
27 CLK_TYPE_R8A77970_SD0,
28};
29
30enum clk_ids {
31
32 LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
33
34
35 CLK_EXTAL,
36 CLK_EXTALR,
37
38
39 CLK_MAIN,
40 CLK_PLL0,
41 CLK_PLL1,
42 CLK_PLL3,
43 CLK_PLL1_DIV2,
44 CLK_PLL1_DIV4,
45
46
47 MOD_CLK_BASE
48};
49
50static const struct cpg_core_clk r8a77970_core_clks[] = {
51
52 DEF_INPUT("extal", CLK_EXTAL),
53 DEF_INPUT("extalr", CLK_EXTALR),
54
55
56 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
57 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
58 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
59 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
60
61 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
62 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
63
64
65 DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
66 DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
67 DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
68 DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
69 DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_PLL1_DIV2, 4, 1),
70 DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_PLL1_DIV2, 8, 1),
71 DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_PLL1_DIV2, 16, 1),
72 DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_PLL1_DIV2, 6, 1),
73 DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1),
74 DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1),
75
76 DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H,
77 CLK_PLL1_DIV2),
78 DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
79
80 DEF_FIXED("rpc", R8A77970_CLK_RPC, CLK_PLL1_DIV2, 5, 1),
81 DEF_FIXED("rpcd2", R8A77970_CLK_RPCD2, CLK_PLL1_DIV2, 10, 1),
82
83 DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
84 DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
85 DEF_FIXED("cpex", R8A77970_CLK_CPEX, CLK_EXTAL, 2, 1),
86
87 DEF_DIV6P1("canfd", R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
88 DEF_DIV6P1("mso", R8A77970_CLK_MSO, CLK_PLL1_DIV4, 0x014),
89 DEF_DIV6P1("csi0", R8A77970_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
90
91 DEF_FIXED("osc", R8A77970_CLK_OSC, CLK_PLL1_DIV2, 12*1024, 1),
92 DEF_FIXED("r", R8A77970_CLK_R, CLK_EXTALR, 1, 1),
93};
94
95static const struct mssr_mod_clk r8a77970_mod_clks[] = {
96 DEF_MOD("tmu4", 121, R8A77970_CLK_S2D2),
97 DEF_MOD("tmu3", 122, R8A77970_CLK_S2D2),
98 DEF_MOD("tmu2", 123, R8A77970_CLK_S2D2),
99 DEF_MOD("tmu1", 124, R8A77970_CLK_S2D2),
100 DEF_MOD("tmu0", 125, R8A77970_CLK_CP),
101 DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
102 DEF_MOD("scif4", 203, R8A77970_CLK_S2D4),
103 DEF_MOD("scif3", 204, R8A77970_CLK_S2D4),
104 DEF_MOD("scif1", 206, R8A77970_CLK_S2D4),
105 DEF_MOD("scif0", 207, R8A77970_CLK_S2D4),
106 DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
107 DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
108 DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
109 DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
110 DEF_MOD("mfis", 213, R8A77970_CLK_S2D2),
111 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
112 DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
113 DEF_MOD("cmt3", 300, R8A77970_CLK_R),
114 DEF_MOD("cmt2", 301, R8A77970_CLK_R),
115 DEF_MOD("cmt1", 302, R8A77970_CLK_R),
116 DEF_MOD("cmt0", 303, R8A77970_CLK_R),
117 DEF_MOD("tpu0", 304, R8A77970_CLK_S2D4),
118 DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
119 DEF_MOD("rwdt", 402, R8A77970_CLK_R),
120 DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
121 DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1),
122 DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1),
123 DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1),
124 DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1),
125 DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1),
126 DEF_MOD("thermal", 522, R8A77970_CLK_CP),
127 DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
128 DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
129 DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
130 DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
131 DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
132 DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
133 DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
134 DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
135 DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
136 DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
137 DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
138 DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
139 DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
140 DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
141 DEF_MOD("gpio2", 910, R8A77970_CLK_CP),
142 DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
143 DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
144 DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
145 DEF_MOD("rpc-if", 917, R8A77970_CLK_RPC),
146 DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
147 DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
148 DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
149 DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2),
150 DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
151};
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170#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
171 (((md) & BIT(13)) >> 12) | \
172 (((md) & BIT(19)) >> 19))
173
174static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] = {
175
176 { 1, 192, 1, 96, 1, },
177 { 1, 192, 1, 80, 1, },
178 { 1, 160, 1, 80, 1, },
179 { 1, 160, 1, 66, 1, },
180 { 2, 236, 1, 118, 1, },
181 { 2, 236, 1, 98, 1, },
182 { 2, 192, 1, 96, 1, },
183 { 2, 192, 1, 80, 1, },
184};
185
186static const struct mstp_stop_table r8a77970_mstp_table[] = {
187 { 0x00230000, 0x0, 0x00230000, 0 },
188 { 0x0be00000, 0x0, 0x0be00000, 0 },
189 { 0x04062fd8, 0x2080, 0x04062fd8, 0 },
190 { 0x00c0c0df, 0x0, 0x00c0c0df, 0 },
191 { 0x80000004, 0x180, 0x80000004, 0 },
192 { 0x00de0028, 0x0, 0x00de0028, 0 },
193 { 0x00800008, 0x0, 0x00800008, 0 },
194 { 0x09010000, 0x0, 0x09010000, 0 },
195 { 0x7ff21f00, 0x0, 0x7ff21f00, 0 },
196 { 0xf8025f84, 0x0, 0xf8025f84, 0 },
197 { 0x00000000, 0x0, 0x00000000, 0 },
198 { 0x00000000, 0x0, 0x00000000, 0 },
199};
200
201static const void *r8a77970_get_pll_config(const u32 cpg_mode)
202{
203 return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
204}
205
206static const struct cpg_mssr_info r8a77970_cpg_mssr_info = {
207 .core_clk = r8a77970_core_clks,
208 .core_clk_size = ARRAY_SIZE(r8a77970_core_clks),
209 .mod_clk = r8a77970_mod_clks,
210 .mod_clk_size = ARRAY_SIZE(r8a77970_mod_clks),
211 .mstp_table = r8a77970_mstp_table,
212 .mstp_table_size = ARRAY_SIZE(r8a77970_mstp_table),
213 .reset_node = "renesas,r8a77970-rst",
214 .reset_modemr_offset = CPG_RST_MODEMR,
215 .extalr_node = "extalr",
216 .mod_clk_base = MOD_CLK_BASE,
217 .clk_extal_id = CLK_EXTAL,
218 .clk_extalr_id = CLK_EXTALR,
219 .get_pll_config = r8a77970_get_pll_config,
220};
221
222static const struct udevice_id r8a77970_clk_ids[] = {
223 {
224 .compatible = "renesas,r8a77970-cpg-mssr",
225 .data = (ulong)&r8a77970_cpg_mssr_info
226 },
227 { }
228};
229
230U_BOOT_DRIVER(clk_r8a77970) = {
231 .name = "clk_r8a77970",
232 .id = UCLASS_CLK,
233 .of_match = r8a77970_clk_ids,
234 .priv_auto = sizeof(struct gen3_clk_priv),
235 .ops = &gen3_clk_ops,
236 .probe = gen3_clk_probe,
237 .remove = gen3_clk_remove,
238};
239
