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6#include <common.h>
7#include <log.h>
8#include <asm/arch/clock_manager.h>
9#include <asm/arch/secure_reg_helper.h>
10#include <asm/arch/system_manager.h>
11#include <clk.h>
12#include <dm.h>
13#include <dwmmc.h>
14#include <errno.h>
15#include <fdtdec.h>
16#include <asm/global_data.h>
17#include <dm/device_compat.h>
18#include <linux/intel-smc.h>
19#include <linux/libfdt.h>
20#include <linux/err.h>
21#include <malloc.h>
22#include <reset.h>
23
24DECLARE_GLOBAL_DATA_PTR;
25
26struct socfpga_dwmci_plat {
27 struct mmc_config cfg;
28 struct mmc mmc;
29};
30
31
32struct dwmci_socfpga_priv_data {
33 struct dwmci_host host;
34 unsigned int drvsel;
35 unsigned int smplsel;
36};
37
38static void socfpga_dwmci_reset(struct udevice *dev)
39{
40 struct reset_ctl_bulk reset_bulk;
41 int ret;
42
43 ret = reset_get_bulk(dev, &reset_bulk);
44 if (ret) {
45 dev_warn(dev, "Can't get reset: %d\n", ret);
46 return;
47 }
48
49 reset_deassert_bulk(&reset_bulk);
50}
51
52static int socfpga_dwmci_clksel(struct dwmci_host *host)
53{
54 struct dwmci_socfpga_priv_data *priv = host->priv;
55 u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
56 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
57
58
59 clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
60 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
61
62 debug("%s: drvsel %d smplsel %d\n", __func__,
63 priv->drvsel, priv->smplsel);
64
65#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
66 int ret;
67
68 ret = socfpga_secure_reg_write32(SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC,
69 sdmmc_mask);
70 if (ret) {
71 printf("DWMMC: Failed to set clksel via SMC call");
72 return ret;
73 }
74#else
75 writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
76
77 debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
78 readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
79#endif
80
81
82 setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
83 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
84
85 return 0;
86}
87
88static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
89{
90 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
91 struct dwmci_host *host = &priv->host;
92#if CONFIG_IS_ENABLED(CLK)
93 struct clk clk;
94 int ret;
95
96 ret = clk_get_by_index(dev, 1, &clk);
97 if (ret)
98 return ret;
99
100 host->bus_hz = clk_get_rate(&clk);
101
102 clk_free(&clk);
103#else
104
105 host->bus_hz = cm_get_mmc_controller_clk_hz();
106#endif
107 if (host->bus_hz == 0) {
108 printf("DWMMC: MMC clock is zero!");
109 return -EINVAL;
110 }
111
112 return 0;
113}
114
115static int socfpga_dwmmc_of_to_plat(struct udevice *dev)
116{
117 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
118 struct dwmci_host *host = &priv->host;
119 int fifo_depth;
120
121 fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
122 "fifo-depth", 0);
123 if (fifo_depth < 0) {
124 printf("DWMMC: Can't get FIFO depth\n");
125 return -EINVAL;
126 }
127
128 host->name = dev->name;
129 host->ioaddr = dev_read_addr_ptr(dev);
130 host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
131 "bus-width", 4);
132 host->clksel = socfpga_dwmci_clksel;
133
134
135
136
137
138 host->dev_index = 0;
139 host->fifoth_val = MSIZE(0x2) |
140 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
141 priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
142 "drvsel", 3);
143 priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
144 "smplsel", 0);
145 host->priv = priv;
146
147 host->fifo_mode = dev_read_bool(dev, "fifo-mode");
148
149 return 0;
150}
151
152static int socfpga_dwmmc_probe(struct udevice *dev)
153{
154#ifdef CONFIG_BLK
155 struct socfpga_dwmci_plat *plat = dev_get_plat(dev);
156#endif
157 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
158 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
159 struct dwmci_host *host = &priv->host;
160 int ret;
161
162 ret = socfpga_dwmmc_get_clk_rate(dev);
163 if (ret)
164 return ret;
165
166 socfpga_dwmci_reset(dev);
167
168#ifdef CONFIG_BLK
169 dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
170 host->mmc = &plat->mmc;
171#else
172
173 ret = add_dwmci(host, host->bus_hz, 400000);
174 if (ret)
175 return ret;
176#endif
177 host->mmc->priv = &priv->host;
178 upriv->mmc = host->mmc;
179 host->mmc->dev = dev;
180
181 return dwmci_probe(dev);
182}
183
184static int socfpga_dwmmc_bind(struct udevice *dev)
185{
186#ifdef CONFIG_BLK
187 struct socfpga_dwmci_plat *plat = dev_get_plat(dev);
188 int ret;
189
190 ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
191 if (ret)
192 return ret;
193#endif
194
195 return 0;
196}
197
198static const struct udevice_id socfpga_dwmmc_ids[] = {
199 { .compatible = "altr,socfpga-dw-mshc" },
200 { }
201};
202
203U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
204 .name = "socfpga_dwmmc",
205 .id = UCLASS_MMC,
206 .of_match = socfpga_dwmmc_ids,
207 .of_to_plat = socfpga_dwmmc_of_to_plat,
208 .ops = &dm_dwmci_ops,
209 .bind = socfpga_dwmmc_bind,
210 .probe = socfpga_dwmmc_probe,
211 .priv_auto = sizeof(struct dwmci_socfpga_priv_data),
212 .plat_auto = sizeof(struct socfpga_dwmci_plat),
213};
214
