1/* SPDX-License-Identifier: BSD-3-Clause */ 2/* 3 * Cadence DDR Driver 4 * 5 * Copyright (C) 2012-2021 Cadence Design Systems, Inc. 6 * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ 7 */ 8 9#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ 10#define REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ 11 12#define LPDDR4__DENALI_CTL_0_READ_MASK 0xFFFF0F01U 13#define LPDDR4__DENALI_CTL_0_WRITE_MASK 0xFFFF0F01U 14#define LPDDR4__DENALI_CTL_0__START_MASK 0x00000001U 15#define LPDDR4__DENALI_CTL_0__START_SHIFT 0U 16#define LPDDR4__DENALI_CTL_0__START_WIDTH 1U 17#define LPDDR4__DENALI_CTL_0__START_WOCLR 0U 18#define LPDDR4__DENALI_CTL_0__START_WOSET 0U 19#define LPDDR4__START__REG DENALI_CTL_0 20#define LPDDR4__START__FLD LPDDR4__DENALI_CTL_0__START 21 22#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK 0x00000F00U 23#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_SHIFT 8U 24#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_WIDTH 4U 25#define LPDDR4__DRAM_CLASS__REG DENALI_CTL_0 26#define LPDDR4__DRAM_CLASS__FLD LPDDR4__DENALI_CTL_0__DRAM_CLASS 27 28#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_MASK 0xFFFF0000U 29#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_SHIFT 16U 30#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_WIDTH 16U 31#define LPDDR4__CONTROLLER_ID__REG DENALI_CTL_0 32#define LPDDR4__CONTROLLER_ID__FLD LPDDR4__DENALI_CTL_0__CONTROLLER_ID 33 34#define LPDDR4__DENALI_CTL_1_READ_MASK 0xFFFFFFFFU 35#define LPDDR4__DENALI_CTL_1_WRITE_MASK 0xFFFFFFFFU 36#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_MASK 0xFFFFFFFFU 37#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_SHIFT 0U 38#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_WIDTH 32U 39#define LPDDR4__CONTROLLER_VERSION_0__REG DENALI_CTL_1 40#define LPDDR4__CONTROLLER_VERSION_0__FLD LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0 41 42#define LPDDR4__DENALI_CTL_2_READ_MASK 0xFFFFFFFFU 43#define LPDDR4__DENALI_CTL_2_WRITE_MASK 0xFFFFFFFFU 44#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_MASK 0xFFFFFFFFU 45#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_SHIFT 0U 46#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_WIDTH 32U 47#define LPDDR4__CONTROLLER_VERSION_1__REG DENALI_CTL_2 48#define LPDDR4__CONTROLLER_VERSION_1__FLD LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1 49 50#define LPDDR4__DENALI_CTL_3_READ_MASK 0xFF030F1FU 51#define LPDDR4__DENALI_CTL_3_WRITE_MASK 0xFF030F1FU 52#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_MASK 0x0000001FU 53#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_SHIFT 0U 54#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_WIDTH 5U 55#define LPDDR4__MAX_ROW_REG__REG DENALI_CTL_3 56#define LPDDR4__MAX_ROW_REG__FLD LPDDR4__DENALI_CTL_3__MAX_ROW_REG 57 58#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_MASK 0x00000F00U 59#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_SHIFT 8U 60#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_WIDTH 4U 61#define LPDDR4__MAX_COL_REG__REG DENALI_CTL_3 62#define LPDDR4__MAX_COL_REG__FLD LPDDR4__DENALI_CTL_3__MAX_COL_REG 63 64#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_MASK 0x00030000U 65#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_SHIFT 16U 66#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_WIDTH 2U 67#define LPDDR4__MAX_CS_REG__REG DENALI_CTL_3 68#define LPDDR4__MAX_CS_REG__FLD LPDDR4__DENALI_CTL_3__MAX_CS_REG 69 70#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_MASK 0xFF000000U 71#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_SHIFT 24U 72#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_WIDTH 8U 73#define LPDDR4__READ_DATA_FIFO_DEPTH__REG DENALI_CTL_3 74#define LPDDR4__READ_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH 75 76#define LPDDR4__DENALI_CTL_4_READ_MASK 0x00FFFFFFU 77#define LPDDR4__DENALI_CTL_4_WRITE_MASK 0x00FFFFFFU 78#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_MASK 0x000000FFU 79#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_SHIFT 0U 80#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_WIDTH 8U 81#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4 82#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH 83 84#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_MASK 0x0000FF00U 85#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_SHIFT 8U 86#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_WIDTH 8U 87#define LPDDR4__WRITE_DATA_FIFO_DEPTH__REG DENALI_CTL_4 88#define LPDDR4__WRITE_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH 89 90#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_MASK 0x00FF0000U 91#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_SHIFT 16U 92#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_WIDTH 8U 93#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4 94#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH 95 96#define LPDDR4__DENALI_CTL_5_READ_MASK 0xFFFFFFFFU 97#define LPDDR4__DENALI_CTL_5_WRITE_MASK 0xFFFFFFFFU 98#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_MASK 0x0000FFFFU 99#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_SHIFT 0U 100#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_WIDTH 16U 101#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__REG DENALI_CTL_5 102#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH 103 104#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_MASK 0x00FF0000U 105#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_SHIFT 16U 106#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_WIDTH 8U 107#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__REG DENALI_CTL_5 108#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH 109 110#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_MASK 0xFF000000U 111#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_SHIFT 24U 112#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_WIDTH 8U 113#define LPDDR4__ASYNC_CDC_STAGES__REG DENALI_CTL_5 114#define LPDDR4__ASYNC_CDC_STAGES__FLD LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES 115 116#define LPDDR4__DENALI_CTL_6_READ_MASK 0xFFFFFFFFU 117#define LPDDR4__DENALI_CTL_6_WRITE_MASK 0xFFFFFFFFU 118#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_MASK 0x000000FFU 119#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_SHIFT 0U 120#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_WIDTH 8U 121#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__REG DENALI_CTL_6 122#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH 123 124#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_MASK 0x0000FF00U 125#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_SHIFT 8U 126#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_WIDTH 8U 127#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__REG DENALI_CTL_6 128#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH 129 130#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_MASK 0x00FF0000U 131#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_SHIFT 16U 132#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_WIDTH 8U 133#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__REG DENALI_CTL_6 134#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH 135 136#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_MASK 0xFF000000U 137#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_SHIFT 24U 138#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_WIDTH 8U 139#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__REG DENALI_CTL_6 140#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH 141 142#define LPDDR4__DENALI_CTL_7_READ_MASK 0x00FFFFFFU 143#define LPDDR4__DENALI_CTL_7_WRITE_MASK 0x00FFFFFFU 144#define LPDDR4__DENALI_CTL_7__TINIT_F0_MASK 0x00FFFFFFU 145#define LPDDR4__DENALI_CTL_7__TINIT_F0_SHIFT 0U 146#define LPDDR4__DENALI_CTL_7__TINIT_F0_WIDTH 24U 147#define LPDDR4__TINIT_F0__REG DENALI_CTL_7 148#define LPDDR4__TINIT_F0__FLD LPDDR4__DENALI_CTL_7__TINIT_F0 149 150#define LPDDR4__DENALI_CTL_8_READ_MASK 0x00FFFFFFU 151#define LPDDR4__DENALI_CTL_8_WRITE_MASK 0x00FFFFFFU 152#define LPDDR4__DENALI_CTL_8__TINIT3_F0_MASK 0x00FFFFFFU 153#define LPDDR4__DENALI_CTL_8__TINIT3_F0_SHIFT 0U 154#define LPDDR4__DENALI_CTL_8__TINIT3_F0_WIDTH 24U 155#define LPDDR4__TINIT3_F0__REG DENALI_CTL_8 156#define LPDDR4__TINIT3_F0__FLD LPDDR4__DENALI_CTL_8__TINIT3_F0 157 158#define LPDDR4__DENALI_CTL_9_READ_MASK 0x00FFFFFFU 159#define LPDDR4__DENALI_CTL_9_WRITE_MASK 0x00FFFFFFU 160#define LPDDR4__DENALI_CTL_9__TINIT4_F0_MASK 0x00FFFFFFU 161#define LPDDR4__DENALI_CTL_9__TINIT4_F0_SHIFT 0U 162#define LPDDR4__DENALI_CTL_9__TINIT4_F0_WIDTH 24U 163#define LPDDR4__TINIT4_F0__REG DENALI_CTL_9 164#define LPDDR4__TINIT4_F0__FLD LPDDR4__DENALI_CTL_9__TINIT4_F0 165 166#define LPDDR4__DENALI_CTL_10_READ_MASK 0x00FFFFFFU 167#define LPDDR4__DENALI_CTL_10_WRITE_MASK 0x00FFFFFFU 168#define LPDDR4__DENALI_CTL_10__TINIT5_F0_MASK 0x00FFFFFFU 169#define LPDDR4__DENALI_CTL_10__TINIT5_F0_SHIFT 0U 170#define LPDDR4__DENALI_CTL_10__TINIT5_F0_WIDTH 24U 171#define LPDDR4__TINIT5_F0__REG DENALI_CTL_10 172#define LPDDR4__TINIT5_F0__FLD LPDDR4__DENALI_CTL_10__TINIT5_F0 173 174#define LPDDR4__DENALI_CTL_11_READ_MASK 0x00FFFFFFU 175#define LPDDR4__DENALI_CTL_11_WRITE_MASK 0x00FFFFFFU 176#define LPDDR4__DENALI_CTL_11__TINIT_F1_MASK 0x00FFFFFFU 177#define LPDDR4__DENALI_CTL_11__TINIT_F1_SHIFT 0U 178#define LPDDR4__DENALI_CTL_11__TINIT_F1_WIDTH 24U 179#define LPDDR4__TINIT_F1__REG DENALI_CTL_11 180#define LPDDR4__TINIT_F1__FLD LPDDR4__DENALI_CTL_11__TINIT_F1 181 182#define LPDDR4__DENALI_CTL_12_READ_MASK 0x00FFFFFFU 183#define LPDDR4__DENALI_CTL_12_WRITE_MASK 0x00FFFFFFU 184#define LPDDR4__DENALI_CTL_12__TINIT3_F1_MASK 0x00FFFFFFU 185#define LPDDR4__DENALI_CTL_12__TINIT3_F1_SHIFT 0U 186#define LPDDR4__DENALI_CTL_12__TINIT3_F1_WIDTH 24U 187#define LPDDR4__TINIT3_F1__REG DENALI_CTL_12 188#define LPDDR4__TINIT3_F1__FLD LPDDR4__DENALI_CTL_12__TINIT3_F1 189 190#define LPDDR4__DENALI_CTL_13_READ_MASK 0x00FFFFFFU 191#define LPDDR4__DENALI_CTL_13_WRITE_MASK 0x00FFFFFFU 192#define LPDDR4__DENALI_CTL_13__TINIT4_F1_MASK 0x00FFFFFFU 193#define LPDDR4__DENALI_CTL_13__TINIT4_F1_SHIFT 0U 194#define LPDDR4__DENALI_CTL_13__TINIT4_F1_WIDTH 24U 195#define LPDDR4__TINIT4_F1__REG DENALI_CTL_13 196#define LPDDR4__TINIT4_F1__FLD LPDDR4__DENALI_CTL_13__TINIT4_F1 197 198#define LPDDR4__DENALI_CTL_14_READ_MASK 0x00FFFFFFU 199#define LPDDR4__DENALI_CTL_14_WRITE_MASK 0x00FFFFFFU 200#define LPDDR4__DENALI_CTL_14__TINIT5_F1_MASK 0x00FFFFFFU 201#define LPDDR4__DENALI_CTL_14__TINIT5_F1_SHIFT 0U 202#define LPDDR4__DENALI_CTL_14__TINIT5_F1_WIDTH 24U 203#define LPDDR4__TINIT5_F1__REG DENALI_CTL_14 204#define LPDDR4__TINIT5_F1__FLD LPDDR4__DENALI_CTL_14__TINIT5_F1 205 206#define LPDDR4__DENALI_CTL_15_READ_MASK 0x00FFFFFFU 207#define LPDDR4__DENALI_CTL_15_WRITE_MASK 0x00FFFFFFU 208#define LPDDR4__DENALI_CTL_15__TINIT_F2_MASK 0x00FFFFFFU 209#define LPDDR4__DENALI_CTL_15__TINIT_F2_SHIFT 0U 210#define LPDDR4__DENALI_CTL_15__TINIT_F2_WIDTH 24U 211#define LPDDR4__TINIT_F2__REG DENALI_CTL_15 212#define LPDDR4__TINIT_F2__FLD LPDDR4__DENALI_CTL_15__TINIT_F2 213 214#define LPDDR4__DENALI_CTL_16_READ_MASK 0x00FFFFFFU 215#define LPDDR4__DENALI_CTL_16_WRITE_MASK 0x00FFFFFFU 216#define LPDDR4__DENALI_CTL_16__TINIT3_F2_MASK 0x00FFFFFFU 217#define LPDDR4__DENALI_CTL_16__TINIT3_F2_SHIFT 0U 218#define LPDDR4__DENALI_CTL_16__TINIT3_F2_WIDTH 24U 219#define LPDDR4__TINIT3_F2__REG DENALI_CTL_16 220#define LPDDR4__TINIT3_F2__FLD LPDDR4__DENALI_CTL_16__TINIT3_F2 221 222#define LPDDR4__DENALI_CTL_17_READ_MASK 0x00FFFFFFU 223#define LPDDR4__DENALI_CTL_17_WRITE_MASK 0x00FFFFFFU 224#define LPDDR4__DENALI_CTL_17__TINIT4_F2_MASK 0x00FFFFFFU 225#define LPDDR4__DENALI_CTL_17__TINIT4_F2_SHIFT 0U 226#define LPDDR4__DENALI_CTL_17__TINIT4_F2_WIDTH 24U 227#define LPDDR4__TINIT4_F2__REG DENALI_CTL_17 228#define LPDDR4__TINIT4_F2__FLD LPDDR4__DENALI_CTL_17__TINIT4_F2 229 230#define LPDDR4__DENALI_CTL_18_READ_MASK 0x01FFFFFFU 231#define LPDDR4__DENALI_CTL_18_WRITE_MASK 0x01FFFFFFU 232#define LPDDR4__DENALI_CTL_18__TINIT5_F2_MASK 0x00FFFFFFU 233#define LPDDR4__DENALI_CTL_18__TINIT5_F2_SHIFT 0U 234#define LPDDR4__DENALI_CTL_18__TINIT5_F2_WIDTH 24U 235#define LPDDR4__TINIT5_F2__REG DENALI_CTL_18 236#define LPDDR4__TINIT5_F2__FLD LPDDR4__DENALI_CTL_18__TINIT5_F2 237 238#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_MASK 0x01000000U 239#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_SHIFT 24U 240#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WIDTH 1U 241#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOCLR 0U 242#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOSET 0U 243#define LPDDR4__NO_AUTO_MRR_INIT__REG DENALI_CTL_18 244#define LPDDR4__NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT 245 246#define LPDDR4__DENALI_CTL_19_READ_MASK 0x01010101U 247#define LPDDR4__DENALI_CTL_19_WRITE_MASK 0x01010101U 248#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_MASK 0x00000001U 249#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_SHIFT 0U 250#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WIDTH 1U 251#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOCLR 0U 252#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOSET 0U 253#define LPDDR4__MRR_ERROR_STATUS__REG DENALI_CTL_19 254#define LPDDR4__MRR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS 255 256#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_MASK 0x00000100U 257#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_SHIFT 8U 258#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WIDTH 1U 259#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOCLR 0U 260#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOSET 0U 261#define LPDDR4__DFI_INV_DATA_CS__REG DENALI_CTL_19 262#define LPDDR4__DFI_INV_DATA_CS__FLD LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS 263 264#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_MASK 0x00010000U 265#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_SHIFT 16U 266#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WIDTH 1U 267#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOCLR 0U 268#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOSET 0U 269#define LPDDR4__NO_MRW_INIT__REG DENALI_CTL_19 270#define LPDDR4__NO_MRW_INIT__FLD LPDDR4__DENALI_CTL_19__NO_MRW_INIT 271 272#define LPDDR4__DENALI_CTL_19__ODT_VALUE_MASK 0x01000000U 273#define LPDDR4__DENALI_CTL_19__ODT_VALUE_SHIFT 24U 274#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WIDTH 1U 275#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOCLR 0U 276#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOSET 0U 277#define LPDDR4__ODT_VALUE__REG DENALI_CTL_19 278#define LPDDR4__ODT_VALUE__FLD LPDDR4__DENALI_CTL_19__ODT_VALUE 279 280#define LPDDR4__DENALI_CTL_20_READ_MASK 0x03013F01U 281#define LPDDR4__DENALI_CTL_20_WRITE_MASK 0x03013F01U 282#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_MASK 0x00000001U 283#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_SHIFT 0U 284#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WIDTH 1U 285#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOCLR 0U 286#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOSET 0U 287#define LPDDR4__PHY_INDEP_TRAIN_MODE__REG DENALI_CTL_20 288#define LPDDR4__PHY_INDEP_TRAIN_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE 289 290#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_MASK 0x00003F00U 291#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_SHIFT 8U 292#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_WIDTH 6U 293#define LPDDR4__TSREF2PHYMSTR__REG DENALI_CTL_20 294#define LPDDR4__TSREF2PHYMSTR__FLD LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR 295 296#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_MASK 0x00010000U 297#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_SHIFT 16U 298#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WIDTH 1U 299#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOCLR 0U 300#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOSET 0U 301#define LPDDR4__PHY_INDEP_INIT_MODE__REG DENALI_CTL_20 302#define LPDDR4__PHY_INDEP_INIT_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE 303 304#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_MASK 0x03000000U 305#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_SHIFT 24U 306#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_WIDTH 2U 307#define LPDDR4__DFIBUS_FREQ_INIT__REG DENALI_CTL_20 308#define LPDDR4__DFIBUS_FREQ_INIT__FLD LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT 309 310#define LPDDR4__DENALI_CTL_21_READ_MASK 0x1F1F1F03U 311#define LPDDR4__DENALI_CTL_21_WRITE_MASK 0x1F1F1F03U 312#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_MASK 0x00000003U 313#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_SHIFT 0U 314#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_WIDTH 2U 315#define LPDDR4__DFIBUS_BOOT_FREQ__REG DENALI_CTL_21 316#define LPDDR4__DFIBUS_BOOT_FREQ__FLD LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ 317 318#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_MASK 0x00001F00U 319#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_SHIFT 8U 320#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_WIDTH 5U 321#define LPDDR4__DFIBUS_FREQ_F0__REG DENALI_CTL_21 322#define LPDDR4__DFIBUS_FREQ_F0__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0 323 324#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_MASK 0x001F0000U 325#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_SHIFT 16U 326#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_WIDTH 5U 327#define LPDDR4__DFIBUS_FREQ_F1__REG DENALI_CTL_21 328#define LPDDR4__DFIBUS_FREQ_F1__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1 329 330#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_MASK 0x1F000000U 331#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_SHIFT 24U 332#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_WIDTH 5U 333#define LPDDR4__DFIBUS_FREQ_F2__REG DENALI_CTL_21 334#define LPDDR4__DFIBUS_FREQ_F2__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2 335 336#define LPDDR4__DENALI_CTL_22_READ_MASK 0x00030303U 337#define LPDDR4__DENALI_CTL_22_WRITE_MASK 0x00030303U 338#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_MASK 0x00000003U 339#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_SHIFT 0U 340#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_WIDTH 2U 341#define LPDDR4__FREQ_CHANGE_TYPE_F0__REG DENALI_CTL_22 342#define LPDDR4__FREQ_CHANGE_TYPE_F0__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0 343 344#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_MASK 0x00000300U 345#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_SHIFT 8U 346#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_WIDTH 2U 347#define LPDDR4__FREQ_CHANGE_TYPE_F1__REG DENALI_CTL_22 348#define LPDDR4__FREQ_CHANGE_TYPE_F1__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1 349 350#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_MASK 0x00030000U 351#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_SHIFT 16U 352#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_WIDTH 2U 353#define LPDDR4__FREQ_CHANGE_TYPE_F2__REG DENALI_CTL_22 354#define LPDDR4__FREQ_CHANGE_TYPE_F2__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2 355 356#define LPDDR4__DENALI_CTL_23_READ_MASK 0xFFFFFFFFU 357#define LPDDR4__DENALI_CTL_23_WRITE_MASK 0xFFFFFFFFU 358#define LPDDR4__DENALI_CTL_23__TRST_PWRON_MASK 0xFFFFFFFFU 359#define LPDDR4__DENALI_CTL_23__TRST_PWRON_SHIFT 0U 360#define LPDDR4__DENALI_CTL_23__TRST_PWRON_WIDTH 32U 361#define LPDDR4__TRST_PWRON__REG DENALI_CTL_23 362#define LPDDR4__TRST_PWRON__FLD LPDDR4__DENALI_CTL_23__TRST_PWRON 363 364#define LPDDR4__DENALI_CTL_24_READ_MASK 0xFFFFFFFFU 365#define LPDDR4__DENALI_CTL_24_WRITE_MASK 0xFFFFFFFFU 366#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_MASK 0xFFFFFFFFU 367#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_SHIFT 0U 368#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_WIDTH 32U 369#define LPDDR4__CKE_INACTIVE__REG DENALI_CTL_24 370#define LPDDR4__CKE_INACTIVE__FLD LPDDR4__DENALI_CTL_24__CKE_INACTIVE 371 372#define LPDDR4__DENALI_CTL_25_READ_MASK 0xFFFFFF01U 373#define LPDDR4__DENALI_CTL_25_WRITE_MASK 0xFFFFFF01U 374#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_MASK 0x00000001U 375#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_SHIFT 0U 376#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WIDTH 1U 377#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOCLR 0U 378#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOSET 0U 379#define LPDDR4__MC_RESERVED0__REG DENALI_CTL_25 380#define LPDDR4__MC_RESERVED0__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED0 381 382#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_MASK 0xFFFFFF00U 383#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_SHIFT 8U 384#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_WIDTH 24U 385#define LPDDR4__MC_RESERVED1__REG DENALI_CTL_25 386#define LPDDR4__MC_RESERVED1__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED1 387 388#define LPDDR4__DENALI_CTL_26_READ_MASK 0x0001FFFFU 389#define LPDDR4__DENALI_CTL_26_WRITE_MASK 0x0001FFFFU 390#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_MASK 0x000000FFU 391#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_SHIFT 0U 392#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_WIDTH 8U 393#define LPDDR4__MC_RESERVED2__REG DENALI_CTL_26 394#define LPDDR4__MC_RESERVED2__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED2 395 396#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_MASK 0x0000FF00U 397#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_SHIFT 8U 398#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_WIDTH 8U 399#define LPDDR4__MC_RESERVED3__REG DENALI_CTL_26 400#define LPDDR4__MC_RESERVED3__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED3 401 402#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_MASK 0x00010000U 403#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_SHIFT 16U 404#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WIDTH 1U 405#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOCLR 0U 406#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOSET 0U 407#define LPDDR4__DQS_OSC_ENABLE__REG DENALI_CTL_26 408#define LPDDR4__DQS_OSC_ENABLE__FLD LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE 409 410#define LPDDR4__DENALI_CTL_27_READ_MASK 0xFF0F7FFFU 411#define LPDDR4__DENALI_CTL_27_WRITE_MASK 0xFF0F7FFFU 412#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_MASK 0x00007FFFU 413#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_SHIFT 0U 414#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_WIDTH 15U 415#define LPDDR4__DQS_OSC_PERIOD__REG DENALI_CTL_27 416#define LPDDR4__DQS_OSC_PERIOD__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD 417 418#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_MASK 0x000F0000U 419#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_SHIFT 16U 420#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_WIDTH 4U 421#define LPDDR4__FUNC_VALID_CYCLES__REG DENALI_CTL_27 422#define LPDDR4__FUNC_VALID_CYCLES__FLD LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES 423 424#define LPDDR4__DENALI_CTL_27__TOSCO_F0_MASK 0xFF000000U 425#define LPDDR4__DENALI_CTL_27__TOSCO_F0_SHIFT 24U 426#define LPDDR4__DENALI_CTL_27__TOSCO_F0_WIDTH 8U 427#define LPDDR4__TOSCO_F0__REG DENALI_CTL_27 428#define LPDDR4__TOSCO_F0__FLD LPDDR4__DENALI_CTL_27__TOSCO_F0 429 430#define LPDDR4__DENALI_CTL_28_READ_MASK 0xFFFFFFFFU 431#define LPDDR4__DENALI_CTL_28_WRITE_MASK 0xFFFFFFFFU 432#define LPDDR4__DENALI_CTL_28__TOSCO_F1_MASK 0x000000FFU 433#define LPDDR4__DENALI_CTL_28__TOSCO_F1_SHIFT 0U 434#define LPDDR4__DENALI_CTL_28__TOSCO_F1_WIDTH 8U 435#define LPDDR4__TOSCO_F1__REG DENALI_CTL_28 436#define LPDDR4__TOSCO_F1__FLD LPDDR4__DENALI_CTL_28__TOSCO_F1 437 438#define LPDDR4__DENALI_CTL_28__TOSCO_F2_MASK 0x0000FF00U 439#define LPDDR4__DENALI_CTL_28__TOSCO_F2_SHIFT 8U 440#define LPDDR4__DENALI_CTL_28__TOSCO_F2_WIDTH 8U 441#define LPDDR4__TOSCO_F2__REG DENALI_CTL_28 442#define LPDDR4__TOSCO_F2__FLD LPDDR4__DENALI_CTL_28__TOSCO_F2 443 444#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_MASK 0x00FF0000U 445#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_SHIFT 16U 446#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_WIDTH 8U 447#define LPDDR4__DQS_OSC_NORM_THRESHOLD__REG DENALI_CTL_28 448#define LPDDR4__DQS_OSC_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD 449 450#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_MASK 0xFF000000U 451#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_SHIFT 24U 452#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_WIDTH 8U 453#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__REG DENALI_CTL_28 454#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD 455 456#define LPDDR4__DENALI_CTL_29_READ_MASK 0xFFFFFFFFU 457#define LPDDR4__DENALI_CTL_29_WRITE_MASK 0xFFFFFFFFU 458#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_MASK 0x000000FFU 459#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_SHIFT 0U 460#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_WIDTH 8U 461#define LPDDR4__DQS_OSC_TIMEOUT__REG DENALI_CTL_29 462#define LPDDR4__DQS_OSC_TIMEOUT__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT 463 464#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_MASK 0x0000FF00U 465#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_SHIFT 8U 466#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_WIDTH 8U 467#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__REG DENALI_CTL_29 468#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD 469 470#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_MASK 0xFFFF0000U 471#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_SHIFT 16U 472#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_WIDTH 16U 473#define LPDDR4__OSC_VARIANCE_LIMIT__REG DENALI_CTL_29 474#define LPDDR4__OSC_VARIANCE_LIMIT__FLD LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT 475 476#define LPDDR4__DENALI_CTL_30_READ_MASK 0x00FFFF00U 477#define LPDDR4__DENALI_CTL_30_WRITE_MASK 0x00FFFF00U 478#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_MASK 0x00000001U 479#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_SHIFT 0U 480#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WIDTH 1U 481#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOCLR 0U 482#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOSET 0U 483#define LPDDR4__DQS_OSC_REQUEST__REG DENALI_CTL_30 484#define LPDDR4__DQS_OSC_REQUEST__FLD LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST 485 486#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_MASK 0x00FFFF00U 487#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_SHIFT 8U 488#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_WIDTH 16U 489#define LPDDR4__OSC_BASE_VALUE_0_CS0__REG DENALI_CTL_30 490#define LPDDR4__OSC_BASE_VALUE_0_CS0__FLD LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0 491 492#define LPDDR4__DENALI_CTL_31_READ_MASK 0xFFFFFFFFU 493#define LPDDR4__DENALI_CTL_31_WRITE_MASK 0xFFFFFFFFU 494#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_MASK 0x0000FFFFU 495#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_SHIFT 0U 496#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_WIDTH 16U 497#define LPDDR4__OSC_BASE_VALUE_1_CS0__REG DENALI_CTL_31 498#define LPDDR4__OSC_BASE_VALUE_1_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0 499 500#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_MASK 0xFFFF0000U 501#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_SHIFT 16U 502#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_WIDTH 16U 503#define LPDDR4__OSC_BASE_VALUE_2_CS0__REG DENALI_CTL_31 504#define LPDDR4__OSC_BASE_VALUE_2_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0 505 506#define LPDDR4__DENALI_CTL_32_READ_MASK 0xFFFFFFFFU 507#define LPDDR4__DENALI_CTL_32_WRITE_MASK 0xFFFFFFFFU 508#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_MASK 0x0000FFFFU 509#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_SHIFT 0U 510#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_WIDTH 16U 511#define LPDDR4__OSC_BASE_VALUE_3_CS0__REG DENALI_CTL_32 512#define LPDDR4__OSC_BASE_VALUE_3_CS0__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0 513 514#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_MASK 0xFFFF0000U 515#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_SHIFT 16U 516#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_WIDTH 16U 517#define LPDDR4__OSC_BASE_VALUE_0_CS1__REG DENALI_CTL_32 518#define LPDDR4__OSC_BASE_VALUE_0_CS1__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1 519 520#define LPDDR4__DENALI_CTL_33_READ_MASK 0xFFFFFFFFU 521#define LPDDR4__DENALI_CTL_33_WRITE_MASK 0xFFFFFFFFU 522#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_MASK 0x0000FFFFU 523#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_SHIFT 0U 524#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_WIDTH 16U 525#define LPDDR4__OSC_BASE_VALUE_1_CS1__REG DENALI_CTL_33 526#define LPDDR4__OSC_BASE_VALUE_1_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1 527 528#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_MASK 0xFFFF0000U 529#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_SHIFT 16U 530#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_WIDTH 16U 531#define LPDDR4__OSC_BASE_VALUE_2_CS1__REG DENALI_CTL_33 532#define LPDDR4__OSC_BASE_VALUE_2_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1 533 534#define LPDDR4__DENALI_CTL_34_READ_MASK 0x7F7FFFFFU 535#define LPDDR4__DENALI_CTL_34_WRITE_MASK 0x7F7FFFFFU 536#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_MASK 0x0000FFFFU 537#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_SHIFT 0U 538#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_WIDTH 16U 539#define LPDDR4__OSC_BASE_VALUE_3_CS1__REG DENALI_CTL_34 540#define LPDDR4__OSC_BASE_VALUE_3_CS1__FLD LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1 541 542#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_MASK 0x007F0000U 543#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_SHIFT 16U 544#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_WIDTH 7U 545#define LPDDR4__CASLAT_LIN_F0__REG DENALI_CTL_34 546#define LPDDR4__CASLAT_LIN_F0__FLD LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0 547 548#define LPDDR4__DENALI_CTL_34__WRLAT_F0_MASK 0x7F000000U 549#define LPDDR4__DENALI_CTL_34__WRLAT_F0_SHIFT 24U 550#define LPDDR4__DENALI_CTL_34__WRLAT_F0_WIDTH 7U 551#define LPDDR4__WRLAT_F0__REG DENALI_CTL_34 552#define LPDDR4__WRLAT_F0__FLD LPDDR4__DENALI_CTL_34__WRLAT_F0 553 554#define LPDDR4__DENALI_CTL_35_READ_MASK 0x7F7F7F7FU 555#define LPDDR4__DENALI_CTL_35_WRITE_MASK 0x7F7F7F7FU 556#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_MASK 0x0000007FU 557#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_SHIFT 0U 558#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_WIDTH 7U 559#define LPDDR4__CASLAT_LIN_F1__REG DENALI_CTL_35 560#define LPDDR4__CASLAT_LIN_F1__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1 561 562#define LPDDR4__DENALI_CTL_35__WRLAT_F1_MASK 0x00007F00U 563#define LPDDR4__DENALI_CTL_35__WRLAT_F1_SHIFT 8U 564#define LPDDR4__DENALI_CTL_35__WRLAT_F1_WIDTH 7U 565#define LPDDR4__WRLAT_F1__REG DENALI_CTL_35 566#define LPDDR4__WRLAT_F1__FLD LPDDR4__DENALI_CTL_35__WRLAT_F1 567 568#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_MASK 0x007F0000U 569#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_SHIFT 16U 570#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_WIDTH 7U 571#define LPDDR4__CASLAT_LIN_F2__REG DENALI_CTL_35 572#define LPDDR4__CASLAT_LIN_F2__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2 573 574#define LPDDR4__DENALI_CTL_35__WRLAT_F2_MASK 0x7F000000U 575#define LPDDR4__DENALI_CTL_35__WRLAT_F2_SHIFT 24U 576#define LPDDR4__DENALI_CTL_35__WRLAT_F2_WIDTH 7U 577#define LPDDR4__WRLAT_F2__REG DENALI_CTL_35 578#define LPDDR4__WRLAT_F2__FLD LPDDR4__DENALI_CTL_35__WRLAT_F2 579 580#define LPDDR4__DENALI_CTL_36_READ_MASK 0x00FF1F07U 581#define LPDDR4__DENALI_CTL_36_WRITE_MASK 0x00FF1F07U 582#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_MASK 0x00000007U 583#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_SHIFT 0U 584#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_WIDTH 3U 585#define LPDDR4__TBST_INT_INTERVAL__REG DENALI_CTL_36 586#define LPDDR4__TBST_INT_INTERVAL__FLD LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL 587 588#define LPDDR4__DENALI_CTL_36__TCCD_MASK 0x00001F00U 589#define LPDDR4__DENALI_CTL_36__TCCD_SHIFT 8U 590#define LPDDR4__DENALI_CTL_36__TCCD_WIDTH 5U 591#define LPDDR4__TCCD__REG DENALI_CTL_36 592#define LPDDR4__TCCD__FLD LPDDR4__DENALI_CTL_36__TCCD 593 594#define LPDDR4__DENALI_CTL_36__TRRD_F0_MASK 0x00FF0000U 595#define LPDDR4__DENALI_CTL_36__TRRD_F0_SHIFT 16U 596#define LPDDR4__DENALI_CTL_36__TRRD_F0_WIDTH 8U 597#define LPDDR4__TRRD_F0__REG DENALI_CTL_36 598#define LPDDR4__TRRD_F0__FLD LPDDR4__DENALI_CTL_36__TRRD_F0 599 600#define LPDDR4__DENALI_CTL_37_READ_MASK 0x3FFF01FFU 601#define LPDDR4__DENALI_CTL_37_WRITE_MASK 0x3FFF01FFU 602#define LPDDR4__DENALI_CTL_37__TRC_F0_MASK 0x000001FFU 603#define LPDDR4__DENALI_CTL_37__TRC_F0_SHIFT 0U 604#define LPDDR4__DENALI_CTL_37__TRC_F0_WIDTH 9U 605#define LPDDR4__TRC_F0__REG DENALI_CTL_37 606#define LPDDR4__TRC_F0__FLD LPDDR4__DENALI_CTL_37__TRC_F0 607 608#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_MASK 0x00FF0000U 609#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_SHIFT 16U 610#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_WIDTH 8U 611#define LPDDR4__TRAS_MIN_F0__REG DENALI_CTL_37 612#define LPDDR4__TRAS_MIN_F0__FLD LPDDR4__DENALI_CTL_37__TRAS_MIN_F0 613 614#define LPDDR4__DENALI_CTL_37__TWTR_F0_MASK 0x3F000000U 615#define LPDDR4__DENALI_CTL_37__TWTR_F0_SHIFT 24U 616#define LPDDR4__DENALI_CTL_37__TWTR_F0_WIDTH 6U 617#define LPDDR4__TWTR_F0__REG DENALI_CTL_37 618#define LPDDR4__TWTR_F0__FLD LPDDR4__DENALI_CTL_37__TWTR_F0 619 620#define LPDDR4__DENALI_CTL_38_READ_MASK 0xFF01FFFFU 621#define LPDDR4__DENALI_CTL_38_WRITE_MASK 0xFF01FFFFU 622#define LPDDR4__DENALI_CTL_38__TRP_F0_MASK 0x000000FFU 623#define LPDDR4__DENALI_CTL_38__TRP_F0_SHIFT 0U 624#define LPDDR4__DENALI_CTL_38__TRP_F0_WIDTH 8U 625#define LPDDR4__TRP_F0__REG DENALI_CTL_38 626#define LPDDR4__TRP_F0__FLD LPDDR4__DENALI_CTL_38__TRP_F0 627 628#define LPDDR4__DENALI_CTL_38__TFAW_F0_MASK 0x0001FF00U 629#define LPDDR4__DENALI_CTL_38__TFAW_F0_SHIFT 8U 630#define LPDDR4__DENALI_CTL_38__TFAW_F0_WIDTH 9U 631#define LPDDR4__TFAW_F0__REG DENALI_CTL_38 632#define LPDDR4__TFAW_F0__FLD LPDDR4__DENALI_CTL_38__TFAW_F0 633 634#define LPDDR4__DENALI_CTL_38__TRRD_F1_MASK 0xFF000000U 635#define LPDDR4__DENALI_CTL_38__TRRD_F1_SHIFT 24U 636#define LPDDR4__DENALI_CTL_38__TRRD_F1_WIDTH 8U 637#define LPDDR4__TRRD_F1__REG DENALI_CTL_38 638#define LPDDR4__TRRD_F1__FLD LPDDR4__DENALI_CTL_38__TRRD_F1 639 640#define LPDDR4__DENALI_CTL_39_READ_MASK 0x3FFF01FFU 641#define LPDDR4__DENALI_CTL_39_WRITE_MASK 0x3FFF01FFU 642#define LPDDR4__DENALI_CTL_39__TRC_F1_MASK 0x000001FFU 643#define LPDDR4__DENALI_CTL_39__TRC_F1_SHIFT 0U 644#define LPDDR4__DENALI_CTL_39__TRC_F1_WIDTH 9U 645#define LPDDR4__TRC_F1__REG DENALI_CTL_39 646#define LPDDR4__TRC_F1__FLD LPDDR4__DENALI_CTL_39__TRC_F1 647 648#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_MASK 0x00FF0000U 649#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_SHIFT 16U 650#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_WIDTH 8U 651#define LPDDR4__TRAS_MIN_F1__REG DENALI_CTL_39 652#define LPDDR4__TRAS_MIN_F1__FLD LPDDR4__DENALI_CTL_39__TRAS_MIN_F1 653 654#define LPDDR4__DENALI_CTL_39__TWTR_F1_MASK 0x3F000000U 655#define LPDDR4__DENALI_CTL_39__TWTR_F1_SHIFT 24U 656#define LPDDR4__DENALI_CTL_39__TWTR_F1_WIDTH 6U 657#define LPDDR4__TWTR_F1__REG DENALI_CTL_39 658#define LPDDR4__TWTR_F1__FLD LPDDR4__DENALI_CTL_39__TWTR_F1 659 660#define LPDDR4__DENALI_CTL_40_READ_MASK 0xFF01FFFFU 661#define LPDDR4__DENALI_CTL_40_WRITE_MASK 0xFF01FFFFU 662#define LPDDR4__DENALI_CTL_40__TRP_F1_MASK 0x000000FFU 663#define LPDDR4__DENALI_CTL_40__TRP_F1_SHIFT 0U 664#define LPDDR4__DENALI_CTL_40__TRP_F1_WIDTH 8U 665#define LPDDR4__TRP_F1__REG DENALI_CTL_40 666#define LPDDR4__TRP_F1__FLD LPDDR4__DENALI_CTL_40__TRP_F1 667 668#define LPDDR4__DENALI_CTL_40__TFAW_F1_MASK 0x0001FF00U 669#define LPDDR4__DENALI_CTL_40__TFAW_F1_SHIFT 8U 670#define LPDDR4__DENALI_CTL_40__TFAW_F1_WIDTH 9U 671#define LPDDR4__TFAW_F1__REG DENALI_CTL_40 672#define LPDDR4__TFAW_F1__FLD LPDDR4__DENALI_CTL_40__TFAW_F1 673 674#define LPDDR4__DENALI_CTL_40__TRRD_F2_MASK 0xFF000000U 675#define LPDDR4__DENALI_CTL_40__TRRD_F2_SHIFT 24U 676#define LPDDR4__DENALI_CTL_40__TRRD_F2_WIDTH 8U 677#define LPDDR4__TRRD_F2__REG DENALI_CTL_40 678#define LPDDR4__TRRD_F2__FLD LPDDR4__DENALI_CTL_40__TRRD_F2 679 680#define LPDDR4__DENALI_CTL_41_READ_MASK 0x3FFF01FFU 681#define LPDDR4__DENALI_CTL_41_WRITE_MASK 0x3FFF01FFU 682#define LPDDR4__DENALI_CTL_41__TRC_F2_MASK 0x000001FFU 683#define LPDDR4__DENALI_CTL_41__TRC_F2_SHIFT 0U 684#define LPDDR4__DENALI_CTL_41__TRC_F2_WIDTH 9U 685#define LPDDR4__TRC_F2__REG DENALI_CTL_41 686#define LPDDR4__TRC_F2__FLD LPDDR4__DENALI_CTL_41__TRC_F2 687 688#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_MASK 0x00FF0000U 689#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_SHIFT 16U 690#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_WIDTH 8U 691#define LPDDR4__TRAS_MIN_F2__REG DENALI_CTL_41 692#define LPDDR4__TRAS_MIN_F2__FLD LPDDR4__DENALI_CTL_41__TRAS_MIN_F2 693 694#define LPDDR4__DENALI_CTL_41__TWTR_F2_MASK 0x3F000000U 695#define LPDDR4__DENALI_CTL_41__TWTR_F2_SHIFT 24U 696#define LPDDR4__DENALI_CTL_41__TWTR_F2_WIDTH 6U 697#define LPDDR4__TWTR_F2__REG DENALI_CTL_41 698#define LPDDR4__TWTR_F2__FLD LPDDR4__DENALI_CTL_41__TWTR_F2 699 700#define LPDDR4__DENALI_CTL_42_READ_MASK 0x3F01FFFFU 701#define LPDDR4__DENALI_CTL_42_WRITE_MASK 0x3F01FFFFU 702#define LPDDR4__DENALI_CTL_42__TRP_F2_MASK 0x000000FFU 703#define LPDDR4__DENALI_CTL_42__TRP_F2_SHIFT 0U 704#define LPDDR4__DENALI_CTL_42__TRP_F2_WIDTH 8U 705#define LPDDR4__TRP_F2__REG DENALI_CTL_42 706#define LPDDR4__TRP_F2__FLD LPDDR4__DENALI_CTL_42__TRP_F2 707 708#define LPDDR4__DENALI_CTL_42__TFAW_F2_MASK 0x0001FF00U 709#define LPDDR4__DENALI_CTL_42__TFAW_F2_SHIFT 8U 710#define LPDDR4__DENALI_CTL_42__TFAW_F2_WIDTH 9U 711#define LPDDR4__TFAW_F2__REG DENALI_CTL_42 712#define LPDDR4__TFAW_F2__FLD LPDDR4__DENALI_CTL_42__TFAW_F2 713 714#define LPDDR4__DENALI_CTL_42__TCCDMW_MASK 0x3F000000U 715#define LPDDR4__DENALI_CTL_42__TCCDMW_SHIFT 24U 716#define LPDDR4__DENALI_CTL_42__TCCDMW_WIDTH 6U 717#define LPDDR4__TCCDMW__REG DENALI_CTL_42 718#define LPDDR4__TCCDMW__FLD LPDDR4__DENALI_CTL_42__TCCDMW 719 720#define LPDDR4__DENALI_CTL_43_READ_MASK 0x00FFFFFFU 721#define LPDDR4__DENALI_CTL_43_WRITE_MASK 0x00FFFFFFU 722#define LPDDR4__DENALI_CTL_43__TRTP_F0_MASK 0x000000FFU 723#define LPDDR4__DENALI_CTL_43__TRTP_F0_SHIFT 0U 724#define LPDDR4__DENALI_CTL_43__TRTP_F0_WIDTH 8U 725#define LPDDR4__TRTP_F0__REG DENALI_CTL_43 726#define LPDDR4__TRTP_F0__FLD LPDDR4__DENALI_CTL_43__TRTP_F0 727 728#define LPDDR4__DENALI_CTL_43__TMRD_F0_MASK 0x0000FF00U 729#define LPDDR4__DENALI_CTL_43__TMRD_F0_SHIFT 8U 730#define LPDDR4__DENALI_CTL_43__TMRD_F0_WIDTH 8U 731#define LPDDR4__TMRD_F0__REG DENALI_CTL_43 732#define LPDDR4__TMRD_F0__FLD LPDDR4__DENALI_CTL_43__TMRD_F0 733 734#define LPDDR4__DENALI_CTL_43__TMOD_F0_MASK 0x00FF0000U 735#define LPDDR4__DENALI_CTL_43__TMOD_F0_SHIFT 16U 736#define LPDDR4__DENALI_CTL_43__TMOD_F0_WIDTH 8U 737#define LPDDR4__TMOD_F0__REG DENALI_CTL_43 738#define LPDDR4__TMOD_F0__FLD LPDDR4__DENALI_CTL_43__TMOD_F0 739 740#define LPDDR4__DENALI_CTL_44_READ_MASK 0x1F01FFFFU 741#define LPDDR4__DENALI_CTL_44_WRITE_MASK 0x1F01FFFFU 742#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_MASK 0x0001FFFFU 743#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_SHIFT 0U 744#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_WIDTH 17U 745#define LPDDR4__TRAS_MAX_F0__REG DENALI_CTL_44 746#define LPDDR4__TRAS_MAX_F0__FLD LPDDR4__DENALI_CTL_44__TRAS_MAX_F0 747 748#define LPDDR4__DENALI_CTL_44__TCKE_F0_MASK 0x1F000000U 749#define LPDDR4__DENALI_CTL_44__TCKE_F0_SHIFT 24U 750#define LPDDR4__DENALI_CTL_44__TCKE_F0_WIDTH 5U 751#define LPDDR4__TCKE_F0__REG DENALI_CTL_44 752#define LPDDR4__TCKE_F0__FLD LPDDR4__DENALI_CTL_44__TCKE_F0 753 754#define LPDDR4__DENALI_CTL_45_READ_MASK 0xFFFFFFFFU 755#define LPDDR4__DENALI_CTL_45_WRITE_MASK 0xFFFFFFFFU 756#define LPDDR4__DENALI_CTL_45__TCKESR_F0_MASK 0x000000FFU 757#define LPDDR4__DENALI_CTL_45__TCKESR_F0_SHIFT 0U 758#define LPDDR4__DENALI_CTL_45__TCKESR_F0_WIDTH 8U 759#define LPDDR4__TCKESR_F0__REG DENALI_CTL_45 760#define LPDDR4__TCKESR_F0__FLD LPDDR4__DENALI_CTL_45__TCKESR_F0 761 762#define LPDDR4__DENALI_CTL_45__TRTP_F1_MASK 0x0000FF00U 763#define LPDDR4__DENALI_CTL_45__TRTP_F1_SHIFT 8U 764#define LPDDR4__DENALI_CTL_45__TRTP_F1_WIDTH 8U 765#define LPDDR4__TRTP_F1__REG DENALI_CTL_45 766#define LPDDR4__TRTP_F1__FLD LPDDR4__DENALI_CTL_45__TRTP_F1 767 768#define LPDDR4__DENALI_CTL_45__TMRD_F1_MASK 0x00FF0000U 769#define LPDDR4__DENALI_CTL_45__TMRD_F1_SHIFT 16U 770#define LPDDR4__DENALI_CTL_45__TMRD_F1_WIDTH 8U 771#define LPDDR4__TMRD_F1__REG DENALI_CTL_45 772#define LPDDR4__TMRD_F1__FLD LPDDR4__DENALI_CTL_45__TMRD_F1 773 774#define LPDDR4__DENALI_CTL_45__TMOD_F1_MASK 0xFF000000U 775#define LPDDR4__DENALI_CTL_45__TMOD_F1_SHIFT 24U 776#define LPDDR4__DENALI_CTL_45__TMOD_F1_WIDTH 8U 777#define LPDDR4__TMOD_F1__REG DENALI_CTL_45 778#define LPDDR4__TMOD_F1__FLD LPDDR4__DENALI_CTL_45__TMOD_F1 779 780#define LPDDR4__DENALI_CTL_46_READ_MASK 0x1F01FFFFU 781#define LPDDR4__DENALI_CTL_46_WRITE_MASK 0x1F01FFFFU 782#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_MASK 0x0001FFFFU 783#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_SHIFT 0U 784#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_WIDTH 17U 785#define LPDDR4__TRAS_MAX_F1__REG DENALI_CTL_46 786#define LPDDR4__TRAS_MAX_F1__FLD LPDDR4__DENALI_CTL_46__TRAS_MAX_F1 787 788#define LPDDR4__DENALI_CTL_46__TCKE_F1_MASK 0x1F000000U 789#define LPDDR4__DENALI_CTL_46__TCKE_F1_SHIFT 24U 790#define LPDDR4__DENALI_CTL_46__TCKE_F1_WIDTH 5U 791#define LPDDR4__TCKE_F1__REG DENALI_CTL_46 792#define LPDDR4__TCKE_F1__FLD LPDDR4__DENALI_CTL_46__TCKE_F1 793 794#define LPDDR4__DENALI_CTL_47_READ_MASK 0xFFFFFFFFU 795#define LPDDR4__DENALI_CTL_47_WRITE_MASK 0xFFFFFFFFU 796#define LPDDR4__DENALI_CTL_47__TCKESR_F1_MASK 0x000000FFU 797#define LPDDR4__DENALI_CTL_47__TCKESR_F1_SHIFT 0U 798#define LPDDR4__DENALI_CTL_47__TCKESR_F1_WIDTH 8U 799#define LPDDR4__TCKESR_F1__REG DENALI_CTL_47 800#define LPDDR4__TCKESR_F1__FLD LPDDR4__DENALI_CTL_47__TCKESR_F1 801 802#define LPDDR4__DENALI_CTL_47__TRTP_F2_MASK 0x0000FF00U 803#define LPDDR4__DENALI_CTL_47__TRTP_F2_SHIFT 8U 804#define LPDDR4__DENALI_CTL_47__TRTP_F2_WIDTH 8U 805#define LPDDR4__TRTP_F2__REG DENALI_CTL_47 806#define LPDDR4__TRTP_F2__FLD LPDDR4__DENALI_CTL_47__TRTP_F2 807 808#define LPDDR4__DENALI_CTL_47__TMRD_F2_MASK 0x00FF0000U 809#define LPDDR4__DENALI_CTL_47__TMRD_F2_SHIFT 16U 810#define LPDDR4__DENALI_CTL_47__TMRD_F2_WIDTH 8U 811#define LPDDR4__TMRD_F2__REG DENALI_CTL_47 812#define LPDDR4__TMRD_F2__FLD LPDDR4__DENALI_CTL_47__TMRD_F2 813 814#define LPDDR4__DENALI_CTL_47__TMOD_F2_MASK 0xFF000000U 815#define LPDDR4__DENALI_CTL_47__TMOD_F2_SHIFT 24U 816#define LPDDR4__DENALI_CTL_47__TMOD_F2_WIDTH 8U 817#define LPDDR4__TMOD_F2__REG DENALI_CTL_47 818#define LPDDR4__TMOD_F2__FLD LPDDR4__DENALI_CTL_47__TMOD_F2 819 820#define LPDDR4__DENALI_CTL_48_READ_MASK 0x1F01FFFFU 821#define LPDDR4__DENALI_CTL_48_WRITE_MASK 0x1F01FFFFU 822#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_MASK 0x0001FFFFU 823#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_SHIFT 0U 824#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_WIDTH 17U 825#define LPDDR4__TRAS_MAX_F2__REG DENALI_CTL_48 826#define LPDDR4__TRAS_MAX_F2__FLD LPDDR4__DENALI_CTL_48__TRAS_MAX_F2 827 828#define LPDDR4__DENALI_CTL_48__TCKE_F2_MASK 0x1F000000U 829#define LPDDR4__DENALI_CTL_48__TCKE_F2_SHIFT 24U 830#define LPDDR4__DENALI_CTL_48__TCKE_F2_WIDTH 5U 831#define LPDDR4__TCKE_F2__REG DENALI_CTL_48 832#define LPDDR4__TCKE_F2__FLD LPDDR4__DENALI_CTL_48__TCKE_F2 833 834#define LPDDR4__DENALI_CTL_49_READ_MASK 0x070707FFU 835#define LPDDR4__DENALI_CTL_49_WRITE_MASK 0x070707FFU 836#define LPDDR4__DENALI_CTL_49__TCKESR_F2_MASK 0x000000FFU 837#define LPDDR4__DENALI_CTL_49__TCKESR_F2_SHIFT 0U 838#define LPDDR4__DENALI_CTL_49__TCKESR_F2_WIDTH 8U 839#define LPDDR4__TCKESR_F2__REG DENALI_CTL_49 840#define LPDDR4__TCKESR_F2__FLD LPDDR4__DENALI_CTL_49__TCKESR_F2 841 842#define LPDDR4__DENALI_CTL_49__TPPD_MASK 0x00000700U 843#define LPDDR4__DENALI_CTL_49__TPPD_SHIFT 8U 844#define LPDDR4__DENALI_CTL_49__TPPD_WIDTH 3U 845#define LPDDR4__TPPD__REG DENALI_CTL_49 846#define LPDDR4__TPPD__FLD LPDDR4__DENALI_CTL_49__TPPD 847 848#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_MASK 0x00070000U 849#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_SHIFT 16U 850#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_WIDTH 3U 851#define LPDDR4__MC_RESERVED4__REG DENALI_CTL_49 852#define LPDDR4__MC_RESERVED4__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED4 853 854#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_MASK 0x07000000U 855#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_SHIFT 24U 856#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_WIDTH 3U 857#define LPDDR4__MC_RESERVED5__REG DENALI_CTL_49 858#define LPDDR4__MC_RESERVED5__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED5 859 860#define LPDDR4__DENALI_CTL_50_READ_MASK 0xFFFFFF01U 861#define LPDDR4__DENALI_CTL_50_WRITE_MASK 0xFFFFFF01U 862#define LPDDR4__DENALI_CTL_50__WRITEINTERP_MASK 0x00000001U 863#define LPDDR4__DENALI_CTL_50__WRITEINTERP_SHIFT 0U 864#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WIDTH 1U 865#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOCLR 0U 866#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOSET 0U 867#define LPDDR4__WRITEINTERP__REG DENALI_CTL_50 868#define LPDDR4__WRITEINTERP__FLD LPDDR4__DENALI_CTL_50__WRITEINTERP 869 870#define LPDDR4__DENALI_CTL_50__TRCD_F0_MASK 0x0000FF00U 871#define LPDDR4__DENALI_CTL_50__TRCD_F0_SHIFT 8U 872#define LPDDR4__DENALI_CTL_50__TRCD_F0_WIDTH 8U 873#define LPDDR4__TRCD_F0__REG DENALI_CTL_50 874#define LPDDR4__TRCD_F0__FLD LPDDR4__DENALI_CTL_50__TRCD_F0 875 876#define LPDDR4__DENALI_CTL_50__TWR_F0_MASK 0x00FF0000U 877#define LPDDR4__DENALI_CTL_50__TWR_F0_SHIFT 16U 878#define LPDDR4__DENALI_CTL_50__TWR_F0_WIDTH 8U 879#define LPDDR4__TWR_F0__REG DENALI_CTL_50 880#define LPDDR4__TWR_F0__FLD LPDDR4__DENALI_CTL_50__TWR_F0 881 882#define LPDDR4__DENALI_CTL_50__TRCD_F1_MASK 0xFF000000U 883#define LPDDR4__DENALI_CTL_50__TRCD_F1_SHIFT 24U 884#define LPDDR4__DENALI_CTL_50__TRCD_F1_WIDTH 8U 885#define LPDDR4__TRCD_F1__REG DENALI_CTL_50 886#define LPDDR4__TRCD_F1__FLD LPDDR4__DENALI_CTL_50__TRCD_F1 887 888#define LPDDR4__DENALI_CTL_51_READ_MASK 0x0FFFFFFFU 889#define LPDDR4__DENALI_CTL_51_WRITE_MASK 0x0FFFFFFFU 890#define LPDDR4__DENALI_CTL_51__TWR_F1_MASK 0x000000FFU 891#define LPDDR4__DENALI_CTL_51__TWR_F1_SHIFT 0U 892#define LPDDR4__DENALI_CTL_51__TWR_F1_WIDTH 8U 893#define LPDDR4__TWR_F1__REG DENALI_CTL_51 894#define LPDDR4__TWR_F1__FLD LPDDR4__DENALI_CTL_51__TWR_F1 895 896#define LPDDR4__DENALI_CTL_51__TRCD_F2_MASK 0x0000FF00U 897#define LPDDR4__DENALI_CTL_51__TRCD_F2_SHIFT 8U 898#define LPDDR4__DENALI_CTL_51__TRCD_F2_WIDTH 8U 899#define LPDDR4__TRCD_F2__REG DENALI_CTL_51 900#define LPDDR4__TRCD_F2__FLD LPDDR4__DENALI_CTL_51__TRCD_F2 901 902#define LPDDR4__DENALI_CTL_51__TWR_F2_MASK 0x00FF0000U 903#define LPDDR4__DENALI_CTL_51__TWR_F2_SHIFT 16U 904#define LPDDR4__DENALI_CTL_51__TWR_F2_WIDTH 8U 905#define LPDDR4__TWR_F2__REG DENALI_CTL_51 906#define LPDDR4__TWR_F2__FLD LPDDR4__DENALI_CTL_51__TWR_F2 907 908#define LPDDR4__DENALI_CTL_51__TMRR_MASK 0x0F000000U 909#define LPDDR4__DENALI_CTL_51__TMRR_SHIFT 24U 910#define LPDDR4__DENALI_CTL_51__TMRR_WIDTH 4U 911#define LPDDR4__TMRR__REG DENALI_CTL_51 912#define LPDDR4__TMRR__FLD LPDDR4__DENALI_CTL_51__TMRR 913 914#define LPDDR4__DENALI_CTL_52_READ_MASK 0x3F03FF1FU 915#define LPDDR4__DENALI_CTL_52_WRITE_MASK 0x3F03FF1FU 916#define LPDDR4__DENALI_CTL_52__TCACKEL_MASK 0x0000001FU 917#define LPDDR4__DENALI_CTL_52__TCACKEL_SHIFT 0U 918#define LPDDR4__DENALI_CTL_52__TCACKEL_WIDTH 5U 919#define LPDDR4__TCACKEL__REG DENALI_CTL_52 920#define LPDDR4__TCACKEL__FLD LPDDR4__DENALI_CTL_52__TCACKEL 921 922#define LPDDR4__DENALI_CTL_52__TCAENT_MASK 0x0003FF00U 923#define LPDDR4__DENALI_CTL_52__TCAENT_SHIFT 8U 924#define LPDDR4__DENALI_CTL_52__TCAENT_WIDTH 10U 925#define LPDDR4__TCAENT__REG DENALI_CTL_52 926#define LPDDR4__TCAENT__FLD LPDDR4__DENALI_CTL_52__TCAENT 927 928#define LPDDR4__DENALI_CTL_52__TCAMRD_MASK 0x3F000000U 929#define LPDDR4__DENALI_CTL_52__TCAMRD_SHIFT 24U 930#define LPDDR4__DENALI_CTL_52__TCAMRD_WIDTH 6U 931#define LPDDR4__TCAMRD__REG DENALI_CTL_52 932#define LPDDR4__TCAMRD__FLD LPDDR4__DENALI_CTL_52__TCAMRD 933 934#define LPDDR4__DENALI_CTL_53_READ_MASK 0x1F1F1F1FU 935#define LPDDR4__DENALI_CTL_53_WRITE_MASK 0x1F1F1F1FU 936#define LPDDR4__DENALI_CTL_53__TCAEXT_MASK 0x0000001FU 937#define LPDDR4__DENALI_CTL_53__TCAEXT_SHIFT 0U 938#define LPDDR4__DENALI_CTL_53__TCAEXT_WIDTH 5U 939#define LPDDR4__TCAEXT__REG DENALI_CTL_53 940#define LPDDR4__TCAEXT__FLD LPDDR4__DENALI_CTL_53__TCAEXT 941 942#define LPDDR4__DENALI_CTL_53__TCACKEH_MASK 0x00001F00U 943#define LPDDR4__DENALI_CTL_53__TCACKEH_SHIFT 8U 944#define LPDDR4__DENALI_CTL_53__TCACKEH_WIDTH 5U 945#define LPDDR4__TCACKEH__REG DENALI_CTL_53 946#define LPDDR4__TCACKEH__FLD LPDDR4__DENALI_CTL_53__TCACKEH 947 948#define LPDDR4__DENALI_CTL_53__TMRZ_F0_MASK 0x001F0000U 949#define LPDDR4__DENALI_CTL_53__TMRZ_F0_SHIFT 16U 950#define LPDDR4__DENALI_CTL_53__TMRZ_F0_WIDTH 5U 951#define LPDDR4__TMRZ_F0__REG DENALI_CTL_53 952#define LPDDR4__TMRZ_F0__FLD LPDDR4__DENALI_CTL_53__TMRZ_F0 953 954#define LPDDR4__DENALI_CTL_53__TMRZ_F1_MASK 0x1F000000U 955#define LPDDR4__DENALI_CTL_53__TMRZ_F1_SHIFT 24U 956#define LPDDR4__DENALI_CTL_53__TMRZ_F1_WIDTH 5U 957#define LPDDR4__TMRZ_F1__REG DENALI_CTL_53 958#define LPDDR4__TMRZ_F1__FLD LPDDR4__DENALI_CTL_53__TMRZ_F1 959 960#define LPDDR4__DENALI_CTL_54_READ_MASK 0x0101011FU 961#define LPDDR4__DENALI_CTL_54_WRITE_MASK 0x0101011FU 962#define LPDDR4__DENALI_CTL_54__TMRZ_F2_MASK 0x0000001FU 963#define LPDDR4__DENALI_CTL_54__TMRZ_F2_SHIFT 0U 964#define LPDDR4__DENALI_CTL_54__TMRZ_F2_WIDTH 5U 965#define LPDDR4__TMRZ_F2__REG DENALI_CTL_54 966#define LPDDR4__TMRZ_F2__FLD LPDDR4__DENALI_CTL_54__TMRZ_F2 967 968#define LPDDR4__DENALI_CTL_54__AP_MASK 0x00000100U 969#define LPDDR4__DENALI_CTL_54__AP_SHIFT 8U 970#define LPDDR4__DENALI_CTL_54__AP_WIDTH 1U 971#define LPDDR4__DENALI_CTL_54__AP_WOCLR 0U 972#define LPDDR4__DENALI_CTL_54__AP_WOSET 0U 973#define LPDDR4__AP__REG DENALI_CTL_54 974#define LPDDR4__AP__FLD LPDDR4__DENALI_CTL_54__AP 975 976#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_MASK 0x00010000U 977#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_SHIFT 16U 978#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WIDTH 1U 979#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOCLR 0U 980#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOSET 0U 981#define LPDDR4__CONCURRENTAP__REG DENALI_CTL_54 982#define LPDDR4__CONCURRENTAP__FLD LPDDR4__DENALI_CTL_54__CONCURRENTAP 983 984#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_MASK 0x01000000U 985#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_SHIFT 24U 986#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WIDTH 1U 987#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOCLR 0U 988#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOSET 0U 989#define LPDDR4__TRAS_LOCKOUT__REG DENALI_CTL_54 990#define LPDDR4__TRAS_LOCKOUT__FLD LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT 991 992#define LPDDR4__DENALI_CTL_55_READ_MASK 0x1FFFFFFFU 993#define LPDDR4__DENALI_CTL_55_WRITE_MASK 0x1FFFFFFFU 994#define LPDDR4__DENALI_CTL_55__TDAL_F0_MASK 0x000000FFU 995#define LPDDR4__DENALI_CTL_55__TDAL_F0_SHIFT 0U 996#define LPDDR4__DENALI_CTL_55__TDAL_F0_WIDTH 8U 997#define LPDDR4__TDAL_F0__REG DENALI_CTL_55 998#define LPDDR4__TDAL_F0__FLD LPDDR4__DENALI_CTL_55__TDAL_F0 999 1000#define LPDDR4__DENALI_CTL_55__TDAL_F1_MASK 0x0000FF00U
1001#define LPDDR4__DENALI_CTL_55__TDAL_F1_SHIFT 8U 1002#define LPDDR4__DENALI_CTL_55__TDAL_F1_WIDTH 8U 1003#define LPDDR4__TDAL_F1__REG DENALI_CTL_55 1004#define LPDDR4__TDAL_F1__FLD LPDDR4__DENALI_CTL_55__TDAL_F1 1005 1006#define LPDDR4__DENALI_CTL_55__TDAL_F2_MASK 0x00FF0000U 1007#define LPDDR4__DENALI_CTL_55__TDAL_F2_SHIFT 16U 1008#define LPDDR4__DENALI_CTL_55__TDAL_F2_WIDTH 8U 1009#define LPDDR4__TDAL_F2__REG DENALI_CTL_55 1010#define LPDDR4__TDAL_F2__FLD LPDDR4__DENALI_CTL_55__TDAL_F2 1011 1012#define LPDDR4__DENALI_CTL_55__BSTLEN_MASK 0x1F000000U 1013#define LPDDR4__DENALI_CTL_55__BSTLEN_SHIFT 24U 1014#define LPDDR4__DENALI_CTL_55__BSTLEN_WIDTH 5U 1015#define LPDDR4__BSTLEN__REG DENALI_CTL_55 1016#define LPDDR4__BSTLEN__FLD LPDDR4__DENALI_CTL_55__BSTLEN 1017 1018#define LPDDR4__DENALI_CTL_56_READ_MASK 0xFFFFFFFFU 1019#define LPDDR4__DENALI_CTL_56_WRITE_MASK 0xFFFFFFFFU 1020#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_MASK 0x000000FFU 1021#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_SHIFT 0U 1022#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_WIDTH 8U 1023#define LPDDR4__TRP_AB_F0_0__REG DENALI_CTL_56 1024#define LPDDR4__TRP_AB_F0_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_0 1025 1026#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_MASK 0x0000FF00U 1027#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_SHIFT 8U 1028#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_WIDTH 8U 1029#define LPDDR4__TRP_AB_F1_0__REG DENALI_CTL_56 1030#define LPDDR4__TRP_AB_F1_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F1_0 1031 1032#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_MASK 0x00FF0000U 1033#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_SHIFT 16U 1034#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_WIDTH 8U 1035#define LPDDR4__TRP_AB_F2_0__REG DENALI_CTL_56 1036#define LPDDR4__TRP_AB_F2_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F2_0 1037 1038#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_MASK 0xFF000000U 1039#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_SHIFT 24U 1040#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_WIDTH 8U 1041#define LPDDR4__TRP_AB_F0_1__REG DENALI_CTL_56 1042#define LPDDR4__TRP_AB_F0_1__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_1 1043 1044#define LPDDR4__DENALI_CTL_57_READ_MASK 0x0301FFFFU 1045#define LPDDR4__DENALI_CTL_57_WRITE_MASK 0x0301FFFFU 1046#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_MASK 0x000000FFU 1047#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_SHIFT 0U 1048#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_WIDTH 8U 1049#define LPDDR4__TRP_AB_F1_1__REG DENALI_CTL_57 1050#define LPDDR4__TRP_AB_F1_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F1_1 1051 1052#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_MASK 0x0000FF00U 1053#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_SHIFT 8U 1054#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_WIDTH 8U 1055#define LPDDR4__TRP_AB_F2_1__REG DENALI_CTL_57 1056#define LPDDR4__TRP_AB_F2_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F2_1 1057 1058#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_MASK 0x00010000U 1059#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_SHIFT 16U 1060#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WIDTH 1U 1061#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOCLR 0U 1062#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOSET 0U 1063#define LPDDR4__REG_DIMM_ENABLE__REG DENALI_CTL_57 1064#define LPDDR4__REG_DIMM_ENABLE__FLD LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE 1065 1066#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_MASK 0x03000000U 1067#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_SHIFT 24U 1068#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_WIDTH 2U 1069#define LPDDR4__MC_RESERVED6__REG DENALI_CTL_57 1070#define LPDDR4__MC_RESERVED6__FLD LPDDR4__DENALI_CTL_57__MC_RESERVED6 1071 1072#define LPDDR4__DENALI_CTL_58_READ_MASK 0x0101017FU 1073#define LPDDR4__DENALI_CTL_58_WRITE_MASK 0x0101017FU 1074#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_MASK 0x0000007FU 1075#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_SHIFT 0U 1076#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_WIDTH 7U 1077#define LPDDR4__MC_RESERVED7__REG DENALI_CTL_58 1078#define LPDDR4__MC_RESERVED7__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED7 1079 1080#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_MASK 0x00000100U 1081#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_SHIFT 8U 1082#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WIDTH 1U 1083#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOCLR 0U 1084#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOSET 0U 1085#define LPDDR4__OPTIMAL_RMODW_EN__REG DENALI_CTL_58 1086#define LPDDR4__OPTIMAL_RMODW_EN__FLD LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN 1087 1088#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_MASK 0x00010000U 1089#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_SHIFT 16U 1090#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WIDTH 1U 1091#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOCLR 0U 1092#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOSET 0U 1093#define LPDDR4__MC_RESERVED8__REG DENALI_CTL_58 1094#define LPDDR4__MC_RESERVED8__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED8 1095 1096#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_MASK 0x01000000U 1097#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_SHIFT 24U 1098#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WIDTH 1U 1099#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOCLR 0U 1100#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOSET 0U 1101#define LPDDR4__NO_MEMORY_DM__REG DENALI_CTL_58 1102#define LPDDR4__NO_MEMORY_DM__FLD LPDDR4__DENALI_CTL_58__NO_MEMORY_DM 1103 1104#define LPDDR4__DENALI_CTL_59_READ_MASK 0x07010100U 1105#define LPDDR4__DENALI_CTL_59_WRITE_MASK 0x07010100U 1106#define LPDDR4__DENALI_CTL_59__AREFRESH_MASK 0x00000001U 1107#define LPDDR4__DENALI_CTL_59__AREFRESH_SHIFT 0U 1108#define LPDDR4__DENALI_CTL_59__AREFRESH_WIDTH 1U 1109#define LPDDR4__DENALI_CTL_59__AREFRESH_WOCLR 0U 1110#define LPDDR4__DENALI_CTL_59__AREFRESH_WOSET 0U 1111#define LPDDR4__AREFRESH__REG DENALI_CTL_59 1112#define LPDDR4__AREFRESH__FLD LPDDR4__DENALI_CTL_59__AREFRESH 1113 1114#define LPDDR4__DENALI_CTL_59__AREF_STATUS_MASK 0x00000100U 1115#define LPDDR4__DENALI_CTL_59__AREF_STATUS_SHIFT 8U 1116#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WIDTH 1U 1117#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOCLR 0U 1118#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOSET 0U 1119#define LPDDR4__AREF_STATUS__REG DENALI_CTL_59 1120#define LPDDR4__AREF_STATUS__FLD LPDDR4__DENALI_CTL_59__AREF_STATUS 1121 1122#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_MASK 0x00010000U 1123#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_SHIFT 16U 1124#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WIDTH 1U 1125#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOCLR 0U 1126#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOSET 0U 1127#define LPDDR4__TREF_ENABLE__REG DENALI_CTL_59 1128#define LPDDR4__TREF_ENABLE__FLD LPDDR4__DENALI_CTL_59__TREF_ENABLE 1129 1130#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_MASK 0x07000000U 1131#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_SHIFT 24U 1132#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_WIDTH 3U 1133#define LPDDR4__MC_RESERVED9__REG DENALI_CTL_59 1134#define LPDDR4__MC_RESERVED9__FLD LPDDR4__DENALI_CTL_59__MC_RESERVED9 1135 1136#define LPDDR4__DENALI_CTL_60_READ_MASK 0x0003FF3FU 1137#define LPDDR4__DENALI_CTL_60_WRITE_MASK 0x0003FF3FU 1138#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_MASK 0x0000003FU 1139#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT 0U 1140#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_WIDTH 6U 1141#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__REG DENALI_CTL_60 1142#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__FLD LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH 1143 1144#define LPDDR4__DENALI_CTL_60__TRFC_F0_MASK 0x0003FF00U 1145#define LPDDR4__DENALI_CTL_60__TRFC_F0_SHIFT 8U 1146#define LPDDR4__DENALI_CTL_60__TRFC_F0_WIDTH 10U 1147#define LPDDR4__TRFC_F0__REG DENALI_CTL_60 1148#define LPDDR4__TRFC_F0__FLD LPDDR4__DENALI_CTL_60__TRFC_F0 1149 1150#define LPDDR4__DENALI_CTL_61_READ_MASK 0x000FFFFFU 1151#define LPDDR4__DENALI_CTL_61_WRITE_MASK 0x000FFFFFU 1152#define LPDDR4__DENALI_CTL_61__TREF_F0_MASK 0x000FFFFFU 1153#define LPDDR4__DENALI_CTL_61__TREF_F0_SHIFT 0U 1154#define LPDDR4__DENALI_CTL_61__TREF_F0_WIDTH 20U 1155#define LPDDR4__TREF_F0__REG DENALI_CTL_61 1156#define LPDDR4__TREF_F0__FLD LPDDR4__DENALI_CTL_61__TREF_F0 1157 1158#define LPDDR4__DENALI_CTL_62_READ_MASK 0x000003FFU 1159#define LPDDR4__DENALI_CTL_62_WRITE_MASK 0x000003FFU 1160#define LPDDR4__DENALI_CTL_62__TRFC_F1_MASK 0x000003FFU 1161#define LPDDR4__DENALI_CTL_62__TRFC_F1_SHIFT 0U 1162#define LPDDR4__DENALI_CTL_62__TRFC_F1_WIDTH 10U 1163#define LPDDR4__TRFC_F1__REG DENALI_CTL_62 1164#define LPDDR4__TRFC_F1__FLD LPDDR4__DENALI_CTL_62__TRFC_F1 1165 1166#define LPDDR4__DENALI_CTL_63_READ_MASK 0x000FFFFFU 1167#define LPDDR4__DENALI_CTL_63_WRITE_MASK 0x000FFFFFU 1168#define LPDDR4__DENALI_CTL_63__TREF_F1_MASK 0x000FFFFFU 1169#define LPDDR4__DENALI_CTL_63__TREF_F1_SHIFT 0U 1170#define LPDDR4__DENALI_CTL_63__TREF_F1_WIDTH 20U 1171#define LPDDR4__TREF_F1__REG DENALI_CTL_63 1172#define LPDDR4__TREF_F1__FLD LPDDR4__DENALI_CTL_63__TREF_F1 1173 1174#define LPDDR4__DENALI_CTL_64_READ_MASK 0x000003FFU 1175#define LPDDR4__DENALI_CTL_64_WRITE_MASK 0x000003FFU 1176#define LPDDR4__DENALI_CTL_64__TRFC_F2_MASK 0x000003FFU 1177#define LPDDR4__DENALI_CTL_64__TRFC_F2_SHIFT 0U 1178#define LPDDR4__DENALI_CTL_64__TRFC_F2_WIDTH 10U 1179#define LPDDR4__TRFC_F2__REG DENALI_CTL_64 1180#define LPDDR4__TRFC_F2__FLD LPDDR4__DENALI_CTL_64__TRFC_F2 1181 1182#define LPDDR4__DENALI_CTL_65_READ_MASK 0x000FFFFFU 1183#define LPDDR4__DENALI_CTL_65_WRITE_MASK 0x000FFFFFU 1184#define LPDDR4__DENALI_CTL_65__TREF_F2_MASK 0x000FFFFFU 1185#define LPDDR4__DENALI_CTL_65__TREF_F2_SHIFT 0U 1186#define LPDDR4__DENALI_CTL_65__TREF_F2_WIDTH 20U 1187#define LPDDR4__TREF_F2__REG DENALI_CTL_65 1188#define LPDDR4__TREF_F2__FLD LPDDR4__DENALI_CTL_65__TREF_F2 1189 1190#define LPDDR4__DENALI_CTL_66_READ_MASK 0x000FFFFFU 1191#define LPDDR4__DENALI_CTL_66_WRITE_MASK 0x000FFFFFU 1192#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_MASK 0x000FFFFFU 1193#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_SHIFT 0U 1194#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_WIDTH 20U 1195#define LPDDR4__TREF_INTERVAL__REG DENALI_CTL_66 1196#define LPDDR4__TREF_INTERVAL__FLD LPDDR4__DENALI_CTL_66__TREF_INTERVAL 1197 1198#define LPDDR4__DENALI_CTL_67_READ_MASK 0x03FF0101U 1199#define LPDDR4__DENALI_CTL_67_WRITE_MASK 0x03FF0101U 1200#define LPDDR4__DENALI_CTL_67__PBR_EN_MASK 0x00000001U 1201#define LPDDR4__DENALI_CTL_67__PBR_EN_SHIFT 0U 1202#define LPDDR4__DENALI_CTL_67__PBR_EN_WIDTH 1U 1203#define LPDDR4__DENALI_CTL_67__PBR_EN_WOCLR 0U 1204#define LPDDR4__DENALI_CTL_67__PBR_EN_WOSET 0U 1205#define LPDDR4__PBR_EN__REG DENALI_CTL_67 1206#define LPDDR4__PBR_EN__FLD LPDDR4__DENALI_CTL_67__PBR_EN 1207 1208#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_MASK 0x00000100U 1209#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_SHIFT 8U 1210#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WIDTH 1U 1211#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOCLR 0U 1212#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOSET 0U 1213#define LPDDR4__PBR_NUMERIC_ORDER__REG DENALI_CTL_67 1214#define LPDDR4__PBR_NUMERIC_ORDER__FLD LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER 1215 1216#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_MASK 0x03FF0000U 1217#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_SHIFT 16U 1218#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_WIDTH 10U 1219#define LPDDR4__TRFC_PB_F0__REG DENALI_CTL_67 1220#define LPDDR4__TRFC_PB_F0__FLD LPDDR4__DENALI_CTL_67__TRFC_PB_F0 1221 1222#define LPDDR4__DENALI_CTL_68_READ_MASK 0x03FFFFFFU 1223#define LPDDR4__DENALI_CTL_68_WRITE_MASK 0x03FFFFFFU 1224#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_MASK 0x0000FFFFU 1225#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_SHIFT 0U 1226#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_WIDTH 16U 1227#define LPDDR4__TREFI_PB_F0__REG DENALI_CTL_68 1228#define LPDDR4__TREFI_PB_F0__FLD LPDDR4__DENALI_CTL_68__TREFI_PB_F0 1229 1230#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_MASK 0x03FF0000U 1231#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_SHIFT 16U 1232#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_WIDTH 10U 1233#define LPDDR4__TRFC_PB_F1__REG DENALI_CTL_68 1234#define LPDDR4__TRFC_PB_F1__FLD LPDDR4__DENALI_CTL_68__TRFC_PB_F1 1235 1236#define LPDDR4__DENALI_CTL_69_READ_MASK 0x03FFFFFFU 1237#define LPDDR4__DENALI_CTL_69_WRITE_MASK 0x03FFFFFFU 1238#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_MASK 0x0000FFFFU 1239#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_SHIFT 0U 1240#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_WIDTH 16U 1241#define LPDDR4__TREFI_PB_F1__REG DENALI_CTL_69 1242#define LPDDR4__TREFI_PB_F1__FLD LPDDR4__DENALI_CTL_69__TREFI_PB_F1 1243 1244#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_MASK 0x03FF0000U 1245#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_SHIFT 16U 1246#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_WIDTH 10U 1247#define LPDDR4__TRFC_PB_F2__REG DENALI_CTL_69 1248#define LPDDR4__TRFC_PB_F2__FLD LPDDR4__DENALI_CTL_69__TRFC_PB_F2 1249 1250#define LPDDR4__DENALI_CTL_70_READ_MASK 0xFFFFFFFFU 1251#define LPDDR4__DENALI_CTL_70_WRITE_MASK 0xFFFFFFFFU 1252#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_MASK 0x0000FFFFU 1253#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_SHIFT 0U 1254#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_WIDTH 16U 1255#define LPDDR4__TREFI_PB_F2__REG DENALI_CTL_70 1256#define LPDDR4__TREFI_PB_F2__FLD LPDDR4__DENALI_CTL_70__TREFI_PB_F2 1257 1258#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_MASK 0xFFFF0000U 1259#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_SHIFT 16U 1260#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_WIDTH 16U 1261#define LPDDR4__PBR_MAX_BANK_WAIT__REG DENALI_CTL_70 1262#define LPDDR4__PBR_MAX_BANK_WAIT__FLD LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT 1263 1264#define LPDDR4__DENALI_CTL_71_READ_MASK 0x1F1F010FU 1265#define LPDDR4__DENALI_CTL_71_WRITE_MASK 0x1F1F010FU 1266#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_MASK 0x0000000FU 1267#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_SHIFT 0U 1268#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_WIDTH 4U 1269#define LPDDR4__PBR_BANK_SELECT_DELAY__REG DENALI_CTL_71 1270#define LPDDR4__PBR_BANK_SELECT_DELAY__FLD LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY 1271 1272#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_MASK 0x00000100U 1273#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_SHIFT 8U 1274#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WIDTH 1U 1275#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOCLR 0U 1276#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOSET 0U 1277#define LPDDR4__PBR_CONT_REQ_EN__REG DENALI_CTL_71 1278#define LPDDR4__PBR_CONT_REQ_EN__FLD LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN 1279 1280#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_MASK 0x001F0000U 1281#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_SHIFT 16U 1282#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_WIDTH 5U 1283#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__REG DENALI_CTL_71 1284#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD 1285 1286#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_MASK 0x1F000000U 1287#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_SHIFT 24U 1288#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_WIDTH 5U 1289#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__REG DENALI_CTL_71 1290#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD 1291 1292#define LPDDR4__DENALI_CTL_72_READ_MASK 0xFFFFFFFFU 1293#define LPDDR4__DENALI_CTL_72_WRITE_MASK 0xFFFFFFFFU 1294#define LPDDR4__DENALI_CTL_72__TPDEX_F0_MASK 0x0000FFFFU 1295#define LPDDR4__DENALI_CTL_72__TPDEX_F0_SHIFT 0U 1296#define LPDDR4__DENALI_CTL_72__TPDEX_F0_WIDTH 16U 1297#define LPDDR4__TPDEX_F0__REG DENALI_CTL_72 1298#define LPDDR4__TPDEX_F0__FLD LPDDR4__DENALI_CTL_72__TPDEX_F0 1299 1300#define LPDDR4__DENALI_CTL_72__TPDEX_F1_MASK 0xFFFF0000U 1301#define LPDDR4__DENALI_CTL_72__TPDEX_F1_SHIFT 16U 1302#define LPDDR4__DENALI_CTL_72__TPDEX_F1_WIDTH 16U 1303#define LPDDR4__TPDEX_F1__REG DENALI_CTL_72 1304#define LPDDR4__TPDEX_F1__FLD LPDDR4__DENALI_CTL_72__TPDEX_F1 1305 1306#define LPDDR4__DENALI_CTL_73_READ_MASK 0xFFFFFFFFU 1307#define LPDDR4__DENALI_CTL_73_WRITE_MASK 0xFFFFFFFFU 1308#define LPDDR4__DENALI_CTL_73__TPDEX_F2_MASK 0x0000FFFFU 1309#define LPDDR4__DENALI_CTL_73__TPDEX_F2_SHIFT 0U 1310#define LPDDR4__DENALI_CTL_73__TPDEX_F2_WIDTH 16U 1311#define LPDDR4__TPDEX_F2__REG DENALI_CTL_73 1312#define LPDDR4__TPDEX_F2__FLD LPDDR4__DENALI_CTL_73__TPDEX_F2 1313 1314#define LPDDR4__DENALI_CTL_73__TMRRI_F0_MASK 0x00FF0000U 1315#define LPDDR4__DENALI_CTL_73__TMRRI_F0_SHIFT 16U 1316#define LPDDR4__DENALI_CTL_73__TMRRI_F0_WIDTH 8U 1317#define LPDDR4__TMRRI_F0__REG DENALI_CTL_73 1318#define LPDDR4__TMRRI_F0__FLD LPDDR4__DENALI_CTL_73__TMRRI_F0 1319 1320#define LPDDR4__DENALI_CTL_73__TMRRI_F1_MASK 0xFF000000U 1321#define LPDDR4__DENALI_CTL_73__TMRRI_F1_SHIFT 24U 1322#define LPDDR4__DENALI_CTL_73__TMRRI_F1_WIDTH 8U 1323#define LPDDR4__TMRRI_F1__REG DENALI_CTL_73 1324#define LPDDR4__TMRRI_F1__FLD LPDDR4__DENALI_CTL_73__TMRRI_F1 1325 1326#define LPDDR4__DENALI_CTL_74_READ_MASK 0x1F1F1FFFU 1327#define LPDDR4__DENALI_CTL_74_WRITE_MASK 0x1F1F1FFFU 1328#define LPDDR4__DENALI_CTL_74__TMRRI_F2_MASK 0x000000FFU 1329#define LPDDR4__DENALI_CTL_74__TMRRI_F2_SHIFT 0U 1330#define LPDDR4__DENALI_CTL_74__TMRRI_F2_WIDTH 8U 1331#define LPDDR4__TMRRI_F2__REG DENALI_CTL_74 1332#define LPDDR4__TMRRI_F2__FLD LPDDR4__DENALI_CTL_74__TMRRI_F2 1333 1334#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_MASK 0x00001F00U 1335#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_SHIFT 8U 1336#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_WIDTH 5U 1337#define LPDDR4__TCSCKE_F0__REG DENALI_CTL_74 1338#define LPDDR4__TCSCKE_F0__FLD LPDDR4__DENALI_CTL_74__TCSCKE_F0 1339 1340#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_MASK 0x001F0000U 1341#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_SHIFT 16U 1342#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_WIDTH 5U 1343#define LPDDR4__TCKELCS_F0__REG DENALI_CTL_74 1344#define LPDDR4__TCKELCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKELCS_F0 1345 1346#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_MASK 0x1F000000U 1347#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_SHIFT 24U 1348#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_WIDTH 5U 1349#define LPDDR4__TCKEHCS_F0__REG DENALI_CTL_74 1350#define LPDDR4__TCKEHCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKEHCS_F0 1351 1352#define LPDDR4__DENALI_CTL_75_READ_MASK 0x1F010F1FU 1353#define LPDDR4__DENALI_CTL_75_WRITE_MASK 0x1F010F1FU 1354#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_MASK 0x0000001FU 1355#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_SHIFT 0U 1356#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_WIDTH 5U 1357#define LPDDR4__TMRWCKEL_F0__REG DENALI_CTL_75 1358#define LPDDR4__TMRWCKEL_F0__FLD LPDDR4__DENALI_CTL_75__TMRWCKEL_F0 1359 1360#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_MASK 0x00000F00U 1361#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_SHIFT 8U 1362#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_WIDTH 4U 1363#define LPDDR4__TZQCKE_F0__REG DENALI_CTL_75 1364#define LPDDR4__TZQCKE_F0__FLD LPDDR4__DENALI_CTL_75__TZQCKE_F0 1365 1366#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_MASK 0x00010000U 1367#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_SHIFT 16U 1368#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WIDTH 1U 1369#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOCLR 0U 1370#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOSET 0U 1371#define LPDDR4__CA_DEFAULT_VAL_F0__REG DENALI_CTL_75 1372#define LPDDR4__CA_DEFAULT_VAL_F0__FLD LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0 1373 1374#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_MASK 0x1F000000U 1375#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_SHIFT 24U 1376#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_WIDTH 5U 1377#define LPDDR4__TCSCKE_F1__REG DENALI_CTL_75 1378#define LPDDR4__TCSCKE_F1__FLD LPDDR4__DENALI_CTL_75__TCSCKE_F1 1379 1380#define LPDDR4__DENALI_CTL_76_READ_MASK 0x0F1F1F1FU 1381#define LPDDR4__DENALI_CTL_76_WRITE_MASK 0x0F1F1F1FU 1382#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_MASK 0x0000001FU 1383#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_SHIFT 0U 1384#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_WIDTH 5U 1385#define LPDDR4__TCKELCS_F1__REG DENALI_CTL_76 1386#define LPDDR4__TCKELCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKELCS_F1 1387 1388#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_MASK 0x00001F00U 1389#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_SHIFT 8U 1390#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_WIDTH 5U 1391#define LPDDR4__TCKEHCS_F1__REG DENALI_CTL_76 1392#define LPDDR4__TCKEHCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKEHCS_F1 1393 1394#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_MASK 0x001F0000U 1395#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_SHIFT 16U 1396#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_WIDTH 5U 1397#define LPDDR4__TMRWCKEL_F1__REG DENALI_CTL_76 1398#define LPDDR4__TMRWCKEL_F1__FLD LPDDR4__DENALI_CTL_76__TMRWCKEL_F1 1399 1400#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_MASK 0x0F000000U 1401#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_SHIFT 24U 1402#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_WIDTH 4U 1403#define LPDDR4__TZQCKE_F1__REG DENALI_CTL_76 1404#define LPDDR4__TZQCKE_F1__FLD LPDDR4__DENALI_CTL_76__TZQCKE_F1 1405 1406#define LPDDR4__DENALI_CTL_77_READ_MASK 0x1F1F1F01U 1407#define LPDDR4__DENALI_CTL_77_WRITE_MASK 0x1F1F1F01U 1408#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_MASK 0x00000001U 1409#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_SHIFT 0U 1410#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WIDTH 1U 1411#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOCLR 0U 1412#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOSET 0U 1413#define LPDDR4__CA_DEFAULT_VAL_F1__REG DENALI_CTL_77 1414#define LPDDR4__CA_DEFAULT_VAL_F1__FLD LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1 1415 1416#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_MASK 0x00001F00U 1417#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_SHIFT 8U 1418#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_WIDTH 5U 1419#define LPDDR4__TCSCKE_F2__REG DENALI_CTL_77 1420#define LPDDR4__TCSCKE_F2__FLD LPDDR4__DENALI_CTL_77__TCSCKE_F2 1421 1422#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_MASK 0x001F0000U 1423#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_SHIFT 16U 1424#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_WIDTH 5U 1425#define LPDDR4__TCKELCS_F2__REG DENALI_CTL_77 1426#define LPDDR4__TCKELCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKELCS_F2 1427 1428#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_MASK 0x1F000000U 1429#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_SHIFT 24U 1430#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_WIDTH 5U 1431#define LPDDR4__TCKEHCS_F2__REG DENALI_CTL_77 1432#define LPDDR4__TCKEHCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKEHCS_F2 1433 1434#define LPDDR4__DENALI_CTL_78_READ_MASK 0x00010F1FU 1435#define LPDDR4__DENALI_CTL_78_WRITE_MASK 0x00010F1FU 1436#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_MASK 0x0000001FU 1437#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_SHIFT 0U 1438#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_WIDTH 5U 1439#define LPDDR4__TMRWCKEL_F2__REG DENALI_CTL_78 1440#define LPDDR4__TMRWCKEL_F2__FLD LPDDR4__DENALI_CTL_78__TMRWCKEL_F2 1441 1442#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_MASK 0x00000F00U 1443#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_SHIFT 8U 1444#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_WIDTH 4U 1445#define LPDDR4__TZQCKE_F2__REG DENALI_CTL_78 1446#define LPDDR4__TZQCKE_F2__FLD LPDDR4__DENALI_CTL_78__TZQCKE_F2 1447 1448#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_MASK 0x00010000U 1449#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_SHIFT 16U 1450#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WIDTH 1U 1451#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOCLR 0U 1452#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOSET 0U 1453#define LPDDR4__CA_DEFAULT_VAL_F2__REG DENALI_CTL_78 1454#define LPDDR4__CA_DEFAULT_VAL_F2__FLD LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2 1455 1456#define LPDDR4__DENALI_CTL_79_READ_MASK 0xFFFFFFFFU 1457#define LPDDR4__DENALI_CTL_79_WRITE_MASK 0xFFFFFFFFU 1458#define LPDDR4__DENALI_CTL_79__TXSR_F0_MASK 0x0000FFFFU 1459#define LPDDR4__DENALI_CTL_79__TXSR_F0_SHIFT 0U 1460#define LPDDR4__DENALI_CTL_79__TXSR_F0_WIDTH 16U 1461#define LPDDR4__TXSR_F0__REG DENALI_CTL_79 1462#define LPDDR4__TXSR_F0__FLD LPDDR4__DENALI_CTL_79__TXSR_F0 1463 1464#define LPDDR4__DENALI_CTL_79__TXSNR_F0_MASK 0xFFFF0000U 1465#define LPDDR4__DENALI_CTL_79__TXSNR_F0_SHIFT 16U 1466#define LPDDR4__DENALI_CTL_79__TXSNR_F0_WIDTH 16U 1467#define LPDDR4__TXSNR_F0__REG DENALI_CTL_79 1468#define LPDDR4__TXSNR_F0__FLD LPDDR4__DENALI_CTL_79__TXSNR_F0 1469 1470#define LPDDR4__DENALI_CTL_80_READ_MASK 0xFFFFFFFFU 1471#define LPDDR4__DENALI_CTL_80_WRITE_MASK 0xFFFFFFFFU 1472#define LPDDR4__DENALI_CTL_80__TXSR_F1_MASK 0x0000FFFFU 1473#define LPDDR4__DENALI_CTL_80__TXSR_F1_SHIFT 0U 1474#define LPDDR4__DENALI_CTL_80__TXSR_F1_WIDTH 16U 1475#define LPDDR4__TXSR_F1__REG DENALI_CTL_80 1476#define LPDDR4__TXSR_F1__FLD LPDDR4__DENALI_CTL_80__TXSR_F1 1477 1478#define LPDDR4__DENALI_CTL_80__TXSNR_F1_MASK 0xFFFF0000U 1479#define LPDDR4__DENALI_CTL_80__TXSNR_F1_SHIFT 16U 1480#define LPDDR4__DENALI_CTL_80__TXSNR_F1_WIDTH 16U 1481#define LPDDR4__TXSNR_F1__REG DENALI_CTL_80 1482#define LPDDR4__TXSNR_F1__FLD LPDDR4__DENALI_CTL_80__TXSNR_F1 1483 1484#define LPDDR4__DENALI_CTL_81_READ_MASK 0xFFFFFFFFU 1485#define LPDDR4__DENALI_CTL_81_WRITE_MASK 0xFFFFFFFFU 1486#define LPDDR4__DENALI_CTL_81__TXSR_F2_MASK 0x0000FFFFU 1487#define LPDDR4__DENALI_CTL_81__TXSR_F2_SHIFT 0U 1488#define LPDDR4__DENALI_CTL_81__TXSR_F2_WIDTH 16U 1489#define LPDDR4__TXSR_F2__REG DENALI_CTL_81 1490#define LPDDR4__TXSR_F2__FLD LPDDR4__DENALI_CTL_81__TXSR_F2 1491 1492#define LPDDR4__DENALI_CTL_81__TXSNR_F2_MASK 0xFFFF0000U 1493#define LPDDR4__DENALI_CTL_81__TXSNR_F2_SHIFT 16U 1494#define LPDDR4__DENALI_CTL_81__TXSNR_F2_WIDTH 16U 1495#define LPDDR4__TXSNR_F2__REG DENALI_CTL_81 1496#define LPDDR4__TXSNR_F2__FLD LPDDR4__DENALI_CTL_81__TXSNR_F2 1497 1498#define LPDDR4__DENALI_CTL_82_READ_MASK 0xFF1F1F1FU 1499#define LPDDR4__DENALI_CTL_82_WRITE_MASK 0xFF1F1F1FU 1500#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_MASK 0x0000001FU 1501#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_SHIFT 0U 1502#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_WIDTH 5U 1503#define LPDDR4__TCKELCMD_F0__REG DENALI_CTL_82 1504#define LPDDR4__TCKELCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKELCMD_F0 1505 1506#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_MASK 0x00001F00U 1507#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_SHIFT 8U 1508#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_WIDTH 5U 1509#define LPDDR4__TCKEHCMD_F0__REG DENALI_CTL_82 1510#define LPDDR4__TCKEHCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKEHCMD_F0 1511 1512#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_MASK 0x001F0000U 1513#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_SHIFT 16U 1514#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_WIDTH 5U 1515#define LPDDR4__TCKCKEL_F0__REG DENALI_CTL_82 1516#define LPDDR4__TCKCKEL_F0__FLD LPDDR4__DENALI_CTL_82__TCKCKEL_F0 1517 1518#define LPDDR4__DENALI_CTL_82__TSR_F0_MASK 0xFF000000U 1519#define LPDDR4__DENALI_CTL_82__TSR_F0_SHIFT 24U 1520#define LPDDR4__DENALI_CTL_82__TSR_F0_WIDTH 8U 1521#define LPDDR4__TSR_F0__REG DENALI_CTL_82 1522#define LPDDR4__TSR_F0__FLD LPDDR4__DENALI_CTL_82__TSR_F0 1523 1524#define LPDDR4__DENALI_CTL_83_READ_MASK 0x1F1F1F07U 1525#define LPDDR4__DENALI_CTL_83_WRITE_MASK 0x1F1F1F07U 1526#define LPDDR4__DENALI_CTL_83__TESCKE_F0_MASK 0x00000007U 1527#define LPDDR4__DENALI_CTL_83__TESCKE_F0_SHIFT 0U 1528#define LPDDR4__DENALI_CTL_83__TESCKE_F0_WIDTH 3U 1529#define LPDDR4__TESCKE_F0__REG DENALI_CTL_83 1530#define LPDDR4__TESCKE_F0__FLD LPDDR4__DENALI_CTL_83__TESCKE_F0 1531 1532#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_MASK 0x00001F00U 1533#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_SHIFT 8U 1534#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_WIDTH 5U 1535#define LPDDR4__TCKELPD_F0__REG DENALI_CTL_83 1536#define LPDDR4__TCKELPD_F0__FLD LPDDR4__DENALI_CTL_83__TCKELPD_F0 1537 1538#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_MASK 0x001F0000U 1539#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_SHIFT 16U 1540#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_WIDTH 5U 1541#define LPDDR4__TCSCKEH_F0__REG DENALI_CTL_83 1542#define LPDDR4__TCSCKEH_F0__FLD LPDDR4__DENALI_CTL_83__TCSCKEH_F0 1543 1544#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_MASK 0x1F000000U 1545#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_SHIFT 24U 1546#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_WIDTH 5U 1547#define LPDDR4__TCMDCKE_F0__REG DENALI_CTL_83 1548#define LPDDR4__TCMDCKE_F0__FLD LPDDR4__DENALI_CTL_83__TCMDCKE_F0 1549 1550#define LPDDR4__DENALI_CTL_84_READ_MASK 0xFF1F1F1FU 1551#define LPDDR4__DENALI_CTL_84_WRITE_MASK 0xFF1F1F1FU 1552#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_MASK 0x0000001FU 1553#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_SHIFT 0U 1554#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_WIDTH 5U 1555#define LPDDR4__TCKELCMD_F1__REG DENALI_CTL_84 1556#define LPDDR4__TCKELCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKELCMD_F1 1557 1558#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_MASK 0x00001F00U 1559#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_SHIFT 8U 1560#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_WIDTH 5U 1561#define LPDDR4__TCKEHCMD_F1__REG DENALI_CTL_84 1562#define LPDDR4__TCKEHCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKEHCMD_F1 1563 1564#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_MASK 0x001F0000U 1565#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_SHIFT 16U 1566#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_WIDTH 5U 1567#define LPDDR4__TCKCKEL_F1__REG DENALI_CTL_84 1568#define LPDDR4__TCKCKEL_F1__FLD LPDDR4__DENALI_CTL_84__TCKCKEL_F1 1569 1570#define LPDDR4__DENALI_CTL_84__TSR_F1_MASK 0xFF000000U 1571#define LPDDR4__DENALI_CTL_84__TSR_F1_SHIFT 24U 1572#define LPDDR4__DENALI_CTL_84__TSR_F1_WIDTH 8U 1573#define LPDDR4__TSR_F1__REG DENALI_CTL_84 1574#define LPDDR4__TSR_F1__FLD LPDDR4__DENALI_CTL_84__TSR_F1 1575 1576#define LPDDR4__DENALI_CTL_85_READ_MASK 0x1F1F1F07U 1577#define LPDDR4__DENALI_CTL_85_WRITE_MASK 0x1F1F1F07U 1578#define LPDDR4__DENALI_CTL_85__TESCKE_F1_MASK 0x00000007U 1579#define LPDDR4__DENALI_CTL_85__TESCKE_F1_SHIFT 0U 1580#define LPDDR4__DENALI_CTL_85__TESCKE_F1_WIDTH 3U 1581#define LPDDR4__TESCKE_F1__REG DENALI_CTL_85 1582#define LPDDR4__TESCKE_F1__FLD LPDDR4__DENALI_CTL_85__TESCKE_F1 1583 1584#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_MASK 0x00001F00U 1585#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_SHIFT 8U 1586#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_WIDTH 5U 1587#define LPDDR4__TCKELPD_F1__REG DENALI_CTL_85 1588#define LPDDR4__TCKELPD_F1__FLD LPDDR4__DENALI_CTL_85__TCKELPD_F1 1589 1590#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_MASK 0x001F0000U 1591#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_SHIFT 16U 1592#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_WIDTH 5U 1593#define LPDDR4__TCSCKEH_F1__REG DENALI_CTL_85 1594#define LPDDR4__TCSCKEH_F1__FLD LPDDR4__DENALI_CTL_85__TCSCKEH_F1 1595 1596#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_MASK 0x1F000000U 1597#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_SHIFT 24U 1598#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_WIDTH 5U 1599#define LPDDR4__TCMDCKE_F1__REG DENALI_CTL_85 1600#define LPDDR4__TCMDCKE_F1__FLD LPDDR4__DENALI_CTL_85__TCMDCKE_F1 1601 1602#define LPDDR4__DENALI_CTL_86_READ_MASK 0xFF1F1F1FU 1603#define LPDDR4__DENALI_CTL_86_WRITE_MASK 0xFF1F1F1FU 1604#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_MASK 0x0000001FU 1605#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_SHIFT 0U 1606#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_WIDTH 5U 1607#define LPDDR4__TCKELCMD_F2__REG DENALI_CTL_86 1608#define LPDDR4__TCKELCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKELCMD_F2 1609 1610#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_MASK 0x00001F00U 1611#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_SHIFT 8U 1612#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_WIDTH 5U 1613#define LPDDR4__TCKEHCMD_F2__REG DENALI_CTL_86 1614#define LPDDR4__TCKEHCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKEHCMD_F2 1615 1616#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_MASK 0x001F0000U 1617#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_SHIFT 16U 1618#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_WIDTH 5U 1619#define LPDDR4__TCKCKEL_F2__REG DENALI_CTL_86 1620#define LPDDR4__TCKCKEL_F2__FLD LPDDR4__DENALI_CTL_86__TCKCKEL_F2 1621 1622#define LPDDR4__DENALI_CTL_86__TSR_F2_MASK 0xFF000000U 1623#define LPDDR4__DENALI_CTL_86__TSR_F2_SHIFT 24U 1624#define LPDDR4__DENALI_CTL_86__TSR_F2_WIDTH 8U 1625#define LPDDR4__TSR_F2__REG DENALI_CTL_86 1626#define LPDDR4__TSR_F2__FLD LPDDR4__DENALI_CTL_86__TSR_F2 1627 1628#define LPDDR4__DENALI_CTL_87_READ_MASK 0x1F1F1F07U 1629#define LPDDR4__DENALI_CTL_87_WRITE_MASK 0x1F1F1F07U 1630#define LPDDR4__DENALI_CTL_87__TESCKE_F2_MASK 0x00000007U 1631#define LPDDR4__DENALI_CTL_87__TESCKE_F2_SHIFT 0U 1632#define LPDDR4__DENALI_CTL_87__TESCKE_F2_WIDTH 3U 1633#define LPDDR4__TESCKE_F2__REG DENALI_CTL_87 1634#define LPDDR4__TESCKE_F2__FLD LPDDR4__DENALI_CTL_87__TESCKE_F2 1635 1636#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_MASK 0x00001F00U 1637#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_SHIFT 8U 1638#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_WIDTH 5U 1639#define LPDDR4__TCKELPD_F2__REG DENALI_CTL_87 1640#define LPDDR4__TCKELPD_F2__FLD LPDDR4__DENALI_CTL_87__TCKELPD_F2 1641 1642#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_MASK 0x001F0000U 1643#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_SHIFT 16U 1644#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_WIDTH 5U 1645#define LPDDR4__TCSCKEH_F2__REG DENALI_CTL_87 1646#define LPDDR4__TCSCKEH_F2__FLD LPDDR4__DENALI_CTL_87__TCSCKEH_F2 1647 1648#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_MASK 0x1F000000U 1649#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_SHIFT 24U 1650#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_WIDTH 5U 1651#define LPDDR4__TCMDCKE_F2__REG DENALI_CTL_87 1652#define LPDDR4__TCMDCKE_F2__FLD LPDDR4__DENALI_CTL_87__TCMDCKE_F2 1653 1654#define LPDDR4__DENALI_CTL_88_READ_MASK 0x07010101U 1655#define LPDDR4__DENALI_CTL_88_WRITE_MASK 0x07010101U 1656#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_MASK 0x00000001U 1657#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_SHIFT 0U 1658#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WIDTH 1U 1659#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOCLR 0U 1660#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOSET 0U 1661#define LPDDR4__PWRUP_SREFRESH_EXIT__REG DENALI_CTL_88 1662#define LPDDR4__PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT 1663 1664#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_MASK 0x00000100U 1665#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_SHIFT 8U 1666#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WIDTH 1U 1667#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOCLR 0U 1668#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOSET 0U 1669#define LPDDR4__MC_RESERVED10__REG DENALI_CTL_88 1670#define LPDDR4__MC_RESERVED10__FLD LPDDR4__DENALI_CTL_88__MC_RESERVED10 1671 1672#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_MASK 0x00010000U 1673#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_SHIFT 16U 1674#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WIDTH 1U 1675#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOCLR 0U 1676#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOSET 0U 1677#define LPDDR4__ENABLE_QUICK_SREFRESH__REG DENALI_CTL_88 1678#define LPDDR4__ENABLE_QUICK_SREFRESH__FLD LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH 1679 1680#define LPDDR4__DENALI_CTL_88__CKE_DELAY_MASK 0x07000000U 1681#define LPDDR4__DENALI_CTL_88__CKE_DELAY_SHIFT 24U 1682#define LPDDR4__DENALI_CTL_88__CKE_DELAY_WIDTH 3U 1683#define LPDDR4__CKE_DELAY__REG DENALI_CTL_88 1684#define LPDDR4__CKE_DELAY__FLD LPDDR4__DENALI_CTL_88__CKE_DELAY 1685 1686#define LPDDR4__DENALI_CTL_89_READ_MASK 0x01010300U 1687#define LPDDR4__DENALI_CTL_89_WRITE_MASK 0x01010300U 1688#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_MASK 0x0000001FU 1689#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_SHIFT 0U 1690#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_WIDTH 5U 1691#define LPDDR4__MC_RESERVED11__REG DENALI_CTL_89 1692#define LPDDR4__MC_RESERVED11__FLD LPDDR4__DENALI_CTL_89__MC_RESERVED11 1693 1694#define LPDDR4__DENALI_CTL_89__DFS_STATUS_MASK 0x00000300U 1695#define LPDDR4__DENALI_CTL_89__DFS_STATUS_SHIFT 8U 1696#define LPDDR4__DENALI_CTL_89__DFS_STATUS_WIDTH 2U 1697#define LPDDR4__DFS_STATUS__REG DENALI_CTL_89 1698#define LPDDR4__DFS_STATUS__FLD LPDDR4__DENALI_CTL_89__DFS_STATUS 1699 1700#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_MASK 0x00010000U 1701#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_SHIFT 16U 1702#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WIDTH 1U 1703#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOCLR 0U 1704#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOSET 0U 1705#define LPDDR4__DFS_ZQ_EN__REG DENALI_CTL_89 1706#define LPDDR4__DFS_ZQ_EN__FLD LPDDR4__DENALI_CTL_89__DFS_ZQ_EN 1707 1708#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_MASK 0x01000000U 1709#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_SHIFT 24U 1710#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WIDTH 1U 1711#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOCLR 0U 1712#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOSET 0U 1713#define LPDDR4__DFS_CALVL_EN__REG DENALI_CTL_89 1714#define LPDDR4__DFS_CALVL_EN__FLD LPDDR4__DENALI_CTL_89__DFS_CALVL_EN 1715 1716#define LPDDR4__DENALI_CTL_90_READ_MASK 0x00010101U 1717#define LPDDR4__DENALI_CTL_90_WRITE_MASK 0x00010101U 1718#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_MASK 0x00000001U 1719#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_SHIFT 0U 1720#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WIDTH 1U 1721#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOCLR 0U 1722#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOSET 0U 1723#define LPDDR4__DFS_WRLVL_EN__REG DENALI_CTL_90 1724#define LPDDR4__DFS_WRLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN 1725 1726#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_MASK 0x00000100U 1727#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_SHIFT 8U 1728#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WIDTH 1U 1729#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOCLR 0U 1730#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOSET 0U 1731#define LPDDR4__DFS_RDLVL_EN__REG DENALI_CTL_90 1732#define LPDDR4__DFS_RDLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN 1733 1734#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_MASK 0x00010000U 1735#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_SHIFT 16U 1736#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WIDTH 1U 1737#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOCLR 0U 1738#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOSET 0U 1739#define LPDDR4__DFS_RDLVL_GATE_EN__REG DENALI_CTL_90 1740#define LPDDR4__DFS_RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN 1741 1742#define LPDDR4__DENALI_CTL_91_READ_MASK 0xFFFFFFFFU 1743#define LPDDR4__DENALI_CTL_91_WRITE_MASK 0xFFFFFFFFU 1744#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU 1745#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_SHIFT 0U 1746#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_WIDTH 16U 1747#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_91 1748#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0 1749 1750#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U 1751#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_SHIFT 16U 1752#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_WIDTH 16U 1753#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_91 1754#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1 1755 1756#define LPDDR4__DENALI_CTL_92_READ_MASK 0x0707FFFFU 1757#define LPDDR4__DENALI_CTL_92_WRITE_MASK 0x0707FFFFU 1758#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU 1759#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_SHIFT 0U 1760#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_WIDTH 16U 1761#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_92 1762#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2 1763 1764#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_MASK 0x00070000U 1765#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_SHIFT 16U 1766#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_WIDTH 3U 1767#define LPDDR4__ZQ_STATUS_LOG__REG DENALI_CTL_92 1768#define LPDDR4__ZQ_STATUS_LOG__FLD LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG 1769 1770#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_MASK 0x07000000U 1771#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_SHIFT 24U 1772#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_WIDTH 3U 1773#define LPDDR4__MC_RESERVED12__REG DENALI_CTL_92 1774#define LPDDR4__MC_RESERVED12__FLD LPDDR4__DENALI_CTL_92__MC_RESERVED12 1775 1776#define LPDDR4__DENALI_CTL_93_READ_MASK 0xFFFFFF07U 1777#define LPDDR4__DENALI_CTL_93_WRITE_MASK 0xFFFFFF07U 1778#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_MASK 0x00000007U 1779#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_SHIFT 0U 1780#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_WIDTH 3U 1781#define LPDDR4__MC_RESERVED13__REG DENALI_CTL_93 1782#define LPDDR4__MC_RESERVED13__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED13 1783 1784#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_MASK 0x0000FF00U 1785#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_SHIFT 8U 1786#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_WIDTH 8U 1787#define LPDDR4__MC_RESERVED14__REG DENALI_CTL_93 1788#define LPDDR4__MC_RESERVED14__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED14 1789 1790#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_MASK 0x00FF0000U 1791#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_SHIFT 16U 1792#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_WIDTH 8U 1793#define LPDDR4__MC_RESERVED15__REG DENALI_CTL_93 1794#define LPDDR4__MC_RESERVED15__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED15 1795 1796#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_MASK 0xFF000000U 1797#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_SHIFT 24U 1798#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_WIDTH 8U 1799#define LPDDR4__MC_RESERVED16__REG DENALI_CTL_93 1800#define LPDDR4__MC_RESERVED16__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED16 1801 1802#define LPDDR4__DENALI_CTL_94_READ_MASK 0xFFFFFFFFU 1803#define LPDDR4__DENALI_CTL_94_WRITE_MASK 0xFFFFFFFFU 1804#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_MASK 0x0000FFFFU 1805#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_SHIFT 0U 1806#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_WIDTH 16U 1807#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__REG DENALI_CTL_94 1808#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0 1809 1810#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U 1811#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_SHIFT 16U 1812#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_WIDTH 16U 1813#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__REG DENALI_CTL_94 1814#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0 1815 1816#define LPDDR4__DENALI_CTL_95_READ_MASK 0xFFFFFFFFU 1817#define LPDDR4__DENALI_CTL_95_WRITE_MASK 0xFFFFFFFFU 1818#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_MASK 0x0000FFFFU 1819#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_SHIFT 0U 1820#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_WIDTH 16U 1821#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__REG DENALI_CTL_95 1822#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0 1823 1824#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U 1825#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U 1826#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U 1827#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_95 1828#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0 1829 1830#define LPDDR4__DENALI_CTL_96_READ_MASK 0xFFFFFFFFU 1831#define LPDDR4__DENALI_CTL_96_WRITE_MASK 0xFFFFFFFFU 1832#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU 1833#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U 1834#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U 1835#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_96 1836#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0 1837 1838#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_MASK 0xFFFF0000U 1839#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_SHIFT 16U 1840#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_WIDTH 16U 1841#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__REG DENALI_CTL_96 1842#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1 1843 1844#define LPDDR4__DENALI_CTL_97_READ_MASK 0xFFFFFFFFU 1845#define LPDDR4__DENALI_CTL_97_WRITE_MASK 0xFFFFFFFFU 1846#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU 1847#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_SHIFT 0U 1848#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_WIDTH 16U 1849#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__REG DENALI_CTL_97 1850#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1 1851 1852#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_MASK 0xFFFF0000U 1853#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_SHIFT 16U 1854#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_WIDTH 16U 1855#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__REG DENALI_CTL_97 1856#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1 1857 1858#define LPDDR4__DENALI_CTL_98_READ_MASK 0xFFFFFFFFU 1859#define LPDDR4__DENALI_CTL_98_WRITE_MASK 0xFFFFFFFFU 1860#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU 1861#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U 1862#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U 1863#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98 1864#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1 1865 1866#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U 1867#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U 1868#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U 1869#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98 1870#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1 1871 1872#define LPDDR4__DENALI_CTL_99_READ_MASK 0xFFFFFFFFU 1873#define LPDDR4__DENALI_CTL_99_WRITE_MASK 0xFFFFFFFFU 1874#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_MASK 0x0000FFFFU 1875#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_SHIFT 0U 1876#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_WIDTH 16U 1877#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__REG DENALI_CTL_99 1878#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2 1879 1880#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U 1881#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_SHIFT 16U 1882#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_WIDTH 16U 1883#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__REG DENALI_CTL_99 1884#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2 1885 1886#define LPDDR4__DENALI_CTL_100_READ_MASK 0xFFFFFFFFU 1887#define LPDDR4__DENALI_CTL_100_WRITE_MASK 0xFFFFFFFFU 1888#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_MASK 0x0000FFFFU 1889#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_SHIFT 0U 1890#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_WIDTH 16U 1891#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__REG DENALI_CTL_100 1892#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2 1893 1894#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U 1895#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U 1896#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U 1897#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_100 1898#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2 1899 1900#define LPDDR4__DENALI_CTL_101_READ_MASK 0x0000FFFFU 1901#define LPDDR4__DENALI_CTL_101_WRITE_MASK 0x0000FFFFU 1902#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU 1903#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U 1904#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U 1905#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_101 1906#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2 1907 1908#define LPDDR4__DENALI_CTL_102_READ_MASK 0xFFFFFFFFU 1909#define LPDDR4__DENALI_CTL_102_WRITE_MASK 0xFFFFFFFFU 1910#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_MASK 0xFFFFFFFFU 1911#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_SHIFT 0U 1912#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_WIDTH 32U 1913#define LPDDR4__TDFI_PHYMSTR_MAX_F0__REG DENALI_CTL_102 1914#define LPDDR4__TDFI_PHYMSTR_MAX_F0__FLD LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0 1915 1916#define LPDDR4__DENALI_CTL_103_READ_MASK 0xFFFFFFFFU 1917#define LPDDR4__DENALI_CTL_103_WRITE_MASK 0xFFFFFFFFU 1918#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_MASK 0xFFFFFFFFU 1919#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT 0U 1920#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_WIDTH 32U 1921#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__REG DENALI_CTL_103 1922#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__FLD LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0 1923 1924#define LPDDR4__DENALI_CTL_104_READ_MASK 0xFFFFFFFFU 1925#define LPDDR4__DENALI_CTL_104_WRITE_MASK 0xFFFFFFFFU 1926#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_MASK 0xFFFFFFFFU 1927#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT 0U 1928#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_WIDTH 32U 1929#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__REG DENALI_CTL_104 1930#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__FLD LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0 1931 1932#define LPDDR4__DENALI_CTL_105_READ_MASK 0xFFFFFFFFU 1933#define LPDDR4__DENALI_CTL_105_WRITE_MASK 0xFFFFFFFFU 1934#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_MASK 0xFFFFFFFFU 1935#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT 0U 1936#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_WIDTH 32U 1937#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__REG DENALI_CTL_105 1938#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__FLD LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0 1939 1940#define LPDDR4__DENALI_CTL_106_READ_MASK 0xFFFFFFFFU 1941#define LPDDR4__DENALI_CTL_106_WRITE_MASK 0xFFFFFFFFU 1942#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_MASK 0xFFFFFFFFU 1943#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT 0U 1944#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_WIDTH 32U 1945#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__REG DENALI_CTL_106 1946#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__FLD LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0 1947 1948#define LPDDR4__DENALI_CTL_107_READ_MASK 0x0000FFFFU 1949#define LPDDR4__DENALI_CTL_107_WRITE_MASK 0x0000FFFFU 1950#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU 1951#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_SHIFT 0U 1952#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_WIDTH 16U 1953#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_107 1954#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0 1955 1956#define LPDDR4__DENALI_CTL_108_READ_MASK 0x000FFFFFU 1957#define LPDDR4__DENALI_CTL_108_WRITE_MASK 0x000FFFFFU 1958#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_MASK 0x000FFFFFU 1959#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_SHIFT 0U 1960#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_WIDTH 20U 1961#define LPDDR4__TDFI_PHYMSTR_RESP_F0__REG DENALI_CTL_108 1962#define LPDDR4__TDFI_PHYMSTR_RESP_F0__FLD LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0 1963 1964#define LPDDR4__DENALI_CTL_109_READ_MASK 0xFFFFFFFFU 1965#define LPDDR4__DENALI_CTL_109_WRITE_MASK 0xFFFFFFFFU 1966#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_MASK 0xFFFFFFFFU 1967#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_SHIFT 0U 1968#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_WIDTH 32U 1969#define LPDDR4__TDFI_PHYMSTR_MAX_F1__REG DENALI_CTL_109 1970#define LPDDR4__TDFI_PHYMSTR_MAX_F1__FLD LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1 1971 1972#define LPDDR4__DENALI_CTL_110_READ_MASK 0xFFFFFFFFU 1973#define LPDDR4__DENALI_CTL_110_WRITE_MASK 0xFFFFFFFFU 1974#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_MASK 0xFFFFFFFFU 1975#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT 0U 1976#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_WIDTH 32U 1977#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__REG DENALI_CTL_110 1978#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__FLD LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1 1979 1980#define LPDDR4__DENALI_CTL_111_READ_MASK 0xFFFFFFFFU 1981#define LPDDR4__DENALI_CTL_111_WRITE_MASK 0xFFFFFFFFU 1982#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_MASK 0xFFFFFFFFU 1983#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT 0U 1984#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_WIDTH 32U 1985#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__REG DENALI_CTL_111 1986#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__FLD LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1 1987 1988#define LPDDR4__DENALI_CTL_112_READ_MASK 0xFFFFFFFFU 1989#define LPDDR4__DENALI_CTL_112_WRITE_MASK 0xFFFFFFFFU 1990#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_MASK 0xFFFFFFFFU 1991#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT 0U 1992#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_WIDTH 32U 1993#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__REG DENALI_CTL_112 1994#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__FLD LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1 1995 1996#define LPDDR4__DENALI_CTL_113_READ_MASK 0xFFFFFFFFU 1997#define LPDDR4__DENALI_CTL_113_WRITE_MASK 0xFFFFFFFFU 1998#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_MASK 0xFFFFFFFFU 1999#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT 0U 2000#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_WIDTH 32U
2001#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__REG DENALI_CTL_113 2002#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__FLD LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1 2003 2004#define LPDDR4__DENALI_CTL_114_READ_MASK 0x0000FFFFU 2005#define LPDDR4__DENALI_CTL_114_WRITE_MASK 0x0000FFFFU 2006#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU 2007#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_SHIFT 0U 2008#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_WIDTH 16U 2009#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_114 2010#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1 2011 2012#define LPDDR4__DENALI_CTL_115_READ_MASK 0x000FFFFFU 2013#define LPDDR4__DENALI_CTL_115_WRITE_MASK 0x000FFFFFU 2014#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_MASK 0x000FFFFFU 2015#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_SHIFT 0U 2016#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_WIDTH 20U 2017#define LPDDR4__TDFI_PHYMSTR_RESP_F1__REG DENALI_CTL_115 2018#define LPDDR4__TDFI_PHYMSTR_RESP_F1__FLD LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1 2019 2020#define LPDDR4__DENALI_CTL_116_READ_MASK 0xFFFFFFFFU 2021#define LPDDR4__DENALI_CTL_116_WRITE_MASK 0xFFFFFFFFU 2022#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_MASK 0xFFFFFFFFU 2023#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_SHIFT 0U 2024#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_WIDTH 32U 2025#define LPDDR4__TDFI_PHYMSTR_MAX_F2__REG DENALI_CTL_116 2026#define LPDDR4__TDFI_PHYMSTR_MAX_F2__FLD LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2 2027 2028#define LPDDR4__DENALI_CTL_117_READ_MASK 0xFFFFFFFFU 2029#define LPDDR4__DENALI_CTL_117_WRITE_MASK 0xFFFFFFFFU 2030#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_MASK 0xFFFFFFFFU 2031#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT 0U 2032#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_WIDTH 32U 2033#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__REG DENALI_CTL_117 2034#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__FLD LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2 2035 2036#define LPDDR4__DENALI_CTL_118_READ_MASK 0xFFFFFFFFU 2037#define LPDDR4__DENALI_CTL_118_WRITE_MASK 0xFFFFFFFFU 2038#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_MASK 0xFFFFFFFFU 2039#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT 0U 2040#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_WIDTH 32U 2041#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__REG DENALI_CTL_118 2042#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__FLD LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2 2043 2044#define LPDDR4__DENALI_CTL_119_READ_MASK 0xFFFFFFFFU 2045#define LPDDR4__DENALI_CTL_119_WRITE_MASK 0xFFFFFFFFU 2046#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_MASK 0xFFFFFFFFU 2047#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT 0U 2048#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_WIDTH 32U 2049#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__REG DENALI_CTL_119 2050#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__FLD LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2 2051 2052#define LPDDR4__DENALI_CTL_120_READ_MASK 0xFFFFFFFFU 2053#define LPDDR4__DENALI_CTL_120_WRITE_MASK 0xFFFFFFFFU 2054#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_MASK 0xFFFFFFFFU 2055#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT 0U 2056#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_WIDTH 32U 2057#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__REG DENALI_CTL_120 2058#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__FLD LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2 2059 2060#define LPDDR4__DENALI_CTL_121_READ_MASK 0x0000FFFFU 2061#define LPDDR4__DENALI_CTL_121_WRITE_MASK 0x0000FFFFU 2062#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU 2063#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_SHIFT 0U 2064#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_WIDTH 16U 2065#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_121 2066#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2 2067 2068#define LPDDR4__DENALI_CTL_122_READ_MASK 0x010FFFFFU 2069#define LPDDR4__DENALI_CTL_122_WRITE_MASK 0x010FFFFFU 2070#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_MASK 0x000FFFFFU 2071#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_SHIFT 0U 2072#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_WIDTH 20U 2073#define LPDDR4__TDFI_PHYMSTR_RESP_F2__REG DENALI_CTL_122 2074#define LPDDR4__TDFI_PHYMSTR_RESP_F2__FLD LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2 2075 2076#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_MASK 0x01000000U 2077#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_SHIFT 24U 2078#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WIDTH 1U 2079#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOCLR 0U 2080#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOSET 0U 2081#define LPDDR4__PHYMSTR_NO_AREF__REG DENALI_CTL_122 2082#define LPDDR4__PHYMSTR_NO_AREF__FLD LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF 2083 2084#define LPDDR4__DENALI_CTL_123_READ_MASK 0x00010103U 2085#define LPDDR4__DENALI_CTL_123_WRITE_MASK 0x00010103U 2086#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_MASK 0x00000003U 2087#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_SHIFT 0U 2088#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_WIDTH 2U 2089#define LPDDR4__PHYMSTR_ERROR_STATUS__REG DENALI_CTL_123 2090#define LPDDR4__PHYMSTR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS 2091 2092#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_MASK 0x00000100U 2093#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_SHIFT 8U 2094#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WIDTH 1U 2095#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WOCLR 0U 2096#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WOSET 0U 2097#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__REG DENALI_CTL_123 2098#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1 2099 2100#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_MASK 0x00010000U 2101#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_SHIFT 16U 2102#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WIDTH 1U 2103#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOCLR 0U 2104#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOSET 0U 2105#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__REG DENALI_CTL_123 2106#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE 2107 2108#define LPDDR4__DENALI_CTL_124_READ_MASK 0xFFFFFFFFU 2109#define LPDDR4__DENALI_CTL_124_WRITE_MASK 0xFFFFFFFFU 2110#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_MASK 0x0000FFFFU 2111#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_SHIFT 0U 2112#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_WIDTH 16U 2113#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__REG DENALI_CTL_124 2114#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0 2115 2116#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U 2117#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_SHIFT 16U 2118#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_WIDTH 16U 2119#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__REG DENALI_CTL_124 2120#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0 2121 2122#define LPDDR4__DENALI_CTL_125_READ_MASK 0xFFFFFFFFU 2123#define LPDDR4__DENALI_CTL_125_WRITE_MASK 0xFFFFFFFFU 2124#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_MASK 0x0000FFFFU 2125#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_SHIFT 0U 2126#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_WIDTH 16U 2127#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__REG DENALI_CTL_125 2128#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0 2129 2130#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_MASK 0xFFFF0000U 2131#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_SHIFT 16U 2132#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_WIDTH 16U 2133#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__REG DENALI_CTL_125 2134#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1 2135 2136#define LPDDR4__DENALI_CTL_126_READ_MASK 0xFFFFFFFFU 2137#define LPDDR4__DENALI_CTL_126_WRITE_MASK 0xFFFFFFFFU 2138#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU 2139#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_SHIFT 0U 2140#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_WIDTH 16U 2141#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__REG DENALI_CTL_126 2142#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1 2143 2144#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_MASK 0xFFFF0000U 2145#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_SHIFT 16U 2146#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_WIDTH 16U 2147#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__REG DENALI_CTL_126 2148#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1 2149 2150#define LPDDR4__DENALI_CTL_127_READ_MASK 0xFFFFFFFFU 2151#define LPDDR4__DENALI_CTL_127_WRITE_MASK 0xFFFFFFFFU 2152#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_MASK 0x0000FFFFU 2153#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_SHIFT 0U 2154#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_WIDTH 16U 2155#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__REG DENALI_CTL_127 2156#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2 2157 2158#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U 2159#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_SHIFT 16U 2160#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_WIDTH 16U 2161#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__REG DENALI_CTL_127 2162#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2 2163 2164#define LPDDR4__DENALI_CTL_128_READ_MASK 0x0001FFFFU 2165#define LPDDR4__DENALI_CTL_128_WRITE_MASK 0x0001FFFFU 2166#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_MASK 0x0000FFFFU 2167#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_SHIFT 0U 2168#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_WIDTH 16U 2169#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__REG DENALI_CTL_128 2170#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2 2171 2172#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_MASK 0x00010000U 2173#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_SHIFT 16U 2174#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WIDTH 1U 2175#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOCLR 0U 2176#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOSET 0U 2177#define LPDDR4__PPR_CONTROL__REG DENALI_CTL_128 2178#define LPDDR4__PPR_CONTROL__FLD LPDDR4__DENALI_CTL_128__PPR_CONTROL 2179 2180#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_MASK 0x07000000U 2181#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_SHIFT 24U 2182#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_WIDTH 3U 2183#define LPDDR4__PPR_COMMAND__REG DENALI_CTL_128 2184#define LPDDR4__PPR_COMMAND__FLD LPDDR4__DENALI_CTL_128__PPR_COMMAND 2185 2186#define LPDDR4__DENALI_CTL_129_READ_MASK 0x01FFFFFFU 2187#define LPDDR4__DENALI_CTL_129_WRITE_MASK 0x01FFFFFFU 2188#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_MASK 0x000000FFU 2189#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_SHIFT 0U 2190#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_WIDTH 8U 2191#define LPDDR4__PPR_COMMAND_MRW__REG DENALI_CTL_129 2192#define LPDDR4__PPR_COMMAND_MRW__FLD LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW 2193 2194#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_MASK 0x01FFFF00U 2195#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_SHIFT 8U 2196#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_WIDTH 17U 2197#define LPDDR4__PPR_ROW_ADDRESS__REG DENALI_CTL_129 2198#define LPDDR4__PPR_ROW_ADDRESS__FLD LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS 2199 2200#define LPDDR4__DENALI_CTL_130_READ_MASK 0x01030107U 2201#define LPDDR4__DENALI_CTL_130_WRITE_MASK 0x01030107U 2202#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_MASK 0x00000007U 2203#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_SHIFT 0U 2204#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_WIDTH 3U 2205#define LPDDR4__PPR_BANK_ADDRESS__REG DENALI_CTL_130 2206#define LPDDR4__PPR_BANK_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS 2207 2208#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_MASK 0x00000100U 2209#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_SHIFT 8U 2210#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WIDTH 1U 2211#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOCLR 0U 2212#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOSET 0U 2213#define LPDDR4__PPR_CS_ADDRESS__REG DENALI_CTL_130 2214#define LPDDR4__PPR_CS_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS 2215 2216#define LPDDR4__DENALI_CTL_130__PPR_STATUS_MASK 0x00030000U 2217#define LPDDR4__DENALI_CTL_130__PPR_STATUS_SHIFT 16U 2218#define LPDDR4__DENALI_CTL_130__PPR_STATUS_WIDTH 2U 2219#define LPDDR4__PPR_STATUS__REG DENALI_CTL_130 2220#define LPDDR4__PPR_STATUS__FLD LPDDR4__DENALI_CTL_130__PPR_STATUS 2221 2222#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_MASK 0x01000000U 2223#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_SHIFT 24U 2224#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WIDTH 1U 2225#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOCLR 0U 2226#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOSET 0U 2227#define LPDDR4__FM_OVRIDE_CONTROL__REG DENALI_CTL_130 2228#define LPDDR4__FM_OVRIDE_CONTROL__FLD LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL 2229 2230#define LPDDR4__DENALI_CTL_131_READ_MASK 0xFFFFFF03U 2231#define LPDDR4__DENALI_CTL_131_WRITE_MASK 0xFFFFFF03U 2232#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_MASK 0x00000003U 2233#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_SHIFT 0U 2234#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_WIDTH 2U 2235#define LPDDR4__LOWPOWER_REFRESH_ENABLE__REG DENALI_CTL_131 2236#define LPDDR4__LOWPOWER_REFRESH_ENABLE__FLD LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE 2237 2238#define LPDDR4__DENALI_CTL_131__CKSRE_F0_MASK 0x0000FF00U 2239#define LPDDR4__DENALI_CTL_131__CKSRE_F0_SHIFT 8U 2240#define LPDDR4__DENALI_CTL_131__CKSRE_F0_WIDTH 8U 2241#define LPDDR4__CKSRE_F0__REG DENALI_CTL_131 2242#define LPDDR4__CKSRE_F0__FLD LPDDR4__DENALI_CTL_131__CKSRE_F0 2243 2244#define LPDDR4__DENALI_CTL_131__CKSRX_F0_MASK 0x00FF0000U 2245#define LPDDR4__DENALI_CTL_131__CKSRX_F0_SHIFT 16U 2246#define LPDDR4__DENALI_CTL_131__CKSRX_F0_WIDTH 8U 2247#define LPDDR4__CKSRX_F0__REG DENALI_CTL_131 2248#define LPDDR4__CKSRX_F0__FLD LPDDR4__DENALI_CTL_131__CKSRX_F0 2249 2250#define LPDDR4__DENALI_CTL_131__CKSRE_F1_MASK 0xFF000000U 2251#define LPDDR4__DENALI_CTL_131__CKSRE_F1_SHIFT 24U 2252#define LPDDR4__DENALI_CTL_131__CKSRE_F1_WIDTH 8U 2253#define LPDDR4__CKSRE_F1__REG DENALI_CTL_131 2254#define LPDDR4__CKSRE_F1__FLD LPDDR4__DENALI_CTL_131__CKSRE_F1 2255 2256#define LPDDR4__DENALI_CTL_132_READ_MASK 0x00FFFFFFU 2257#define LPDDR4__DENALI_CTL_132_WRITE_MASK 0x00FFFFFFU 2258#define LPDDR4__DENALI_CTL_132__CKSRX_F1_MASK 0x000000FFU 2259#define LPDDR4__DENALI_CTL_132__CKSRX_F1_SHIFT 0U 2260#define LPDDR4__DENALI_CTL_132__CKSRX_F1_WIDTH 8U 2261#define LPDDR4__CKSRX_F1__REG DENALI_CTL_132 2262#define LPDDR4__CKSRX_F1__FLD LPDDR4__DENALI_CTL_132__CKSRX_F1 2263 2264#define LPDDR4__DENALI_CTL_132__CKSRE_F2_MASK 0x0000FF00U 2265#define LPDDR4__DENALI_CTL_132__CKSRE_F2_SHIFT 8U 2266#define LPDDR4__DENALI_CTL_132__CKSRE_F2_WIDTH 8U 2267#define LPDDR4__CKSRE_F2__REG DENALI_CTL_132 2268#define LPDDR4__CKSRE_F2__FLD LPDDR4__DENALI_CTL_132__CKSRE_F2 2269 2270#define LPDDR4__DENALI_CTL_132__CKSRX_F2_MASK 0x00FF0000U 2271#define LPDDR4__DENALI_CTL_132__CKSRX_F2_SHIFT 16U 2272#define LPDDR4__DENALI_CTL_132__CKSRX_F2_WIDTH 8U 2273#define LPDDR4__CKSRX_F2__REG DENALI_CTL_132 2274#define LPDDR4__CKSRX_F2__FLD LPDDR4__DENALI_CTL_132__CKSRX_F2 2275 2276#define LPDDR4__DENALI_CTL_132__LP_CMD_MASK 0x7F000000U 2277#define LPDDR4__DENALI_CTL_132__LP_CMD_SHIFT 24U 2278#define LPDDR4__DENALI_CTL_132__LP_CMD_WIDTH 7U 2279#define LPDDR4__LP_CMD__REG DENALI_CTL_132 2280#define LPDDR4__LP_CMD__FLD LPDDR4__DENALI_CTL_132__LP_CMD 2281 2282#define LPDDR4__DENALI_CTL_133_READ_MASK 0x0F0F0F0FU 2283#define LPDDR4__DENALI_CTL_133_WRITE_MASK 0x0F0F0F0FU 2284#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_MASK 0x0000000FU 2285#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_SHIFT 0U 2286#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_WIDTH 4U 2287#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__REG DENALI_CTL_133 2288#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0 2289 2290#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_MASK 0x00000F00U 2291#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_SHIFT 8U 2292#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_WIDTH 4U 2293#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG DENALI_CTL_133 2294#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0 2295 2296#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_MASK 0x000F0000U 2297#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_SHIFT 16U 2298#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_WIDTH 4U 2299#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG DENALI_CTL_133 2300#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0 2301 2302#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x0F000000U 2303#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 24U 2304#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U 2305#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_133 2306#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0 2307 2308#define LPDDR4__DENALI_CTL_134_READ_MASK 0x0F0F0F0FU 2309#define LPDDR4__DENALI_CTL_134_WRITE_MASK 0x0F0F0F0FU 2310#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_MASK 0x0000000FU 2311#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_SHIFT 0U 2312#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_WIDTH 4U 2313#define LPDDR4__LPI_PD_WAKEUP_F0__REG DENALI_CTL_134 2314#define LPDDR4__LPI_PD_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0 2315 2316#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_MASK 0x00000F00U 2317#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_SHIFT 8U 2318#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_WIDTH 4U 2319#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG DENALI_CTL_134 2320#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0 2321 2322#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_MASK 0x000F0000U 2323#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_SHIFT 16U 2324#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_WIDTH 4U 2325#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG DENALI_CTL_134 2326#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0 2327 2328#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x0F000000U 2329#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 24U 2330#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U 2331#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_134 2332#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0 2333 2334#define LPDDR4__DENALI_CTL_135_READ_MASK 0x0F0F0F0FU 2335#define LPDDR4__DENALI_CTL_135_WRITE_MASK 0x0F0F0F0FU 2336#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_MASK 0x0000000FU 2337#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_SHIFT 0U 2338#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_WIDTH 4U 2339#define LPDDR4__LPI_TIMER_WAKEUP_F0__REG DENALI_CTL_135 2340#define LPDDR4__LPI_TIMER_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0 2341 2342#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_MASK 0x00000F00U 2343#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_SHIFT 8U 2344#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_WIDTH 4U 2345#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__REG DENALI_CTL_135 2346#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1 2347 2348#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_MASK 0x000F0000U 2349#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_SHIFT 16U 2350#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_WIDTH 4U 2351#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG DENALI_CTL_135 2352#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1 2353 2354#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_MASK 0x0F000000U 2355#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_SHIFT 24U 2356#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_WIDTH 4U 2357#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG DENALI_CTL_135 2358#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1 2359 2360#define LPDDR4__DENALI_CTL_136_READ_MASK 0x0F0F0F0FU 2361#define LPDDR4__DENALI_CTL_136_WRITE_MASK 0x0F0F0F0FU 2362#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU 2363#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 0U 2364#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U 2365#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_136 2366#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1 2367 2368#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_MASK 0x00000F00U 2369#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_SHIFT 8U 2370#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_WIDTH 4U 2371#define LPDDR4__LPI_PD_WAKEUP_F1__REG DENALI_CTL_136 2372#define LPDDR4__LPI_PD_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1 2373 2374#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_MASK 0x000F0000U 2375#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_SHIFT 16U 2376#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_WIDTH 4U 2377#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG DENALI_CTL_136 2378#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1 2379 2380#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_MASK 0x0F000000U 2381#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_SHIFT 24U 2382#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_WIDTH 4U 2383#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG DENALI_CTL_136 2384#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1 2385 2386#define LPDDR4__DENALI_CTL_137_READ_MASK 0x0F0F0F0FU 2387#define LPDDR4__DENALI_CTL_137_WRITE_MASK 0x0F0F0F0FU 2388#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU 2389#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 0U 2390#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U 2391#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_137 2392#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1 2393 2394#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_MASK 0x00000F00U 2395#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_SHIFT 8U 2396#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_WIDTH 4U 2397#define LPDDR4__LPI_TIMER_WAKEUP_F1__REG DENALI_CTL_137 2398#define LPDDR4__LPI_TIMER_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1 2399 2400#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_MASK 0x000F0000U 2401#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_SHIFT 16U 2402#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_WIDTH 4U 2403#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__REG DENALI_CTL_137 2404#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2 2405 2406#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_MASK 0x0F000000U 2407#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_SHIFT 24U 2408#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_WIDTH 4U 2409#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG DENALI_CTL_137 2410#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2 2411 2412#define LPDDR4__DENALI_CTL_138_READ_MASK 0x0F0F0F0FU 2413#define LPDDR4__DENALI_CTL_138_WRITE_MASK 0x0F0F0F0FU 2414#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_MASK 0x0000000FU 2415#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_SHIFT 0U 2416#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_WIDTH 4U 2417#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG DENALI_CTL_138 2418#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2 2419 2420#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x00000F00U 2421#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 8U 2422#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U 2423#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_138 2424#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2 2425 2426#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_MASK 0x000F0000U 2427#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_SHIFT 16U 2428#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_WIDTH 4U 2429#define LPDDR4__LPI_PD_WAKEUP_F2__REG DENALI_CTL_138 2430#define LPDDR4__LPI_PD_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2 2431 2432#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_MASK 0x0F000000U 2433#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_SHIFT 24U 2434#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_WIDTH 4U 2435#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG DENALI_CTL_138 2436#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2 2437 2438#define LPDDR4__DENALI_CTL_139_READ_MASK 0x3F0F0F0FU 2439#define LPDDR4__DENALI_CTL_139_WRITE_MASK 0x3F0F0F0FU 2440#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_MASK 0x0000000FU 2441#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_SHIFT 0U 2442#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_WIDTH 4U 2443#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG DENALI_CTL_139 2444#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2 2445 2446#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x00000F00U 2447#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 8U 2448#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U 2449#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_139 2450#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 2451 2452#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_MASK 0x000F0000U 2453#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_SHIFT 16U 2454#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_WIDTH 4U 2455#define LPDDR4__LPI_TIMER_WAKEUP_F2__REG DENALI_CTL_139 2456#define LPDDR4__LPI_TIMER_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2 2457 2458#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_MASK 0x3F000000U 2459#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_SHIFT 24U 2460#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_WIDTH 6U 2461#define LPDDR4__LPI_WAKEUP_EN__REG DENALI_CTL_139 2462#define LPDDR4__LPI_WAKEUP_EN__FLD LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN 2463 2464#define LPDDR4__DENALI_CTL_140_READ_MASK 0x070FFF01U 2465#define LPDDR4__DENALI_CTL_140_WRITE_MASK 0x070FFF01U 2466#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_MASK 0x00000001U 2467#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_SHIFT 0U 2468#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WIDTH 1U 2469#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOCLR 0U 2470#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOSET 0U 2471#define LPDDR4__LPI_CTRL_REQ_EN__REG DENALI_CTL_140 2472#define LPDDR4__LPI_CTRL_REQ_EN__FLD LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN 2473 2474#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_MASK 0x000FFF00U 2475#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_SHIFT 8U 2476#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_WIDTH 12U 2477#define LPDDR4__LPI_WAKEUP_TIMEOUT__REG DENALI_CTL_140 2478#define LPDDR4__LPI_WAKEUP_TIMEOUT__FLD LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT 2479 2480#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_MASK 0x07000000U 2481#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_SHIFT 24U 2482#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_WIDTH 3U 2483#define LPDDR4__TDFI_LP_RESP__REG DENALI_CTL_140 2484#define LPDDR4__TDFI_LP_RESP__FLD LPDDR4__DENALI_CTL_140__TDFI_LP_RESP 2485 2486#define LPDDR4__DENALI_CTL_141_READ_MASK 0x0F0F7F7FU 2487#define LPDDR4__DENALI_CTL_141_WRITE_MASK 0x0F0F7F7FU 2488#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_MASK 0x0000007FU 2489#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_SHIFT 0U 2490#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_WIDTH 7U 2491#define LPDDR4__LP_STATE_CS0__REG DENALI_CTL_141 2492#define LPDDR4__LP_STATE_CS0__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS0 2493 2494#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_MASK 0x00007F00U 2495#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_SHIFT 8U 2496#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_WIDTH 7U 2497#define LPDDR4__LP_STATE_CS1__REG DENALI_CTL_141 2498#define LPDDR4__LP_STATE_CS1__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS1 2499 2500#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_MASK 0x000F0000U 2501#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_SHIFT 16U 2502#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_WIDTH 4U 2503#define LPDDR4__LP_AUTO_ENTRY_EN__REG DENALI_CTL_141 2504#define LPDDR4__LP_AUTO_ENTRY_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN 2505 2506#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_MASK 0x0F000000U 2507#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_SHIFT 24U 2508#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_WIDTH 4U 2509#define LPDDR4__LP_AUTO_EXIT_EN__REG DENALI_CTL_141 2510#define LPDDR4__LP_AUTO_EXIT_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN 2511 2512#define LPDDR4__DENALI_CTL_142_READ_MASK 0x000FFF07U 2513#define LPDDR4__DENALI_CTL_142_WRITE_MASK 0x000FFF07U 2514#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_MASK 0x00000007U 2515#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_SHIFT 0U 2516#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_WIDTH 3U 2517#define LPDDR4__LP_AUTO_MEM_GATE_EN__REG DENALI_CTL_142 2518#define LPDDR4__LP_AUTO_MEM_GATE_EN__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN 2519 2520#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_MASK 0x000FFF00U 2521#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_SHIFT 8U 2522#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_WIDTH 12U 2523#define LPDDR4__LP_AUTO_PD_IDLE__REG DENALI_CTL_142 2524#define LPDDR4__LP_AUTO_PD_IDLE__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE 2525 2526#define LPDDR4__DENALI_CTL_143_READ_MASK 0xFFFF0FFFU 2527#define LPDDR4__DENALI_CTL_143_WRITE_MASK 0xFFFF0FFFU 2528#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_MASK 0x00000FFFU 2529#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_SHIFT 0U 2530#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_WIDTH 12U 2531#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__REG DENALI_CTL_143 2532#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE 2533 2534#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_MASK 0x00FF0000U 2535#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_SHIFT 16U 2536#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_WIDTH 8U 2537#define LPDDR4__LP_AUTO_SR_LONG_IDLE__REG DENALI_CTL_143 2538#define LPDDR4__LP_AUTO_SR_LONG_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE 2539 2540#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_MASK 0xFF000000U 2541#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_SHIFT 24U 2542#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_WIDTH 8U 2543#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__REG DENALI_CTL_143 2544#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE 2545 2546#define LPDDR4__DENALI_CTL_144_READ_MASK 0xFFFFFFFFU 2547#define LPDDR4__DENALI_CTL_144_WRITE_MASK 0xFFFFFFFFU 2548#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU 2549#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_SHIFT 0U 2550#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_WIDTH 16U 2551#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_144 2552#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0 2553 2554#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U 2555#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_SHIFT 16U 2556#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_WIDTH 16U 2557#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_144 2558#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1 2559 2560#define LPDDR4__DENALI_CTL_145_READ_MASK 0xFFFFFFFFU 2561#define LPDDR4__DENALI_CTL_145_WRITE_MASK 0xFFFFFFFFU 2562#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU 2563#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_SHIFT 0U 2564#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_WIDTH 16U 2565#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_145 2566#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2 2567 2568#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U 2569#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_SHIFT 16U 2570#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_WIDTH 16U 2571#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_145 2572#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0 2573 2574#define LPDDR4__DENALI_CTL_146_READ_MASK 0xFFFFFFFFU 2575#define LPDDR4__DENALI_CTL_146_WRITE_MASK 0xFFFFFFFFU 2576#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU 2577#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_SHIFT 0U 2578#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_WIDTH 16U 2579#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_146 2580#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1 2581 2582#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U 2583#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_SHIFT 16U 2584#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_WIDTH 16U 2585#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_146 2586#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2 2587 2588#define LPDDR4__DENALI_CTL_147_READ_MASK 0x01010101U 2589#define LPDDR4__DENALI_CTL_147_WRITE_MASK 0x01010101U 2590#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_MASK 0x00000001U 2591#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_SHIFT 0U 2592#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WIDTH 1U 2593#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOCLR 0U 2594#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOSET 0U 2595#define LPDDR4__LPC_SR_CTRLUPD_EN__REG DENALI_CTL_147 2596#define LPDDR4__LPC_SR_CTRLUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN 2597 2598#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_MASK 0x00000100U 2599#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_SHIFT 8U 2600#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WIDTH 1U 2601#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOCLR 0U 2602#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOSET 0U 2603#define LPDDR4__LPC_SR_PHYUPD_EN__REG DENALI_CTL_147 2604#define LPDDR4__LPC_SR_PHYUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN 2605 2606#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_MASK 0x00010000U 2607#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_SHIFT 16U 2608#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WIDTH 1U 2609#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOCLR 0U 2610#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOSET 0U 2611#define LPDDR4__LPC_SR_PHYMSTR_EN__REG DENALI_CTL_147 2612#define LPDDR4__LPC_SR_PHYMSTR_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN 2613 2614#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_MASK 0x01000000U 2615#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_SHIFT 24U 2616#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WIDTH 1U 2617#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOCLR 0U 2618#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOSET 0U 2619#define LPDDR4__MC_RESERVED17__REG DENALI_CTL_147 2620#define LPDDR4__MC_RESERVED17__FLD LPDDR4__DENALI_CTL_147__MC_RESERVED17 2621 2622#define LPDDR4__DENALI_CTL_148_READ_MASK 0x3F3F0101U 2623#define LPDDR4__DENALI_CTL_148_WRITE_MASK 0x3F3F0101U 2624#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_MASK 0x00000001U 2625#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_SHIFT 0U 2626#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WIDTH 1U 2627#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOCLR 0U 2628#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOSET 0U 2629#define LPDDR4__LPC_SR_ZQ_EN__REG DENALI_CTL_148 2630#define LPDDR4__LPC_SR_ZQ_EN__FLD LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN 2631 2632#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_MASK 0x00000100U 2633#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_SHIFT 8U 2634#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WIDTH 1U 2635#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOCLR 0U 2636#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOSET 0U 2637#define LPDDR4__PCPCS_PD_EN__REG DENALI_CTL_148 2638#define LPDDR4__PCPCS_PD_EN__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EN 2639 2640#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_MASK 0x003F0000U 2641#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_SHIFT 16U 2642#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_WIDTH 6U 2643#define LPDDR4__PCPCS_PD_ENTER_DEPTH__REG DENALI_CTL_148 2644#define LPDDR4__PCPCS_PD_ENTER_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH 2645 2646#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_MASK 0x3F000000U 2647#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_SHIFT 24U 2648#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_WIDTH 6U 2649#define LPDDR4__PCPCS_PD_EXIT_DEPTH__REG DENALI_CTL_148 2650#define LPDDR4__PCPCS_PD_EXIT_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH 2651 2652#define LPDDR4__DENALI_CTL_149_READ_MASK 0x01FF03FFU 2653#define LPDDR4__DENALI_CTL_149_WRITE_MASK 0x01FF03FFU 2654#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_MASK 0x000000FFU 2655#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_SHIFT 0U 2656#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_WIDTH 8U 2657#define LPDDR4__PCPCS_PD_ENTER_TIMER__REG DENALI_CTL_149 2658#define LPDDR4__PCPCS_PD_ENTER_TIMER__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER 2659 2660#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_MASK 0x00000300U 2661#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_SHIFT 8U 2662#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_WIDTH 2U 2663#define LPDDR4__PCPCS_PD_MASK__REG DENALI_CTL_149 2664#define LPDDR4__PCPCS_PD_MASK__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK 2665 2666#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_MASK 0x00FF0000U 2667#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_SHIFT 16U 2668#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_WIDTH 8U 2669#define LPDDR4__MC_RESERVED18__REG DENALI_CTL_149 2670#define LPDDR4__MC_RESERVED18__FLD LPDDR4__DENALI_CTL_149__MC_RESERVED18 2671 2672#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_MASK 0x01000000U 2673#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_SHIFT 24U 2674#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WIDTH 1U 2675#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOCLR 0U 2676#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOSET 0U 2677#define LPDDR4__DFS_ENABLE__REG DENALI_CTL_149 2678#define LPDDR4__DFS_ENABLE__FLD LPDDR4__DENALI_CTL_149__DFS_ENABLE 2679 2680#define LPDDR4__DENALI_CTL_150_READ_MASK 0xFFFF03FFU 2681#define LPDDR4__DENALI_CTL_150_WRITE_MASK 0xFFFF03FFU 2682#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_MASK 0x000003FFU 2683#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_SHIFT 0U 2684#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_WIDTH 10U 2685#define LPDDR4__TDFI_INIT_START_F0__REG DENALI_CTL_150 2686#define LPDDR4__TDFI_INIT_START_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0 2687 2688#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_MASK 0xFFFF0000U 2689#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_SHIFT 16U 2690#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_WIDTH 16U 2691#define LPDDR4__TDFI_INIT_COMPLETE_F0__REG DENALI_CTL_150 2692#define LPDDR4__TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0 2693 2694#define LPDDR4__DENALI_CTL_151_READ_MASK 0xFFFF03FFU 2695#define LPDDR4__DENALI_CTL_151_WRITE_MASK 0xFFFF03FFU 2696#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_MASK 0x000003FFU 2697#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_SHIFT 0U 2698#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_WIDTH 10U 2699#define LPDDR4__TDFI_INIT_START_F1__REG DENALI_CTL_151 2700#define LPDDR4__TDFI_INIT_START_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1 2701 2702#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_MASK 0xFFFF0000U 2703#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_SHIFT 16U 2704#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_WIDTH 16U 2705#define LPDDR4__TDFI_INIT_COMPLETE_F1__REG DENALI_CTL_151 2706#define LPDDR4__TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1 2707 2708#define LPDDR4__DENALI_CTL_152_READ_MASK 0xFFFF03FFU 2709#define LPDDR4__DENALI_CTL_152_WRITE_MASK 0xFFFF03FFU 2710#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_MASK 0x000003FFU 2711#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_SHIFT 0U 2712#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_WIDTH 10U 2713#define LPDDR4__TDFI_INIT_START_F2__REG DENALI_CTL_152 2714#define LPDDR4__TDFI_INIT_START_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2 2715 2716#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_MASK 0xFFFF0000U 2717#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_SHIFT 16U 2718#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_WIDTH 16U 2719#define LPDDR4__TDFI_INIT_COMPLETE_F2__REG DENALI_CTL_152 2720#define LPDDR4__TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2 2721 2722#define LPDDR4__DENALI_CTL_153_READ_MASK 0x00000103U 2723#define LPDDR4__DENALI_CTL_153_WRITE_MASK 0x00000103U 2724#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_MASK 0x00000003U 2725#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_SHIFT 0U 2726#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_WIDTH 2U 2727#define LPDDR4__CURRENT_REG_COPY__REG DENALI_CTL_153 2728#define LPDDR4__CURRENT_REG_COPY__FLD LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY 2729 2730#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_MASK 0x00000100U 2731#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_SHIFT 8U 2732#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WIDTH 1U 2733#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOCLR 0U 2734#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOSET 0U 2735#define LPDDR4__DFS_PHY_REG_WRITE_EN__REG DENALI_CTL_153 2736#define LPDDR4__DFS_PHY_REG_WRITE_EN__FLD LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN 2737 2738#define LPDDR4__DENALI_CTL_154_READ_MASK 0xFFFFFFFFU 2739#define LPDDR4__DENALI_CTL_154_WRITE_MASK 0xFFFFFFFFU 2740#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_MASK 0xFFFFFFFFU 2741#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_SHIFT 0U 2742#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_WIDTH 32U 2743#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__REG DENALI_CTL_154 2744#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__FLD LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR 2745 2746#define LPDDR4__DENALI_CTL_155_READ_MASK 0xFFFFFFFFU 2747#define LPDDR4__DENALI_CTL_155_WRITE_MASK 0xFFFFFFFFU 2748#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_MASK 0xFFFFFFFFU 2749#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_SHIFT 0U 2750#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_WIDTH 32U 2751#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__REG DENALI_CTL_155 2752#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__FLD LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0 2753 2754#define LPDDR4__DENALI_CTL_156_READ_MASK 0xFFFFFFFFU 2755#define LPDDR4__DENALI_CTL_156_WRITE_MASK 0xFFFFFFFFU 2756#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_MASK 0xFFFFFFFFU 2757#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_SHIFT 0U 2758#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_WIDTH 32U 2759#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__REG DENALI_CTL_156 2760#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__FLD LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1 2761 2762#define LPDDR4__DENALI_CTL_157_READ_MASK 0xFFFFFFFFU 2763#define LPDDR4__DENALI_CTL_157_WRITE_MASK 0xFFFFFFFFU 2764#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_MASK 0xFFFFFFFFU 2765#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_SHIFT 0U 2766#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_WIDTH 32U 2767#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__REG DENALI_CTL_157 2768#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__FLD LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2 2769 2770#define LPDDR4__DENALI_CTL_158_READ_MASK 0x00FFFF0FU 2771#define LPDDR4__DENALI_CTL_158_WRITE_MASK 0x00FFFF0FU 2772#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_MASK 0x0000000FU 2773#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_SHIFT 0U 2774#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_WIDTH 4U 2775#define LPDDR4__DFS_PHY_REG_WRITE_MASK__REG DENALI_CTL_158 2776#define LPDDR4__DFS_PHY_REG_WRITE_MASK__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK 2777 2778#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_MASK 0x00FFFF00U 2779#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_SHIFT 8U 2780#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_WIDTH 16U 2781#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__REG DENALI_CTL_158 2782#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT 2783 2784#define LPDDR4__DENALI_CTL_159_READ_MASK 0x07FFFFFFU 2785#define LPDDR4__DENALI_CTL_159_WRITE_MASK 0x07FFFFFFU 2786#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_MASK 0x07FFFFFFU 2787#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_SHIFT 0U 2788#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_WIDTH 27U 2789#define LPDDR4__WRITE_MODEREG__REG DENALI_CTL_159 2790#define LPDDR4__WRITE_MODEREG__FLD LPDDR4__DENALI_CTL_159__WRITE_MODEREG 2791 2792#define LPDDR4__DENALI_CTL_160_READ_MASK 0x01FFFFFFU 2793#define LPDDR4__DENALI_CTL_160_WRITE_MASK 0x01FFFFFFU 2794#define LPDDR4__DENALI_CTL_160__MRW_STATUS_MASK 0x000000FFU 2795#define LPDDR4__DENALI_CTL_160__MRW_STATUS_SHIFT 0U 2796#define LPDDR4__DENALI_CTL_160__MRW_STATUS_WIDTH 8U 2797#define LPDDR4__MRW_STATUS__REG DENALI_CTL_160 2798#define LPDDR4__MRW_STATUS__FLD LPDDR4__DENALI_CTL_160__MRW_STATUS 2799 2800#define LPDDR4__DENALI_CTL_160__READ_MODEREG_MASK 0x01FFFF00U 2801#define LPDDR4__DENALI_CTL_160__READ_MODEREG_SHIFT 8U 2802#define LPDDR4__DENALI_CTL_160__READ_MODEREG_WIDTH 17U 2803#define LPDDR4__READ_MODEREG__REG DENALI_CTL_160 2804#define LPDDR4__READ_MODEREG__FLD LPDDR4__DENALI_CTL_160__READ_MODEREG 2805 2806#define LPDDR4__DENALI_CTL_161_READ_MASK 0xFFFFFFFFU 2807#define LPDDR4__DENALI_CTL_161_WRITE_MASK 0xFFFFFFFFU 2808#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_MASK 0xFFFFFFFFU 2809#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_SHIFT 0U 2810#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_WIDTH 32U 2811#define LPDDR4__PERIPHERAL_MRR_DATA_0__REG DENALI_CTL_161 2812#define LPDDR4__PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0 2813 2814#define LPDDR4__DENALI_CTL_162_READ_MASK 0x00FFFFFFU 2815#define LPDDR4__DENALI_CTL_162_WRITE_MASK 0x00FFFFFFU 2816#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_MASK 0x000000FFU 2817#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_SHIFT 0U 2818#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_WIDTH 8U 2819#define LPDDR4__PERIPHERAL_MRR_DATA_1__REG DENALI_CTL_162 2820#define LPDDR4__PERIPHERAL_MRR_DATA_1__FLD LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1 2821 2822#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_MASK 0x00FFFF00U 2823#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_SHIFT 8U 2824#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_WIDTH 16U 2825#define LPDDR4__AUTO_TEMPCHK_VAL_0__REG DENALI_CTL_162 2826#define LPDDR4__AUTO_TEMPCHK_VAL_0__FLD LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0 2827 2828#define LPDDR4__DENALI_CTL_163_READ_MASK 0x0001FFFFU 2829#define LPDDR4__DENALI_CTL_163_WRITE_MASK 0x0001FFFFU 2830#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_MASK 0x0000FFFFU 2831#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_SHIFT 0U 2832#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_WIDTH 16U 2833#define LPDDR4__AUTO_TEMPCHK_VAL_1__REG DENALI_CTL_163 2834#define LPDDR4__AUTO_TEMPCHK_VAL_1__FLD LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1 2835 2836#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_MASK 0x00010000U 2837#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_SHIFT 16U 2838#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WIDTH 1U 2839#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOCLR 0U 2840#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOSET 0U 2841#define LPDDR4__DISABLE_UPDATE_TVRCG__REG DENALI_CTL_163 2842#define LPDDR4__DISABLE_UPDATE_TVRCG__FLD LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG 2843 2844#define LPDDR4__DENALI_CTL_164_READ_MASK 0x03FF0003U 2845#define LPDDR4__DENALI_CTL_164_WRITE_MASK 0x03FF0003U 2846#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_MASK 0x00000003U 2847#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_SHIFT 0U 2848#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_WIDTH 2U 2849#define LPDDR4__MRW_DFS_UPDATE_FRC__REG DENALI_CTL_164 2850#define LPDDR4__MRW_DFS_UPDATE_FRC__FLD LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC 2851 2852#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_MASK 0x03FF0000U 2853#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_SHIFT 16U 2854#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_WIDTH 10U 2855#define LPDDR4__TVRCG_ENABLE_F0__REG DENALI_CTL_164 2856#define LPDDR4__TVRCG_ENABLE_F0__FLD LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0 2857 2858#define LPDDR4__DENALI_CTL_165_READ_MASK 0x03FF03FFU 2859#define LPDDR4__DENALI_CTL_165_WRITE_MASK 0x03FF03FFU 2860#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_MASK 0x000003FFU 2861#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_SHIFT 0U 2862#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_WIDTH 10U 2863#define LPDDR4__TVRCG_DISABLE_F0__REG DENALI_CTL_165 2864#define LPDDR4__TVRCG_DISABLE_F0__FLD LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0 2865 2866#define LPDDR4__DENALI_CTL_165__TFC_F0_MASK 0x03FF0000U 2867#define LPDDR4__DENALI_CTL_165__TFC_F0_SHIFT 16U 2868#define LPDDR4__DENALI_CTL_165__TFC_F0_WIDTH 10U 2869#define LPDDR4__TFC_F0__REG DENALI_CTL_165 2870#define LPDDR4__TFC_F0__FLD LPDDR4__DENALI_CTL_165__TFC_F0 2871 2872#define LPDDR4__DENALI_CTL_166_READ_MASK 0xFFFF1F1FU 2873#define LPDDR4__DENALI_CTL_166_WRITE_MASK 0xFFFF1F1FU 2874#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_MASK 0x0000001FU 2875#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_SHIFT 0U 2876#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_WIDTH 5U 2877#define LPDDR4__TCKFSPE_F0__REG DENALI_CTL_166 2878#define LPDDR4__TCKFSPE_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPE_F0 2879 2880#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_MASK 0x00001F00U 2881#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_SHIFT 8U 2882#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_WIDTH 5U 2883#define LPDDR4__TCKFSPX_F0__REG DENALI_CTL_166 2884#define LPDDR4__TCKFSPX_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPX_F0 2885 2886#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_MASK 0xFFFF0000U 2887#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_SHIFT 16U 2888#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_WIDTH 16U 2889#define LPDDR4__TVREF_LONG_F0__REG DENALI_CTL_166 2890#define LPDDR4__TVREF_LONG_F0__FLD LPDDR4__DENALI_CTL_166__TVREF_LONG_F0 2891 2892#define LPDDR4__DENALI_CTL_167_READ_MASK 0x03FF03FFU 2893#define LPDDR4__DENALI_CTL_167_WRITE_MASK 0x03FF03FFU 2894#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_MASK 0x000003FFU 2895#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_SHIFT 0U 2896#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_WIDTH 10U 2897#define LPDDR4__TVRCG_ENABLE_F1__REG DENALI_CTL_167 2898#define LPDDR4__TVRCG_ENABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1 2899 2900#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_MASK 0x03FF0000U 2901#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_SHIFT 16U 2902#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_WIDTH 10U 2903#define LPDDR4__TVRCG_DISABLE_F1__REG DENALI_CTL_167 2904#define LPDDR4__TVRCG_DISABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1 2905 2906#define LPDDR4__DENALI_CTL_168_READ_MASK 0x1F1F03FFU 2907#define LPDDR4__DENALI_CTL_168_WRITE_MASK 0x1F1F03FFU 2908#define LPDDR4__DENALI_CTL_168__TFC_F1_MASK 0x000003FFU 2909#define LPDDR4__DENALI_CTL_168__TFC_F1_SHIFT 0U 2910#define LPDDR4__DENALI_CTL_168__TFC_F1_WIDTH 10U 2911#define LPDDR4__TFC_F1__REG DENALI_CTL_168 2912#define LPDDR4__TFC_F1__FLD LPDDR4__DENALI_CTL_168__TFC_F1 2913 2914#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_MASK 0x001F0000U 2915#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_SHIFT 16U 2916#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_WIDTH 5U 2917#define LPDDR4__TCKFSPE_F1__REG DENALI_CTL_168 2918#define LPDDR4__TCKFSPE_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPE_F1 2919 2920#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_MASK 0x1F000000U 2921#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_SHIFT 24U 2922#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_WIDTH 5U 2923#define LPDDR4__TCKFSPX_F1__REG DENALI_CTL_168 2924#define LPDDR4__TCKFSPX_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPX_F1 2925 2926#define LPDDR4__DENALI_CTL_169_READ_MASK 0x03FFFFFFU 2927#define LPDDR4__DENALI_CTL_169_WRITE_MASK 0x03FFFFFFU 2928#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_MASK 0x0000FFFFU 2929#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_SHIFT 0U 2930#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_WIDTH 16U 2931#define LPDDR4__TVREF_LONG_F1__REG DENALI_CTL_169 2932#define LPDDR4__TVREF_LONG_F1__FLD LPDDR4__DENALI_CTL_169__TVREF_LONG_F1 2933 2934#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_MASK 0x03FF0000U 2935#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_SHIFT 16U 2936#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_WIDTH 10U 2937#define LPDDR4__TVRCG_ENABLE_F2__REG DENALI_CTL_169 2938#define LPDDR4__TVRCG_ENABLE_F2__FLD LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2 2939 2940#define LPDDR4__DENALI_CTL_170_READ_MASK 0x03FF03FFU 2941#define LPDDR4__DENALI_CTL_170_WRITE_MASK 0x03FF03FFU 2942#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_MASK 0x000003FFU 2943#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_SHIFT 0U 2944#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_WIDTH 10U 2945#define LPDDR4__TVRCG_DISABLE_F2__REG DENALI_CTL_170 2946#define LPDDR4__TVRCG_DISABLE_F2__FLD LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2 2947 2948#define LPDDR4__DENALI_CTL_170__TFC_F2_MASK 0x03FF0000U 2949#define LPDDR4__DENALI_CTL_170__TFC_F2_SHIFT 16U 2950#define LPDDR4__DENALI_CTL_170__TFC_F2_WIDTH 10U 2951#define LPDDR4__TFC_F2__REG DENALI_CTL_170 2952#define LPDDR4__TFC_F2__FLD LPDDR4__DENALI_CTL_170__TFC_F2 2953 2954#define LPDDR4__DENALI_CTL_171_READ_MASK 0xFFFF1F1FU 2955#define LPDDR4__DENALI_CTL_171_WRITE_MASK 0xFFFF1F1FU 2956#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_MASK 0x0000001FU 2957#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_SHIFT 0U 2958#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_WIDTH 5U 2959#define LPDDR4__TCKFSPE_F2__REG DENALI_CTL_171 2960#define LPDDR4__TCKFSPE_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPE_F2 2961 2962#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_MASK 0x00001F00U 2963#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_SHIFT 8U 2964#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_WIDTH 5U 2965#define LPDDR4__TCKFSPX_F2__REG DENALI_CTL_171 2966#define LPDDR4__TCKFSPX_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPX_F2 2967 2968#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_MASK 0xFFFF0000U 2969#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_SHIFT 16U 2970#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_WIDTH 16U 2971#define LPDDR4__TVREF_LONG_F2__REG DENALI_CTL_171 2972#define LPDDR4__TVREF_LONG_F2__FLD LPDDR4__DENALI_CTL_171__TVREF_LONG_F2 2973 2974#define LPDDR4__DENALI_CTL_172_READ_MASK 0xFFFFFFFFU 2975#define LPDDR4__DENALI_CTL_172_WRITE_MASK 0xFFFFFFFFU 2976#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU 2977#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_SHIFT 0U 2978#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_WIDTH 16U 2979#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_172 2980#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0 2981 2982#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U 2983#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_SHIFT 16U 2984#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_WIDTH 16U 2985#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_172 2986#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1 2987 2988#define LPDDR4__DENALI_CTL_173_READ_MASK 0xFFFFFFFFU 2989#define LPDDR4__DENALI_CTL_173_WRITE_MASK 0xFFFFFFFFU 2990#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU 2991#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_SHIFT 0U 2992#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_WIDTH 16U 2993#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_173 2994#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2 2995 2996#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U 2997#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_SHIFT 16U 2998#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_WIDTH 16U 2999#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_173 3000#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0
3001 3002#define LPDDR4__DENALI_CTL_174_READ_MASK 0xFFFFFFFFU 3003#define LPDDR4__DENALI_CTL_174_WRITE_MASK 0xFFFFFFFFU 3004#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU 3005#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_SHIFT 0U 3006#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_WIDTH 16U 3007#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_174 3008#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1 3009 3010#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U 3011#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_SHIFT 16U 3012#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_WIDTH 16U 3013#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_174 3014#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2 3015 3016#define LPDDR4__DENALI_CTL_175_READ_MASK 0xFFFFFFFFU 3017#define LPDDR4__DENALI_CTL_175_WRITE_MASK 0xFFFFFFFFU 3018#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_MASK 0x000000FFU 3019#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_SHIFT 0U 3020#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_WIDTH 8U 3021#define LPDDR4__MR1_DATA_F0_0__REG DENALI_CTL_175 3022#define LPDDR4__MR1_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0 3023 3024#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_MASK 0x0000FF00U 3025#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_SHIFT 8U 3026#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_WIDTH 8U 3027#define LPDDR4__MR2_DATA_F0_0__REG DENALI_CTL_175 3028#define LPDDR4__MR2_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0 3029 3030#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_MASK 0x00FF0000U 3031#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_SHIFT 16U 3032#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_WIDTH 8U 3033#define LPDDR4__MR1_DATA_F1_0__REG DENALI_CTL_175 3034#define LPDDR4__MR1_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0 3035 3036#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_MASK 0xFF000000U 3037#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_SHIFT 24U 3038#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_WIDTH 8U 3039#define LPDDR4__MR2_DATA_F1_0__REG DENALI_CTL_175 3040#define LPDDR4__MR2_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0 3041 3042#define LPDDR4__DENALI_CTL_176_READ_MASK 0xFFFFFFFFU 3043#define LPDDR4__DENALI_CTL_176_WRITE_MASK 0xFFFFFFFFU 3044#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_MASK 0x000000FFU 3045#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_SHIFT 0U 3046#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_WIDTH 8U 3047#define LPDDR4__MR1_DATA_F2_0__REG DENALI_CTL_176 3048#define LPDDR4__MR1_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0 3049 3050#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_MASK 0x0000FF00U 3051#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_SHIFT 8U 3052#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_WIDTH 8U 3053#define LPDDR4__MR2_DATA_F2_0__REG DENALI_CTL_176 3054#define LPDDR4__MR2_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0 3055 3056#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_MASK 0x00FF0000U 3057#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_SHIFT 16U 3058#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_WIDTH 8U 3059#define LPDDR4__MRSINGLE_DATA_0__REG DENALI_CTL_176 3060#define LPDDR4__MRSINGLE_DATA_0__FLD LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0 3061 3062#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_MASK 0xFF000000U 3063#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_SHIFT 24U 3064#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_WIDTH 8U 3065#define LPDDR4__MR3_DATA_F0_0__REG DENALI_CTL_176 3066#define LPDDR4__MR3_DATA_F0_0__FLD LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0 3067 3068#define LPDDR4__DENALI_CTL_177_READ_MASK 0xFFFFFFFFU 3069#define LPDDR4__DENALI_CTL_177_WRITE_MASK 0xFFFFFFFFU 3070#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_MASK 0x000000FFU 3071#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_SHIFT 0U 3072#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_WIDTH 8U 3073#define LPDDR4__MR3_DATA_F1_0__REG DENALI_CTL_177 3074#define LPDDR4__MR3_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0 3075 3076#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_MASK 0x0000FF00U 3077#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_SHIFT 8U 3078#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_WIDTH 8U 3079#define LPDDR4__MR3_DATA_F2_0__REG DENALI_CTL_177 3080#define LPDDR4__MR3_DATA_F2_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0 3081 3082#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_MASK 0x00FF0000U 3083#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_SHIFT 16U 3084#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_WIDTH 8U 3085#define LPDDR4__MR4_DATA_F0_0__REG DENALI_CTL_177 3086#define LPDDR4__MR4_DATA_F0_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0 3087 3088#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_MASK 0xFF000000U 3089#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_SHIFT 24U 3090#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_WIDTH 8U 3091#define LPDDR4__MR4_DATA_F1_0__REG DENALI_CTL_177 3092#define LPDDR4__MR4_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0 3093 3094#define LPDDR4__DENALI_CTL_178_READ_MASK 0xFFFFFFFFU 3095#define LPDDR4__DENALI_CTL_178_WRITE_MASK 0xFFFFFFFFU 3096#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_MASK 0x000000FFU 3097#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_SHIFT 0U 3098#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_WIDTH 8U 3099#define LPDDR4__MR4_DATA_F2_0__REG DENALI_CTL_178 3100#define LPDDR4__MR4_DATA_F2_0__FLD LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0 3101 3102#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_MASK 0x0000FF00U 3103#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_SHIFT 8U 3104#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_WIDTH 8U 3105#define LPDDR4__MR8_DATA_0__REG DENALI_CTL_178 3106#define LPDDR4__MR8_DATA_0__FLD LPDDR4__DENALI_CTL_178__MR8_DATA_0 3107 3108#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_MASK 0x00FF0000U 3109#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_SHIFT 16U 3110#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_WIDTH 8U 3111#define LPDDR4__MR11_DATA_F0_0__REG DENALI_CTL_178 3112#define LPDDR4__MR11_DATA_F0_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0 3113 3114#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_MASK 0xFF000000U 3115#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_SHIFT 24U 3116#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_WIDTH 8U 3117#define LPDDR4__MR11_DATA_F1_0__REG DENALI_CTL_178 3118#define LPDDR4__MR11_DATA_F1_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0 3119 3120#define LPDDR4__DENALI_CTL_179_READ_MASK 0xFFFFFFFFU 3121#define LPDDR4__DENALI_CTL_179_WRITE_MASK 0xFFFFFFFFU 3122#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_MASK 0x000000FFU 3123#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_SHIFT 0U 3124#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_WIDTH 8U 3125#define LPDDR4__MR11_DATA_F2_0__REG DENALI_CTL_179 3126#define LPDDR4__MR11_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0 3127 3128#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_MASK 0x0000FF00U 3129#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_SHIFT 8U 3130#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_WIDTH 8U 3131#define LPDDR4__MR12_DATA_F0_0__REG DENALI_CTL_179 3132#define LPDDR4__MR12_DATA_F0_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0 3133 3134#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_MASK 0x00FF0000U 3135#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_SHIFT 16U 3136#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_WIDTH 8U 3137#define LPDDR4__MR12_DATA_F1_0__REG DENALI_CTL_179 3138#define LPDDR4__MR12_DATA_F1_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0 3139 3140#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_MASK 0xFF000000U 3141#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_SHIFT 24U 3142#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_WIDTH 8U 3143#define LPDDR4__MR12_DATA_F2_0__REG DENALI_CTL_179 3144#define LPDDR4__MR12_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0 3145 3146#define LPDDR4__DENALI_CTL_180_READ_MASK 0xFFFFFFFFU 3147#define LPDDR4__DENALI_CTL_180_WRITE_MASK 0xFFFFFFFFU 3148#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_MASK 0x000000FFU 3149#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_SHIFT 0U 3150#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_WIDTH 8U 3151#define LPDDR4__MR13_DATA_0__REG DENALI_CTL_180 3152#define LPDDR4__MR13_DATA_0__FLD LPDDR4__DENALI_CTL_180__MR13_DATA_0 3153 3154#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_MASK 0x0000FF00U 3155#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_SHIFT 8U 3156#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_WIDTH 8U 3157#define LPDDR4__MR14_DATA_F0_0__REG DENALI_CTL_180 3158#define LPDDR4__MR14_DATA_F0_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0 3159 3160#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_MASK 0x00FF0000U 3161#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_SHIFT 16U 3162#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_WIDTH 8U 3163#define LPDDR4__MR14_DATA_F1_0__REG DENALI_CTL_180 3164#define LPDDR4__MR14_DATA_F1_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0 3165 3166#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_MASK 0xFF000000U 3167#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_SHIFT 24U 3168#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_WIDTH 8U 3169#define LPDDR4__MR14_DATA_F2_0__REG DENALI_CTL_180 3170#define LPDDR4__MR14_DATA_F2_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0 3171 3172#define LPDDR4__DENALI_CTL_181_READ_MASK 0xFFFFFFFFU 3173#define LPDDR4__DENALI_CTL_181_WRITE_MASK 0xFFFFFFFFU 3174#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_MASK 0x000000FFU 3175#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_SHIFT 0U 3176#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_WIDTH 8U 3177#define LPDDR4__MR16_DATA_0__REG DENALI_CTL_181 3178#define LPDDR4__MR16_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR16_DATA_0 3179 3180#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_MASK 0x0000FF00U 3181#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_SHIFT 8U 3182#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_WIDTH 8U 3183#define LPDDR4__MR17_DATA_0__REG DENALI_CTL_181 3184#define LPDDR4__MR17_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR17_DATA_0 3185 3186#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_MASK 0x00FF0000U 3187#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_SHIFT 16U 3188#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_WIDTH 8U 3189#define LPDDR4__MR20_DATA_0__REG DENALI_CTL_181 3190#define LPDDR4__MR20_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR20_DATA_0 3191 3192#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_MASK 0xFF000000U 3193#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_SHIFT 24U 3194#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_WIDTH 8U 3195#define LPDDR4__MR22_DATA_F0_0__REG DENALI_CTL_181 3196#define LPDDR4__MR22_DATA_F0_0__FLD LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0 3197 3198#define LPDDR4__DENALI_CTL_182_READ_MASK 0xFFFFFFFFU 3199#define LPDDR4__DENALI_CTL_182_WRITE_MASK 0xFFFFFFFFU 3200#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_MASK 0x000000FFU 3201#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_SHIFT 0U 3202#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_WIDTH 8U 3203#define LPDDR4__MR22_DATA_F1_0__REG DENALI_CTL_182 3204#define LPDDR4__MR22_DATA_F1_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0 3205 3206#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_MASK 0x0000FF00U 3207#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_SHIFT 8U 3208#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_WIDTH 8U 3209#define LPDDR4__MR22_DATA_F2_0__REG DENALI_CTL_182 3210#define LPDDR4__MR22_DATA_F2_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0 3211 3212#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_MASK 0x00FF0000U 3213#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_SHIFT 16U 3214#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_WIDTH 8U 3215#define LPDDR4__MR1_DATA_F0_1__REG DENALI_CTL_182 3216#define LPDDR4__MR1_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1 3217 3218#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_MASK 0xFF000000U 3219#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_SHIFT 24U 3220#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_WIDTH 8U 3221#define LPDDR4__MR2_DATA_F0_1__REG DENALI_CTL_182 3222#define LPDDR4__MR2_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1 3223 3224#define LPDDR4__DENALI_CTL_183_READ_MASK 0xFFFFFFFFU 3225#define LPDDR4__DENALI_CTL_183_WRITE_MASK 0xFFFFFFFFU 3226#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_MASK 0x000000FFU 3227#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_SHIFT 0U 3228#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_WIDTH 8U 3229#define LPDDR4__MR1_DATA_F1_1__REG DENALI_CTL_183 3230#define LPDDR4__MR1_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1 3231 3232#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_MASK 0x0000FF00U 3233#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_SHIFT 8U 3234#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_WIDTH 8U 3235#define LPDDR4__MR2_DATA_F1_1__REG DENALI_CTL_183 3236#define LPDDR4__MR2_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1 3237 3238#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_MASK 0x00FF0000U 3239#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_SHIFT 16U 3240#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_WIDTH 8U 3241#define LPDDR4__MR1_DATA_F2_1__REG DENALI_CTL_183 3242#define LPDDR4__MR1_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1 3243 3244#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_MASK 0xFF000000U 3245#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_SHIFT 24U 3246#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_WIDTH 8U 3247#define LPDDR4__MR2_DATA_F2_1__REG DENALI_CTL_183 3248#define LPDDR4__MR2_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1 3249 3250#define LPDDR4__DENALI_CTL_184_READ_MASK 0xFFFFFFFFU 3251#define LPDDR4__DENALI_CTL_184_WRITE_MASK 0xFFFFFFFFU 3252#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_MASK 0x000000FFU 3253#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_SHIFT 0U 3254#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_WIDTH 8U 3255#define LPDDR4__MRSINGLE_DATA_1__REG DENALI_CTL_184 3256#define LPDDR4__MRSINGLE_DATA_1__FLD LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1 3257 3258#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_MASK 0x0000FF00U 3259#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_SHIFT 8U 3260#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_WIDTH 8U 3261#define LPDDR4__MR3_DATA_F0_1__REG DENALI_CTL_184 3262#define LPDDR4__MR3_DATA_F0_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1 3263 3264#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_MASK 0x00FF0000U 3265#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_SHIFT 16U 3266#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_WIDTH 8U 3267#define LPDDR4__MR3_DATA_F1_1__REG DENALI_CTL_184 3268#define LPDDR4__MR3_DATA_F1_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1 3269 3270#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_MASK 0xFF000000U 3271#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_SHIFT 24U 3272#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_WIDTH 8U 3273#define LPDDR4__MR3_DATA_F2_1__REG DENALI_CTL_184 3274#define LPDDR4__MR3_DATA_F2_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1 3275 3276#define LPDDR4__DENALI_CTL_185_READ_MASK 0xFFFFFFFFU 3277#define LPDDR4__DENALI_CTL_185_WRITE_MASK 0xFFFFFFFFU 3278#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_MASK 0x000000FFU 3279#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_SHIFT 0U 3280#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_WIDTH 8U 3281#define LPDDR4__MR4_DATA_F0_1__REG DENALI_CTL_185 3282#define LPDDR4__MR4_DATA_F0_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1 3283 3284#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_MASK 0x0000FF00U 3285#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_SHIFT 8U 3286#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_WIDTH 8U 3287#define LPDDR4__MR4_DATA_F1_1__REG DENALI_CTL_185 3288#define LPDDR4__MR4_DATA_F1_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1 3289 3290#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_MASK 0x00FF0000U 3291#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_SHIFT 16U 3292#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_WIDTH 8U 3293#define LPDDR4__MR4_DATA_F2_1__REG DENALI_CTL_185 3294#define LPDDR4__MR4_DATA_F2_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1 3295 3296#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_MASK 0xFF000000U 3297#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_SHIFT 24U 3298#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_WIDTH 8U 3299#define LPDDR4__MR8_DATA_1__REG DENALI_CTL_185 3300#define LPDDR4__MR8_DATA_1__FLD LPDDR4__DENALI_CTL_185__MR8_DATA_1 3301 3302#define LPDDR4__DENALI_CTL_186_READ_MASK 0xFFFFFFFFU 3303#define LPDDR4__DENALI_CTL_186_WRITE_MASK 0xFFFFFFFFU 3304#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_MASK 0x000000FFU 3305#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_SHIFT 0U 3306#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_WIDTH 8U 3307#define LPDDR4__MR11_DATA_F0_1__REG DENALI_CTL_186 3308#define LPDDR4__MR11_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1 3309 3310#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_MASK 0x0000FF00U 3311#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_SHIFT 8U 3312#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_WIDTH 8U 3313#define LPDDR4__MR11_DATA_F1_1__REG DENALI_CTL_186 3314#define LPDDR4__MR11_DATA_F1_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1 3315 3316#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_MASK 0x00FF0000U 3317#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_SHIFT 16U 3318#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_WIDTH 8U 3319#define LPDDR4__MR11_DATA_F2_1__REG DENALI_CTL_186 3320#define LPDDR4__MR11_DATA_F2_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1 3321 3322#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_MASK 0xFF000000U 3323#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_SHIFT 24U 3324#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_WIDTH 8U 3325#define LPDDR4__MR12_DATA_F0_1__REG DENALI_CTL_186 3326#define LPDDR4__MR12_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1 3327 3328#define LPDDR4__DENALI_CTL_187_READ_MASK 0xFFFFFFFFU 3329#define LPDDR4__DENALI_CTL_187_WRITE_MASK 0xFFFFFFFFU 3330#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_MASK 0x000000FFU 3331#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_SHIFT 0U 3332#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_WIDTH 8U 3333#define LPDDR4__MR12_DATA_F1_1__REG DENALI_CTL_187 3334#define LPDDR4__MR12_DATA_F1_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1 3335 3336#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_MASK 0x0000FF00U 3337#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_SHIFT 8U 3338#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_WIDTH 8U 3339#define LPDDR4__MR12_DATA_F2_1__REG DENALI_CTL_187 3340#define LPDDR4__MR12_DATA_F2_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1 3341 3342#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_MASK 0x00FF0000U 3343#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_SHIFT 16U 3344#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_WIDTH 8U 3345#define LPDDR4__MR13_DATA_1__REG DENALI_CTL_187 3346#define LPDDR4__MR13_DATA_1__FLD LPDDR4__DENALI_CTL_187__MR13_DATA_1 3347 3348#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_MASK 0xFF000000U 3349#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_SHIFT 24U 3350#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_WIDTH 8U 3351#define LPDDR4__MR14_DATA_F0_1__REG DENALI_CTL_187 3352#define LPDDR4__MR14_DATA_F0_1__FLD LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1 3353 3354#define LPDDR4__DENALI_CTL_188_READ_MASK 0xFFFFFFFFU 3355#define LPDDR4__DENALI_CTL_188_WRITE_MASK 0xFFFFFFFFU 3356#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_MASK 0x000000FFU 3357#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_SHIFT 0U 3358#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_WIDTH 8U 3359#define LPDDR4__MR14_DATA_F1_1__REG DENALI_CTL_188 3360#define LPDDR4__MR14_DATA_F1_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1 3361 3362#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_MASK 0x0000FF00U 3363#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_SHIFT 8U 3364#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_WIDTH 8U 3365#define LPDDR4__MR14_DATA_F2_1__REG DENALI_CTL_188 3366#define LPDDR4__MR14_DATA_F2_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1 3367 3368#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_MASK 0x00FF0000U 3369#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_SHIFT 16U 3370#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_WIDTH 8U 3371#define LPDDR4__MR16_DATA_1__REG DENALI_CTL_188 3372#define LPDDR4__MR16_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR16_DATA_1 3373 3374#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_MASK 0xFF000000U 3375#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_SHIFT 24U 3376#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_WIDTH 8U 3377#define LPDDR4__MR17_DATA_1__REG DENALI_CTL_188 3378#define LPDDR4__MR17_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR17_DATA_1 3379 3380#define LPDDR4__DENALI_CTL_189_READ_MASK 0xFFFFFFFFU 3381#define LPDDR4__DENALI_CTL_189_WRITE_MASK 0xFFFFFFFFU 3382#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_MASK 0x000000FFU 3383#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_SHIFT 0U 3384#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_WIDTH 8U 3385#define LPDDR4__MR20_DATA_1__REG DENALI_CTL_189 3386#define LPDDR4__MR20_DATA_1__FLD LPDDR4__DENALI_CTL_189__MR20_DATA_1 3387 3388#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_MASK 0x0000FF00U 3389#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_SHIFT 8U 3390#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_WIDTH 8U 3391#define LPDDR4__MR22_DATA_F0_1__REG DENALI_CTL_189 3392#define LPDDR4__MR22_DATA_F0_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1 3393 3394#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_MASK 0x00FF0000U 3395#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_SHIFT 16U 3396#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_WIDTH 8U 3397#define LPDDR4__MR22_DATA_F1_1__REG DENALI_CTL_189 3398#define LPDDR4__MR22_DATA_F1_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1 3399 3400#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_MASK 0xFF000000U 3401#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_SHIFT 24U 3402#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_WIDTH 8U 3403#define LPDDR4__MR22_DATA_F2_1__REG DENALI_CTL_189 3404#define LPDDR4__MR22_DATA_F2_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1 3405 3406#define LPDDR4__DENALI_CTL_190_READ_MASK 0x010101FFU 3407#define LPDDR4__DENALI_CTL_190_WRITE_MASK 0x010101FFU 3408#define LPDDR4__DENALI_CTL_190__MR23_DATA_MASK 0x000000FFU 3409#define LPDDR4__DENALI_CTL_190__MR23_DATA_SHIFT 0U 3410#define LPDDR4__DENALI_CTL_190__MR23_DATA_WIDTH 8U 3411#define LPDDR4__MR23_DATA__REG DENALI_CTL_190 3412#define LPDDR4__MR23_DATA__FLD LPDDR4__DENALI_CTL_190__MR23_DATA 3413 3414#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_MASK 0x00000100U 3415#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_SHIFT 8U 3416#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WIDTH 1U 3417#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOCLR 0U 3418#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOSET 0U 3419#define LPDDR4__MR_FSP_DATA_VALID_F0__REG DENALI_CTL_190 3420#define LPDDR4__MR_FSP_DATA_VALID_F0__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0 3421 3422#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_MASK 0x00010000U 3423#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_SHIFT 16U 3424#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WIDTH 1U 3425#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOCLR 0U 3426#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOSET 0U 3427#define LPDDR4__MR_FSP_DATA_VALID_F1__REG DENALI_CTL_190 3428#define LPDDR4__MR_FSP_DATA_VALID_F1__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1 3429 3430#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_MASK 0x01000000U 3431#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_SHIFT 24U 3432#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WIDTH 1U 3433#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOCLR 0U 3434#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOSET 0U 3435#define LPDDR4__MR_FSP_DATA_VALID_F2__REG DENALI_CTL_190 3436#define LPDDR4__MR_FSP_DATA_VALID_F2__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2 3437 3438#define LPDDR4__DENALI_CTL_191_READ_MASK 0x01010103U 3439#define LPDDR4__DENALI_CTL_191_WRITE_MASK 0x01010103U 3440#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_MASK 0x00000003U 3441#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_SHIFT 0U 3442#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_WIDTH 2U 3443#define LPDDR4__RL3_SUPPORT_EN__REG DENALI_CTL_191 3444#define LPDDR4__RL3_SUPPORT_EN__FLD LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN 3445 3446#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_MASK 0x00000100U 3447#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_SHIFT 8U 3448#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WIDTH 1U 3449#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOCLR 0U 3450#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOSET 0U 3451#define LPDDR4__MC_RESERVED19__REG DENALI_CTL_191 3452#define LPDDR4__MC_RESERVED19__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED19 3453 3454#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_MASK 0x00010000U 3455#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_SHIFT 16U 3456#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WIDTH 1U 3457#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOCLR 0U 3458#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOSET 0U 3459#define LPDDR4__MC_RESERVED20__REG DENALI_CTL_191 3460#define LPDDR4__MC_RESERVED20__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED20 3461 3462#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_MASK 0x01000000U 3463#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_SHIFT 24U 3464#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WIDTH 1U 3465#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOCLR 0U 3466#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOSET 0U 3467#define LPDDR4__FSP_PHY_UPDATE_MRW__REG DENALI_CTL_191 3468#define LPDDR4__FSP_PHY_UPDATE_MRW__FLD LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW 3469 3470#define LPDDR4__DENALI_CTL_192_READ_MASK 0x01010101U 3471#define LPDDR4__DENALI_CTL_192_WRITE_MASK 0x01010101U 3472#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_MASK 0x00000001U 3473#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_SHIFT 0U 3474#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WIDTH 1U 3475#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOCLR 0U 3476#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOSET 0U 3477#define LPDDR4__DFS_ALWAYS_WRITE_FSP__REG DENALI_CTL_192 3478#define LPDDR4__DFS_ALWAYS_WRITE_FSP__FLD LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP 3479 3480#define LPDDR4__DENALI_CTL_192__FSP_STATUS_MASK 0x00000100U 3481#define LPDDR4__DENALI_CTL_192__FSP_STATUS_SHIFT 8U 3482#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WIDTH 1U 3483#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOCLR 0U 3484#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOSET 0U 3485#define LPDDR4__FSP_STATUS__REG DENALI_CTL_192 3486#define LPDDR4__FSP_STATUS__FLD LPDDR4__DENALI_CTL_192__FSP_STATUS 3487 3488#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_MASK 0x00010000U 3489#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_SHIFT 16U 3490#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WIDTH 1U 3491#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOCLR 0U 3492#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOSET 0U 3493#define LPDDR4__FSP_OP_CURRENT__REG DENALI_CTL_192 3494#define LPDDR4__FSP_OP_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT 3495 3496#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_MASK 0x01000000U 3497#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_SHIFT 24U 3498#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WIDTH 1U 3499#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOCLR 0U 3500#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOSET 0U 3501#define LPDDR4__FSP_WR_CURRENT__REG DENALI_CTL_192 3502#define LPDDR4__FSP_WR_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT 3503 3504#define LPDDR4__DENALI_CTL_193_READ_MASK 0x03030101U 3505#define LPDDR4__DENALI_CTL_193_WRITE_MASK 0x03030101U 3506#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_MASK 0x00000001U 3507#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_SHIFT 0U 3508#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WIDTH 1U 3509#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOCLR 0U 3510#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOSET 0U 3511#define LPDDR4__FSP0_FRC_VALID__REG DENALI_CTL_193 3512#define LPDDR4__FSP0_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID 3513 3514#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_MASK 0x00000100U 3515#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_SHIFT 8U 3516#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WIDTH 1U 3517#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOCLR 0U 3518#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOSET 0U 3519#define LPDDR4__FSP1_FRC_VALID__REG DENALI_CTL_193 3520#define LPDDR4__FSP1_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID 3521 3522#define LPDDR4__DENALI_CTL_193__FSP0_FRC_MASK 0x00030000U 3523#define LPDDR4__DENALI_CTL_193__FSP0_FRC_SHIFT 16U 3524#define LPDDR4__DENALI_CTL_193__FSP0_FRC_WIDTH 2U 3525#define LPDDR4__FSP0_FRC__REG DENALI_CTL_193 3526#define LPDDR4__FSP0_FRC__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC 3527 3528#define LPDDR4__DENALI_CTL_193__FSP1_FRC_MASK 0x03000000U 3529#define LPDDR4__DENALI_CTL_193__FSP1_FRC_SHIFT 24U 3530#define LPDDR4__DENALI_CTL_193__FSP1_FRC_WIDTH 2U 3531#define LPDDR4__FSP1_FRC__REG DENALI_CTL_193 3532#define LPDDR4__FSP1_FRC__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC 3533 3534#define LPDDR4__DENALI_CTL_194_READ_MASK 0x013F0300U 3535#define LPDDR4__DENALI_CTL_194_WRITE_MASK 0x013F0300U 3536#define LPDDR4__DENALI_CTL_194__BIST_GO_MASK 0x00000001U 3537#define LPDDR4__DENALI_CTL_194__BIST_GO_SHIFT 0U 3538#define LPDDR4__DENALI_CTL_194__BIST_GO_WIDTH 1U 3539#define LPDDR4__DENALI_CTL_194__BIST_GO_WOCLR 0U 3540#define LPDDR4__DENALI_CTL_194__BIST_GO_WOSET 0U 3541#define LPDDR4__BIST_GO__REG DENALI_CTL_194 3542#define LPDDR4__BIST_GO__FLD LPDDR4__DENALI_CTL_194__BIST_GO 3543 3544#define LPDDR4__DENALI_CTL_194__BIST_RESULT_MASK 0x00000300U 3545#define LPDDR4__DENALI_CTL_194__BIST_RESULT_SHIFT 8U 3546#define LPDDR4__DENALI_CTL_194__BIST_RESULT_WIDTH 2U 3547#define LPDDR4__BIST_RESULT__REG DENALI_CTL_194 3548#define LPDDR4__BIST_RESULT__FLD LPDDR4__DENALI_CTL_194__BIST_RESULT 3549 3550#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_MASK 0x003F0000U 3551#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_SHIFT 16U 3552#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_WIDTH 6U 3553#define LPDDR4__ADDR_SPACE__REG DENALI_CTL_194 3554#define LPDDR4__ADDR_SPACE__FLD LPDDR4__DENALI_CTL_194__ADDR_SPACE 3555 3556#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_MASK 0x01000000U 3557#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_SHIFT 24U 3558#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WIDTH 1U 3559#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOCLR 0U 3560#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOSET 0U 3561#define LPDDR4__BIST_DATA_CHECK__REG DENALI_CTL_194 3562#define LPDDR4__BIST_DATA_CHECK__FLD LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK 3563 3564#define LPDDR4__DENALI_CTL_195_READ_MASK 0x00000001U 3565#define LPDDR4__DENALI_CTL_195_WRITE_MASK 0x00000001U 3566#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_MASK 0x00000001U 3567#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_SHIFT 0U 3568#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WIDTH 1U 3569#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOCLR 0U 3570#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOSET 0U 3571#define LPDDR4__BIST_ADDR_CHECK__REG DENALI_CTL_195 3572#define LPDDR4__BIST_ADDR_CHECK__FLD LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK 3573 3574#define LPDDR4__DENALI_CTL_196_READ_MASK 0xFFFFFFFFU 3575#define LPDDR4__DENALI_CTL_196_WRITE_MASK 0xFFFFFFFFU 3576#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU 3577#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_SHIFT 0U 3578#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_WIDTH 32U 3579#define LPDDR4__BIST_START_ADDRESS_0__REG DENALI_CTL_196 3580#define LPDDR4__BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0 3581 3582#define LPDDR4__DENALI_CTL_197_READ_MASK 0x00000007U 3583#define LPDDR4__DENALI_CTL_197_WRITE_MASK 0x00000007U 3584#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_MASK 0x00000007U 3585#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_SHIFT 0U 3586#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_WIDTH 3U 3587#define LPDDR4__BIST_START_ADDRESS_1__REG DENALI_CTL_197 3588#define LPDDR4__BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1 3589 3590#define LPDDR4__DENALI_CTL_198_READ_MASK 0xFFFFFFFFU 3591#define LPDDR4__DENALI_CTL_198_WRITE_MASK 0xFFFFFFFFU 3592#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_MASK 0xFFFFFFFFU 3593#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_SHIFT 0U 3594#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_WIDTH 32U 3595#define LPDDR4__BIST_DATA_MASK_0__REG DENALI_CTL_198 3596#define LPDDR4__BIST_DATA_MASK_0__FLD LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0 3597 3598#define LPDDR4__DENALI_CTL_199_READ_MASK 0xFFFFFFFFU 3599#define LPDDR4__DENALI_CTL_199_WRITE_MASK 0xFFFFFFFFU 3600#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_MASK 0xFFFFFFFFU 3601#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_SHIFT 0U 3602#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_WIDTH 32U 3603#define LPDDR4__BIST_DATA_MASK_1__REG DENALI_CTL_199 3604#define LPDDR4__BIST_DATA_MASK_1__FLD LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1 3605 3606#define LPDDR4__DENALI_CTL_200_READ_MASK 0x00000007U 3607#define LPDDR4__DENALI_CTL_200_WRITE_MASK 0x00000007U 3608#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_MASK 0x00000007U 3609#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_SHIFT 0U 3610#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_WIDTH 3U 3611#define LPDDR4__BIST_TEST_MODE__REG DENALI_CTL_200 3612#define LPDDR4__BIST_TEST_MODE__FLD LPDDR4__DENALI_CTL_200__BIST_TEST_MODE 3613 3614#define LPDDR4__DENALI_CTL_201_READ_MASK 0xFFFFFFFFU 3615#define LPDDR4__DENALI_CTL_201_WRITE_MASK 0xFFFFFFFFU 3616#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_MASK 0xFFFFFFFFU 3617#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_SHIFT 0U 3618#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_WIDTH 32U 3619#define LPDDR4__BIST_DATA_PATTERN_0__REG DENALI_CTL_201 3620#define LPDDR4__BIST_DATA_PATTERN_0__FLD LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0 3621 3622#define LPDDR4__DENALI_CTL_202_READ_MASK 0xFFFFFFFFU 3623#define LPDDR4__DENALI_CTL_202_WRITE_MASK 0xFFFFFFFFU 3624#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_MASK 0xFFFFFFFFU 3625#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_SHIFT 0U 3626#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_WIDTH 32U 3627#define LPDDR4__BIST_DATA_PATTERN_1__REG DENALI_CTL_202 3628#define LPDDR4__BIST_DATA_PATTERN_1__FLD LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1 3629 3630#define LPDDR4__DENALI_CTL_203_READ_MASK 0xFFFFFFFFU 3631#define LPDDR4__DENALI_CTL_203_WRITE_MASK 0xFFFFFFFFU 3632#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_MASK 0xFFFFFFFFU 3633#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_SHIFT 0U 3634#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_WIDTH 32U 3635#define LPDDR4__BIST_DATA_PATTERN_2__REG DENALI_CTL_203 3636#define LPDDR4__BIST_DATA_PATTERN_2__FLD LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2 3637 3638#define LPDDR4__DENALI_CTL_204_READ_MASK 0xFFFFFFFFU 3639#define LPDDR4__DENALI_CTL_204_WRITE_MASK 0xFFFFFFFFU 3640#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_MASK 0xFFFFFFFFU 3641#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_SHIFT 0U 3642#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_WIDTH 32U 3643#define LPDDR4__BIST_DATA_PATTERN_3__REG DENALI_CTL_204 3644#define LPDDR4__BIST_DATA_PATTERN_3__FLD LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3 3645 3646#define LPDDR4__DENALI_CTL_205_READ_MASK 0x0FFF0100U 3647#define LPDDR4__DENALI_CTL_205_WRITE_MASK 0x0FFF0100U 3648#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_MASK 0x00000001U 3649#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_SHIFT 0U 3650#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WIDTH 1U 3651#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOCLR 0U 3652#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOSET 0U 3653#define LPDDR4__BIST_RET_STATE_EXIT__REG DENALI_CTL_205 3654#define LPDDR4__BIST_RET_STATE_EXIT__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT 3655 3656#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_MASK 0x00000100U 3657#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_SHIFT 8U 3658#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WIDTH 1U 3659#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOCLR 0U 3660#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOSET 0U 3661#define LPDDR4__BIST_RET_STATE__REG DENALI_CTL_205 3662#define LPDDR4__BIST_RET_STATE__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE 3663 3664#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_MASK 0x0FFF0000U 3665#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_SHIFT 16U 3666#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_WIDTH 12U 3667#define LPDDR4__BIST_ERR_STOP__REG DENALI_CTL_205 3668#define LPDDR4__BIST_ERR_STOP__FLD LPDDR4__DENALI_CTL_205__BIST_ERR_STOP 3669 3670#define LPDDR4__DENALI_CTL_206_READ_MASK 0x07030FFFU 3671#define LPDDR4__DENALI_CTL_206_WRITE_MASK 0x07030FFFU 3672#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_MASK 0x00000FFFU 3673#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_SHIFT 0U 3674#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_WIDTH 12U 3675#define LPDDR4__BIST_ERR_COUNT__REG DENALI_CTL_206 3676#define LPDDR4__BIST_ERR_COUNT__FLD LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT 3677 3678#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_MASK 0x00030000U 3679#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_SHIFT 16U 3680#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_WIDTH 2U 3681#define LPDDR4__ECC_ENABLE__REG DENALI_CTL_206 3682#define LPDDR4__ECC_ENABLE__FLD LPDDR4__DENALI_CTL_206__ECC_ENABLE 3683 3684#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_MASK 0x07000000U 3685#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_SHIFT 24U 3686#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_WIDTH 3U 3687#define LPDDR4__INLINE_ECC_BANK_OFFSET__REG DENALI_CTL_206 3688#define LPDDR4__INLINE_ECC_BANK_OFFSET__FLD LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET 3689 3690#define LPDDR4__DENALI_CTL_207_READ_MASK 0x010F0101U 3691#define LPDDR4__DENALI_CTL_207_WRITE_MASK 0x010F0101U 3692#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_MASK 0x00000001U 3693#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_SHIFT 0U 3694#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WIDTH 1U 3695#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOCLR 0U 3696#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOSET 0U 3697#define LPDDR4__ECC_READ_CACHING_EN__REG DENALI_CTL_207 3698#define LPDDR4__ECC_READ_CACHING_EN__FLD LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN 3699 3700#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_MASK 0x00000100U 3701#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_SHIFT 8U 3702#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WIDTH 1U 3703#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOCLR 0U 3704#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOSET 0U 3705#define LPDDR4__ECC_WRITE_COMBINING_EN__REG DENALI_CTL_207 3706#define LPDDR4__ECC_WRITE_COMBINING_EN__FLD LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN 3707 3708#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_MASK 0x000F0000U 3709#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_SHIFT 16U 3710#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_WIDTH 4U 3711#define LPDDR4__MC_RESERVED21__REG DENALI_CTL_207 3712#define LPDDR4__MC_RESERVED21__FLD LPDDR4__DENALI_CTL_207__MC_RESERVED21 3713 3714#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_MASK 0x01000000U 3715#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_SHIFT 24U 3716#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WIDTH 1U 3717#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOCLR 0U 3718#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOSET 0U 3719#define LPDDR4__MC_RESERVED22__REG DENALI_CTL_207 3720#define LPDDR4__MC_RESERVED22__FLD LPDDR4__DENALI_CTL_207__MC_RESERVED22 3721 3722#define LPDDR4__DENALI_CTL_208_READ_MASK 0x01FFFF01U 3723#define LPDDR4__DENALI_CTL_208_WRITE_MASK 0x01FFFF01U 3724#define LPDDR4__DENALI_CTL_208__FWC_MASK 0x00000001U 3725#define LPDDR4__DENALI_CTL_208__FWC_SHIFT 0U 3726#define LPDDR4__DENALI_CTL_208__FWC_WIDTH 1U 3727#define LPDDR4__DENALI_CTL_208__FWC_WOCLR 0U 3728#define LPDDR4__DENALI_CTL_208__FWC_WOSET 0U 3729#define LPDDR4__FWC__REG DENALI_CTL_208 3730#define LPDDR4__FWC__FLD LPDDR4__DENALI_CTL_208__FWC 3731 3732#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_MASK 0x00FFFF00U 3733#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_SHIFT 8U 3734#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_WIDTH 16U 3735#define LPDDR4__XOR_CHECK_BITS__REG DENALI_CTL_208 3736#define LPDDR4__XOR_CHECK_BITS__FLD LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS 3737 3738#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_MASK 0x01000000U 3739#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_SHIFT 24U 3740#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WIDTH 1U 3741#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOCLR 0U 3742#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOSET 0U 3743#define LPDDR4__ECC_WRITEBACK_EN__REG DENALI_CTL_208 3744#define LPDDR4__ECC_WRITEBACK_EN__FLD LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN 3745 3746#define LPDDR4__DENALI_CTL_209_READ_MASK 0x00000001U 3747#define LPDDR4__DENALI_CTL_209_WRITE_MASK 0x00000001U 3748#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_MASK 0x00000001U 3749#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_SHIFT 0U 3750#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WIDTH 1U 3751#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOCLR 0U 3752#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOSET 0U 3753#define LPDDR4__ECC_DISABLE_W_UC_ERR__REG DENALI_CTL_209 3754#define LPDDR4__ECC_DISABLE_W_UC_ERR__FLD LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR 3755 3756#define LPDDR4__DENALI_CTL_210_READ_MASK 0xFFFFFFFFU 3757#define LPDDR4__DENALI_CTL_210_WRITE_MASK 0xFFFFFFFFU 3758#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_MASK 0xFFFFFFFFU 3759#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_SHIFT 0U 3760#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_WIDTH 32U 3761#define LPDDR4__ECC_U_ADDR_0__REG DENALI_CTL_210 3762#define LPDDR4__ECC_U_ADDR_0__FLD LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0 3763 3764#define LPDDR4__DENALI_CTL_211_READ_MASK 0x0000FF07U 3765#define LPDDR4__DENALI_CTL_211_WRITE_MASK 0x0000FF07U 3766#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_MASK 0x00000007U 3767#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_SHIFT 0U 3768#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_WIDTH 3U 3769#define LPDDR4__ECC_U_ADDR_1__REG DENALI_CTL_211 3770#define LPDDR4__ECC_U_ADDR_1__FLD LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1 3771 3772#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_MASK 0x0000FF00U 3773#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_SHIFT 8U 3774#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_WIDTH 8U 3775#define LPDDR4__ECC_U_SYND__REG DENALI_CTL_211 3776#define LPDDR4__ECC_U_SYND__FLD LPDDR4__DENALI_CTL_211__ECC_U_SYND 3777 3778#define LPDDR4__DENALI_CTL_212_READ_MASK 0xFFFFFFFFU 3779#define LPDDR4__DENALI_CTL_212_WRITE_MASK 0xFFFFFFFFU 3780#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_MASK 0xFFFFFFFFU 3781#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_SHIFT 0U 3782#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_WIDTH 32U 3783#define LPDDR4__ECC_U_DATA_0__REG DENALI_CTL_212 3784#define LPDDR4__ECC_U_DATA_0__FLD LPDDR4__DENALI_CTL_212__ECC_U_DATA_0 3785 3786#define LPDDR4__DENALI_CTL_213_READ_MASK 0xFFFFFFFFU 3787#define LPDDR4__DENALI_CTL_213_WRITE_MASK 0xFFFFFFFFU 3788#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_MASK 0xFFFFFFFFU 3789#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_SHIFT 0U 3790#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_WIDTH 32U 3791#define LPDDR4__ECC_U_DATA_1__REG DENALI_CTL_213 3792#define LPDDR4__ECC_U_DATA_1__FLD LPDDR4__DENALI_CTL_213__ECC_U_DATA_1 3793 3794#define LPDDR4__DENALI_CTL_214_READ_MASK 0xFFFFFFFFU 3795#define LPDDR4__DENALI_CTL_214_WRITE_MASK 0xFFFFFFFFU 3796#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_MASK 0xFFFFFFFFU 3797#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_SHIFT 0U 3798#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_WIDTH 32U 3799#define LPDDR4__ECC_C_ADDR_0__REG DENALI_CTL_214 3800#define LPDDR4__ECC_C_ADDR_0__FLD LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0 3801 3802#define LPDDR4__DENALI_CTL_215_READ_MASK 0x0000FF07U 3803#define LPDDR4__DENALI_CTL_215_WRITE_MASK 0x0000FF07U 3804#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_MASK 0x00000007U 3805#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_SHIFT 0U 3806#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_WIDTH 3U 3807#define LPDDR4__ECC_C_ADDR_1__REG DENALI_CTL_215 3808#define LPDDR4__ECC_C_ADDR_1__FLD LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1 3809 3810#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_MASK 0x0000FF00U 3811#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_SHIFT 8U 3812#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_WIDTH 8U 3813#define LPDDR4__ECC_C_SYND__REG DENALI_CTL_215 3814#define LPDDR4__ECC_C_SYND__FLD LPDDR4__DENALI_CTL_215__ECC_C_SYND 3815 3816#define LPDDR4__DENALI_CTL_216_READ_MASK 0xFFFFFFFFU 3817#define LPDDR4__DENALI_CTL_216_WRITE_MASK 0xFFFFFFFFU 3818#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_MASK 0xFFFFFFFFU 3819#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_SHIFT 0U 3820#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_WIDTH 32U 3821#define LPDDR4__ECC_C_DATA_0__REG DENALI_CTL_216 3822#define LPDDR4__ECC_C_DATA_0__FLD LPDDR4__DENALI_CTL_216__ECC_C_DATA_0 3823 3824#define LPDDR4__DENALI_CTL_217_READ_MASK 0xFFFFFFFFU 3825#define LPDDR4__DENALI_CTL_217_WRITE_MASK 0xFFFFFFFFU 3826#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_MASK 0xFFFFFFFFU 3827#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_SHIFT 0U 3828#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_WIDTH 32U 3829#define LPDDR4__ECC_C_DATA_1__REG DENALI_CTL_217 3830#define LPDDR4__ECC_C_DATA_1__FLD LPDDR4__DENALI_CTL_217__ECC_C_DATA_1 3831 3832#define LPDDR4__DENALI_CTL_218_READ_MASK 0x7FFF3F3FU 3833#define LPDDR4__DENALI_CTL_218_WRITE_MASK 0x7FFF3F3FU 3834#define LPDDR4__DENALI_CTL_218__ECC_U_ID_MASK 0x0000003FU 3835#define LPDDR4__DENALI_CTL_218__ECC_U_ID_SHIFT 0U 3836#define LPDDR4__DENALI_CTL_218__ECC_U_ID_WIDTH 6U 3837#define LPDDR4__ECC_U_ID__REG DENALI_CTL_218 3838#define LPDDR4__ECC_U_ID__FLD LPDDR4__DENALI_CTL_218__ECC_U_ID 3839 3840#define LPDDR4__DENALI_CTL_218__ECC_C_ID_MASK 0x00003F00U 3841#define LPDDR4__DENALI_CTL_218__ECC_C_ID_SHIFT 8U 3842#define LPDDR4__DENALI_CTL_218__ECC_C_ID_WIDTH 6U 3843#define LPDDR4__ECC_C_ID__REG DENALI_CTL_218 3844#define LPDDR4__ECC_C_ID__FLD LPDDR4__DENALI_CTL_218__ECC_C_ID 3845 3846#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_MASK 0x7FFF0000U 3847#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_SHIFT 16U 3848#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_WIDTH 15U 3849#define LPDDR4__NON_ECC_REGION_START_ADDR_0__REG DENALI_CTL_218 3850#define LPDDR4__NON_ECC_REGION_START_ADDR_0__FLD LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0 3851 3852#define LPDDR4__DENALI_CTL_219_READ_MASK 0x7FFF7FFFU 3853#define LPDDR4__DENALI_CTL_219_WRITE_MASK 0x7FFF7FFFU 3854#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_MASK 0x00007FFFU 3855#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_SHIFT 0U 3856#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_WIDTH 15U 3857#define LPDDR4__NON_ECC_REGION_END_ADDR_0__REG DENALI_CTL_219 3858#define LPDDR4__NON_ECC_REGION_END_ADDR_0__FLD LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0 3859 3860#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_MASK 0x7FFF0000U 3861#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_SHIFT 16U 3862#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_WIDTH 15U 3863#define LPDDR4__NON_ECC_REGION_START_ADDR_1__REG DENALI_CTL_219 3864#define LPDDR4__NON_ECC_REGION_START_ADDR_1__FLD LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1 3865 3866#define LPDDR4__DENALI_CTL_220_READ_MASK 0x7FFF7FFFU 3867#define LPDDR4__DENALI_CTL_220_WRITE_MASK 0x7FFF7FFFU 3868#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_MASK 0x00007FFFU 3869#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_SHIFT 0U 3870#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_WIDTH 15U 3871#define LPDDR4__NON_ECC_REGION_END_ADDR_1__REG DENALI_CTL_220 3872#define LPDDR4__NON_ECC_REGION_END_ADDR_1__FLD LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1 3873 3874#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_MASK 0x7FFF0000U 3875#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_SHIFT 16U 3876#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_WIDTH 15U 3877#define LPDDR4__NON_ECC_REGION_START_ADDR_2__REG DENALI_CTL_220 3878#define LPDDR4__NON_ECC_REGION_START_ADDR_2__FLD LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2 3879 3880#define LPDDR4__DENALI_CTL_221_READ_MASK 0x00077FFFU 3881#define LPDDR4__DENALI_CTL_221_WRITE_MASK 0x00077FFFU 3882#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_MASK 0x00007FFFU 3883#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_SHIFT 0U 3884#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_WIDTH 15U 3885#define LPDDR4__NON_ECC_REGION_END_ADDR_2__REG DENALI_CTL_221 3886#define LPDDR4__NON_ECC_REGION_END_ADDR_2__FLD LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2 3887 3888#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_MASK 0x00070000U 3889#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_SHIFT 16U 3890#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_WIDTH 3U 3891#define LPDDR4__NON_ECC_REGION_ENABLE__REG DENALI_CTL_221 3892#define LPDDR4__NON_ECC_REGION_ENABLE__FLD LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE 3893 3894#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_MASK 0x01000000U 3895#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_SHIFT 24U 3896#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WIDTH 1U 3897#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOCLR 0U 3898#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOSET 0U 3899#define LPDDR4__ECC_SCRUB_START__REG DENALI_CTL_221 3900#define LPDDR4__ECC_SCRUB_START__FLD LPDDR4__DENALI_CTL_221__ECC_SCRUB_START 3901 3902#define LPDDR4__DENALI_CTL_222_READ_MASK 0x010FFF01U 3903#define LPDDR4__DENALI_CTL_222_WRITE_MASK 0x010FFF01U 3904#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_MASK 0x00000001U 3905#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_SHIFT 0U 3906#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WIDTH 1U 3907#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOCLR 0U 3908#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOSET 0U 3909#define LPDDR4__ECC_SCRUB_IN_PROGRESS__REG DENALI_CTL_222 3910#define LPDDR4__ECC_SCRUB_IN_PROGRESS__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS 3911 3912#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_MASK 0x000FFF00U 3913#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_SHIFT 8U 3914#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_WIDTH 12U 3915#define LPDDR4__ECC_SCRUB_LEN__REG DENALI_CTL_222 3916#define LPDDR4__ECC_SCRUB_LEN__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN 3917 3918#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_MASK 0x01000000U 3919#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_SHIFT 24U 3920#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WIDTH 1U 3921#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOCLR 0U 3922#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOSET 0U 3923#define LPDDR4__ECC_SCRUB_MODE__REG DENALI_CTL_222 3924#define LPDDR4__ECC_SCRUB_MODE__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE 3925 3926#define LPDDR4__DENALI_CTL_223_READ_MASK 0xFFFFFFFFU 3927#define LPDDR4__DENALI_CTL_223_WRITE_MASK 0xFFFFFFFFU 3928#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_MASK 0x0000FFFFU 3929#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_SHIFT 0U 3930#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_WIDTH 16U 3931#define LPDDR4__ECC_SCRUB_INTERVAL__REG DENALI_CTL_223 3932#define LPDDR4__ECC_SCRUB_INTERVAL__FLD LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL 3933 3934#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_MASK 0xFFFF0000U 3935#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_SHIFT 16U 3936#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_WIDTH 16U 3937#define LPDDR4__ECC_SCRUB_IDLE_CNT__REG DENALI_CTL_223 3938#define LPDDR4__ECC_SCRUB_IDLE_CNT__FLD LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT 3939 3940#define LPDDR4__DENALI_CTL_224_READ_MASK 0xFFFFFFFFU 3941#define LPDDR4__DENALI_CTL_224_WRITE_MASK 0xFFFFFFFFU 3942#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_MASK 0xFFFFFFFFU 3943#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_SHIFT 0U 3944#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_WIDTH 32U 3945#define LPDDR4__ECC_SCRUB_START_ADDR_0__REG DENALI_CTL_224 3946#define LPDDR4__ECC_SCRUB_START_ADDR_0__FLD LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0 3947 3948#define LPDDR4__DENALI_CTL_225_READ_MASK 0x00000007U 3949#define LPDDR4__DENALI_CTL_225_WRITE_MASK 0x00000007U 3950#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_MASK 0x00000007U 3951#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_SHIFT 0U 3952#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_WIDTH 3U 3953#define LPDDR4__ECC_SCRUB_START_ADDR_1__REG DENALI_CTL_225 3954#define LPDDR4__ECC_SCRUB_START_ADDR_1__FLD LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1 3955 3956#define LPDDR4__DENALI_CTL_226_READ_MASK 0xFFFFFFFFU 3957#define LPDDR4__DENALI_CTL_226_WRITE_MASK 0xFFFFFFFFU 3958#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_MASK 0xFFFFFFFFU 3959#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_SHIFT 0U 3960#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_WIDTH 32U 3961#define LPDDR4__ECC_SCRUB_END_ADDR_0__REG DENALI_CTL_226 3962#define LPDDR4__ECC_SCRUB_END_ADDR_0__FLD LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0 3963 3964#define LPDDR4__DENALI_CTL_227_READ_MASK 0x1F1F1F07U 3965#define LPDDR4__DENALI_CTL_227_WRITE_MASK 0x1F1F1F07U 3966#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_MASK 0x00000007U 3967#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_SHIFT 0U 3968#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_WIDTH 3U 3969#define LPDDR4__ECC_SCRUB_END_ADDR_1__REG DENALI_CTL_227 3970#define LPDDR4__ECC_SCRUB_END_ADDR_1__FLD LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1 3971 3972#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_MASK 0x00001F00U 3973#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_SHIFT 8U 3974#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_WIDTH 5U 3975#define LPDDR4__LONG_COUNT_MASK__REG DENALI_CTL_227 3976#define LPDDR4__LONG_COUNT_MASK__FLD LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK 3977 3978#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_MASK 0x001F0000U 3979#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_SHIFT 16U 3980#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_WIDTH 5U 3981#define LPDDR4__AREF_NORM_THRESHOLD__REG DENALI_CTL_227 3982#define LPDDR4__AREF_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD 3983 3984#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_MASK 0x1F000000U 3985#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_SHIFT 24U 3986#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_WIDTH 5U 3987#define LPDDR4__AREF_HIGH_THRESHOLD__REG DENALI_CTL_227 3988#define LPDDR4__AREF_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD 3989 3990#define LPDDR4__DENALI_CTL_228_READ_MASK 0x000F1F1FU 3991#define LPDDR4__DENALI_CTL_228_WRITE_MASK 0x000F1F1FU 3992#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_MASK 0x0000001FU 3993#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_SHIFT 0U 3994#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_WIDTH 5U 3995#define LPDDR4__AREF_MAX_DEFICIT__REG DENALI_CTL_228 3996#define LPDDR4__AREF_MAX_DEFICIT__FLD LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT 3997 3998#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_MASK 0x00001F00U 3999#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_SHIFT 8U 4000#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_WIDTH 5U
4001#define LPDDR4__AREF_MAX_CREDIT__REG DENALI_CTL_228 4002#define LPDDR4__AREF_MAX_CREDIT__FLD LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT 4003 4004#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_MASK 0x000F0000U 4005#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_SHIFT 16U 4006#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_WIDTH 4U 4007#define LPDDR4__AREF_CMD_MAX_PER_TREFI__REG DENALI_CTL_228 4008#define LPDDR4__AREF_CMD_MAX_PER_TREFI__FLD LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI 4009 4010#define LPDDR4__DENALI_CTL_229_READ_MASK 0xFFFFFFFFU 4011#define LPDDR4__DENALI_CTL_229_WRITE_MASK 0xFFFFFFFFU 4012#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_MASK 0x0000FFFFU 4013#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_SHIFT 0U 4014#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_WIDTH 16U 4015#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__REG DENALI_CTL_229 4016#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0 4017 4018#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U 4019#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_SHIFT 16U 4020#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_WIDTH 16U 4021#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__REG DENALI_CTL_229 4022#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0 4023 4024#define LPDDR4__DENALI_CTL_230_READ_MASK 0xFFFFFFFFU 4025#define LPDDR4__DENALI_CTL_230_WRITE_MASK 0xFFFFFFFFU 4026#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU 4027#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_SHIFT 0U 4028#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_WIDTH 16U 4029#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__REG DENALI_CTL_230 4030#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0 4031 4032#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_MASK 0xFFFF0000U 4033#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_SHIFT 16U 4034#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_WIDTH 16U 4035#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__REG DENALI_CTL_230 4036#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0 4037 4038#define LPDDR4__DENALI_CTL_231_READ_MASK 0xFFFFFFFFU 4039#define LPDDR4__DENALI_CTL_231_WRITE_MASK 0xFFFFFFFFU 4040#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU 4041#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_SHIFT 0U 4042#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_WIDTH 16U 4043#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__REG DENALI_CTL_231 4044#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0 4045 4046#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_MASK 0xFFFF0000U 4047#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_SHIFT 16U 4048#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_WIDTH 16U 4049#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__REG DENALI_CTL_231 4050#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0 4051 4052#define LPDDR4__DENALI_CTL_232_READ_MASK 0xFFFFFFFFU 4053#define LPDDR4__DENALI_CTL_232_WRITE_MASK 0xFFFFFFFFU 4054#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_MASK 0x0000FFFFU 4055#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_SHIFT 0U 4056#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_WIDTH 16U 4057#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__REG DENALI_CTL_232 4058#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0 4059 4060#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_MASK 0xFFFF0000U 4061#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_SHIFT 16U 4062#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_WIDTH 16U 4063#define LPDDR4__ZQ_CS_TIMEOUT_F0__REG DENALI_CTL_232 4064#define LPDDR4__ZQ_CS_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0 4065 4066#define LPDDR4__DENALI_CTL_233_READ_MASK 0xFFFFFFFFU 4067#define LPDDR4__DENALI_CTL_233_WRITE_MASK 0xFFFFFFFFU 4068#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU 4069#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_SHIFT 0U 4070#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_WIDTH 16U 4071#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_233 4072#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0 4073 4074#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_MASK 0xFFFF0000U 4075#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_SHIFT 16U 4076#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_WIDTH 16U 4077#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__REG DENALI_CTL_233 4078#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1 4079 4080#define LPDDR4__DENALI_CTL_234_READ_MASK 0xFFFFFFFFU 4081#define LPDDR4__DENALI_CTL_234_WRITE_MASK 0xFFFFFFFFU 4082#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU 4083#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_SHIFT 0U 4084#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_WIDTH 16U 4085#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__REG DENALI_CTL_234 4086#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1 4087 4088#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U 4089#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_SHIFT 16U 4090#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_WIDTH 16U 4091#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__REG DENALI_CTL_234 4092#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1 4093 4094#define LPDDR4__DENALI_CTL_235_READ_MASK 0xFFFFFFFFU 4095#define LPDDR4__DENALI_CTL_235_WRITE_MASK 0xFFFFFFFFU 4096#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_MASK 0x0000FFFFU 4097#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_SHIFT 0U 4098#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_WIDTH 16U 4099#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__REG DENALI_CTL_235 4100#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1 4101 4102#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U 4103#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_SHIFT 16U 4104#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_WIDTH 16U 4105#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__REG DENALI_CTL_235 4106#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1 4107 4108#define LPDDR4__DENALI_CTL_236_READ_MASK 0xFFFFFFFFU 4109#define LPDDR4__DENALI_CTL_236_WRITE_MASK 0xFFFFFFFFU 4110#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_MASK 0x0000FFFFU 4111#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_SHIFT 0U 4112#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_WIDTH 16U 4113#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__REG DENALI_CTL_236 4114#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1 4115 4116#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_MASK 0xFFFF0000U 4117#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_SHIFT 16U 4118#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_WIDTH 16U 4119#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__REG DENALI_CTL_236 4120#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1 4121 4122#define LPDDR4__DENALI_CTL_237_READ_MASK 0xFFFFFFFFU 4123#define LPDDR4__DENALI_CTL_237_WRITE_MASK 0xFFFFFFFFU 4124#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_MASK 0x0000FFFFU 4125#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_SHIFT 0U 4126#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_WIDTH 16U 4127#define LPDDR4__ZQ_CS_TIMEOUT_F1__REG DENALI_CTL_237 4128#define LPDDR4__ZQ_CS_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1 4129 4130#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U 4131#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_SHIFT 16U 4132#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_WIDTH 16U 4133#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_237 4134#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1 4135 4136#define LPDDR4__DENALI_CTL_238_READ_MASK 0xFFFFFFFFU 4137#define LPDDR4__DENALI_CTL_238_WRITE_MASK 0xFFFFFFFFU 4138#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_MASK 0x0000FFFFU 4139#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_SHIFT 0U 4140#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_WIDTH 16U 4141#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__REG DENALI_CTL_238 4142#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2 4143 4144#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U 4145#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_SHIFT 16U 4146#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_WIDTH 16U 4147#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__REG DENALI_CTL_238 4148#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2 4149 4150#define LPDDR4__DENALI_CTL_239_READ_MASK 0xFFFFFFFFU 4151#define LPDDR4__DENALI_CTL_239_WRITE_MASK 0xFFFFFFFFU 4152#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU 4153#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_SHIFT 0U 4154#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_WIDTH 16U 4155#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__REG DENALI_CTL_239 4156#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2 4157 4158#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_MASK 0xFFFF0000U 4159#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_SHIFT 16U 4160#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_WIDTH 16U 4161#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__REG DENALI_CTL_239 4162#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2 4163 4164#define LPDDR4__DENALI_CTL_240_READ_MASK 0xFFFFFFFFU 4165#define LPDDR4__DENALI_CTL_240_WRITE_MASK 0xFFFFFFFFU 4166#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU 4167#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_SHIFT 0U 4168#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_WIDTH 16U 4169#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__REG DENALI_CTL_240 4170#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2 4171 4172#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_MASK 0xFFFF0000U 4173#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_SHIFT 16U 4174#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_WIDTH 16U 4175#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__REG DENALI_CTL_240 4176#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2 4177 4178#define LPDDR4__DENALI_CTL_241_READ_MASK 0xFFFFFFFFU 4179#define LPDDR4__DENALI_CTL_241_WRITE_MASK 0xFFFFFFFFU 4180#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_MASK 0x0000FFFFU 4181#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_SHIFT 0U 4182#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_WIDTH 16U 4183#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__REG DENALI_CTL_241 4184#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2 4185 4186#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_MASK 0xFFFF0000U 4187#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_SHIFT 16U 4188#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_WIDTH 16U 4189#define LPDDR4__ZQ_CS_TIMEOUT_F2__REG DENALI_CTL_241 4190#define LPDDR4__ZQ_CS_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2 4191 4192#define LPDDR4__DENALI_CTL_242_READ_MASK 0x0007FFFFU 4193#define LPDDR4__DENALI_CTL_242_WRITE_MASK 0x0007FFFFU 4194#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU 4195#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_SHIFT 0U 4196#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_WIDTH 16U 4197#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_242 4198#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2 4199 4200#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_MASK 0x00070000U 4201#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_SHIFT 16U 4202#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_WIDTH 3U 4203#define LPDDR4__MC_RESERVED23__REG DENALI_CTL_242 4204#define LPDDR4__MC_RESERVED23__FLD LPDDR4__DENALI_CTL_242__MC_RESERVED23 4205 4206#define LPDDR4__DENALI_CTL_243_READ_MASK 0xFFFFFFFFU 4207#define LPDDR4__DENALI_CTL_243_WRITE_MASK 0xFFFFFFFFU 4208#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_MASK 0x0000FFFFU 4209#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_SHIFT 0U 4210#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_WIDTH 16U 4211#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F0__REG DENALI_CTL_243 4212#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F0__FLD LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0 4213 4214#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_MASK 0xFFFF0000U 4215#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_SHIFT 16U 4216#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_WIDTH 16U 4217#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F0__REG DENALI_CTL_243 4218#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F0__FLD LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0 4219 4220#define LPDDR4__DENALI_CTL_244_READ_MASK 0xFFFFFFFFU 4221#define LPDDR4__DENALI_CTL_244_WRITE_MASK 0xFFFFFFFFU 4222#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_MASK 0x0000FFFFU 4223#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_SHIFT 0U 4224#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_WIDTH 16U 4225#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0__REG DENALI_CTL_244 4226#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0__FLD LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0 4227 4228#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_MASK 0xFFFF0000U 4229#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_SHIFT 16U 4230#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_WIDTH 16U 4231#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F0__REG DENALI_CTL_244 4232#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F0__FLD LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0 4233 4234#define LPDDR4__DENALI_CTL_245_READ_MASK 0xFFFFFFFFU 4235#define LPDDR4__DENALI_CTL_245_WRITE_MASK 0xFFFFFFFFU 4236#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_MASK 0x0000FFFFU 4237#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_SHIFT 0U 4238#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_WIDTH 16U 4239#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F0__REG DENALI_CTL_245 4240#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F0__FLD LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0 4241 4242#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_MASK 0xFFFF0000U 4243#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_SHIFT 16U 4244#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_WIDTH 16U 4245#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0__REG DENALI_CTL_245 4246#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0__FLD LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0 4247 4248#define LPDDR4__DENALI_CTL_246_READ_MASK 0xFFFFFFFFU 4249#define LPDDR4__DENALI_CTL_246_WRITE_MASK 0xFFFFFFFFU 4250#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_MASK 0x0000FFFFU 4251#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_SHIFT 0U 4252#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_WIDTH 16U 4253#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0__REG DENALI_CTL_246 4254#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0__FLD LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0 4255 4256#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_MASK 0xFFFF0000U 4257#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_SHIFT 16U 4258#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_WIDTH 16U 4259#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0__REG DENALI_CTL_246 4260#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0__FLD LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0 4261 4262#define LPDDR4__DENALI_CTL_247_READ_MASK 0xFFFFFFFFU 4263#define LPDDR4__DENALI_CTL_247_WRITE_MASK 0xFFFFFFFFU 4264#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_MASK 0x0000FFFFU 4265#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_SHIFT 0U 4266#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_WIDTH 16U 4267#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F1__REG DENALI_CTL_247 4268#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F1__FLD LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1 4269 4270#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_MASK 0xFFFF0000U 4271#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_SHIFT 16U 4272#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_WIDTH 16U 4273#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F1__REG DENALI_CTL_247 4274#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F1__FLD LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1 4275 4276#define LPDDR4__DENALI_CTL_248_READ_MASK 0xFFFFFFFFU 4277#define LPDDR4__DENALI_CTL_248_WRITE_MASK 0xFFFFFFFFU 4278#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_MASK 0x0000FFFFU 4279#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_SHIFT 0U 4280#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_WIDTH 16U 4281#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1__REG DENALI_CTL_248 4282#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1__FLD LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1 4283 4284#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_MASK 0xFFFF0000U 4285#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_SHIFT 16U 4286#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_WIDTH 16U 4287#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F1__REG DENALI_CTL_248 4288#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F1__FLD LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1 4289 4290#define LPDDR4__DENALI_CTL_249_READ_MASK 0xFFFFFFFFU 4291#define LPDDR4__DENALI_CTL_249_WRITE_MASK 0xFFFFFFFFU 4292#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_MASK 0x0000FFFFU 4293#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_SHIFT 0U 4294#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_WIDTH 16U 4295#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F1__REG DENALI_CTL_249 4296#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F1__FLD LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1 4297 4298#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_MASK 0xFFFF0000U 4299#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_SHIFT 16U 4300#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_WIDTH 16U 4301#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1__REG DENALI_CTL_249 4302#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1__FLD LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1 4303 4304#define LPDDR4__DENALI_CTL_250_READ_MASK 0xFFFFFFFFU 4305#define LPDDR4__DENALI_CTL_250_WRITE_MASK 0xFFFFFFFFU 4306#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_MASK 0x0000FFFFU 4307#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_SHIFT 0U 4308#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_WIDTH 16U 4309#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1__REG DENALI_CTL_250 4310#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1__FLD LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1 4311 4312#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_MASK 0xFFFF0000U 4313#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_SHIFT 16U 4314#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_WIDTH 16U 4315#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1__REG DENALI_CTL_250 4316#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1__FLD LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1 4317 4318#define LPDDR4__DENALI_CTL_251_READ_MASK 0xFFFFFFFFU 4319#define LPDDR4__DENALI_CTL_251_WRITE_MASK 0xFFFFFFFFU 4320#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_MASK 0x0000FFFFU 4321#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_SHIFT 0U 4322#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_WIDTH 16U 4323#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F2__REG DENALI_CTL_251 4324#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F2__FLD LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2 4325 4326#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_MASK 0xFFFF0000U 4327#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_SHIFT 16U 4328#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_WIDTH 16U 4329#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F2__REG DENALI_CTL_251 4330#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F2__FLD LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2 4331 4332#define LPDDR4__DENALI_CTL_252_READ_MASK 0xFFFFFFFFU 4333#define LPDDR4__DENALI_CTL_252_WRITE_MASK 0xFFFFFFFFU 4334#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_MASK 0x0000FFFFU 4335#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_SHIFT 0U 4336#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_WIDTH 16U 4337#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2__REG DENALI_CTL_252 4338#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2__FLD LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2 4339 4340#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_MASK 0xFFFF0000U 4341#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_SHIFT 16U 4342#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_WIDTH 16U 4343#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F2__REG DENALI_CTL_252 4344#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F2__FLD LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2 4345 4346#define LPDDR4__DENALI_CTL_253_READ_MASK 0xFFFFFFFFU 4347#define LPDDR4__DENALI_CTL_253_WRITE_MASK 0xFFFFFFFFU 4348#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_MASK 0x0000FFFFU 4349#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_SHIFT 0U 4350#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_WIDTH 16U 4351#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F2__REG DENALI_CTL_253 4352#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F2__FLD LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2 4353 4354#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_MASK 0xFFFF0000U 4355#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_SHIFT 16U 4356#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_WIDTH 16U 4357#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2__REG DENALI_CTL_253 4358#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2__FLD LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2 4359 4360#define LPDDR4__DENALI_CTL_254_READ_MASK 0xFFFFFFFFU 4361#define LPDDR4__DENALI_CTL_254_WRITE_MASK 0xFFFFFFFFU 4362#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_MASK 0x0000FFFFU 4363#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_SHIFT 0U 4364#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_WIDTH 16U 4365#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2__REG DENALI_CTL_254 4366#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2__FLD LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2 4367 4368#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_MASK 0xFFFF0000U 4369#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_SHIFT 16U 4370#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_WIDTH 16U 4371#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2__REG DENALI_CTL_254 4372#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2__FLD LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2 4373 4374#define LPDDR4__DENALI_CTL_255_READ_MASK 0x0000FF00U 4375#define LPDDR4__DENALI_CTL_255_WRITE_MASK 0x0000FF00U 4376#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_MASK 0x000000FFU 4377#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_SHIFT 0U 4378#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_WIDTH 8U 4379#define LPDDR4__WATCHDOG_RELOAD__REG DENALI_CTL_255 4380#define LPDDR4__WATCHDOG_RELOAD__FLD LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD 4381 4382#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_MASK 0x0000FF00U 4383#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_SHIFT 8U 4384#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_WIDTH 8U 4385#define LPDDR4__WATCHDOG_DIAGNOSTIC_MODE__REG DENALI_CTL_255 4386#define LPDDR4__WATCHDOG_DIAGNOSTIC_MODE__FLD LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE 4387 4388#define LPDDR4__DENALI_CTL_256_READ_MASK 0x000FFFFFU 4389#define LPDDR4__DENALI_CTL_256_WRITE_MASK 0x000FFFFFU 4390#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_MASK 0x000FFFFFU 4391#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_SHIFT 0U 4392#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_WIDTH 20U 4393#define LPDDR4__TIMEOUT_TIMER_LOG__REG DENALI_CTL_256 4394#define LPDDR4__TIMEOUT_TIMER_LOG__FLD LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG 4395 4396#define LPDDR4__DENALI_CTL_257_READ_MASK 0x0FFF0FFFU 4397#define LPDDR4__DENALI_CTL_257_WRITE_MASK 0x0FFF0FFFU 4398#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_MASK 0x00000FFFU 4399#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_SHIFT 0U 4400#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_WIDTH 12U 4401#define LPDDR4__ZQINIT_F0__REG DENALI_CTL_257 4402#define LPDDR4__ZQINIT_F0__FLD LPDDR4__DENALI_CTL_257__ZQINIT_F0 4403 4404#define LPDDR4__DENALI_CTL_257__ZQCL_F0_MASK 0x0FFF0000U 4405#define LPDDR4__DENALI_CTL_257__ZQCL_F0_SHIFT 16U 4406#define LPDDR4__DENALI_CTL_257__ZQCL_F0_WIDTH 12U 4407#define LPDDR4__ZQCL_F0__REG DENALI_CTL_257 4408#define LPDDR4__ZQCL_F0__FLD LPDDR4__DENALI_CTL_257__ZQCL_F0 4409 4410#define LPDDR4__DENALI_CTL_258_READ_MASK 0x0FFF0FFFU 4411#define LPDDR4__DENALI_CTL_258_WRITE_MASK 0x0FFF0FFFU 4412#define LPDDR4__DENALI_CTL_258__ZQCS_F0_MASK 0x00000FFFU 4413#define LPDDR4__DENALI_CTL_258__ZQCS_F0_SHIFT 0U 4414#define LPDDR4__DENALI_CTL_258__ZQCS_F0_WIDTH 12U 4415#define LPDDR4__ZQCS_F0__REG DENALI_CTL_258 4416#define LPDDR4__ZQCS_F0__FLD LPDDR4__DENALI_CTL_258__ZQCS_F0 4417 4418#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_MASK 0x0FFF0000U 4419#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_SHIFT 16U 4420#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_WIDTH 12U 4421#define LPDDR4__TZQCAL_F0__REG DENALI_CTL_258 4422#define LPDDR4__TZQCAL_F0__FLD LPDDR4__DENALI_CTL_258__TZQCAL_F0 4423 4424#define LPDDR4__DENALI_CTL_259_READ_MASK 0x000FFF7FU 4425#define LPDDR4__DENALI_CTL_259_WRITE_MASK 0x000FFF7FU 4426#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_MASK 0x0000007FU 4427#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_SHIFT 0U 4428#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_WIDTH 7U 4429#define LPDDR4__TZQLAT_F0__REG DENALI_CTL_259 4430#define LPDDR4__TZQLAT_F0__FLD LPDDR4__DENALI_CTL_259__TZQLAT_F0 4431 4432#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_MASK 0x000FFF00U 4433#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_SHIFT 8U 4434#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_WIDTH 12U 4435#define LPDDR4__ZQINIT_F1__REG DENALI_CTL_259 4436#define LPDDR4__ZQINIT_F1__FLD LPDDR4__DENALI_CTL_259__ZQINIT_F1 4437 4438#define LPDDR4__DENALI_CTL_260_READ_MASK 0x0FFF0FFFU 4439#define LPDDR4__DENALI_CTL_260_WRITE_MASK 0x0FFF0FFFU 4440#define LPDDR4__DENALI_CTL_260__ZQCL_F1_MASK 0x00000FFFU 4441#define LPDDR4__DENALI_CTL_260__ZQCL_F1_SHIFT 0U 4442#define LPDDR4__DENALI_CTL_260__ZQCL_F1_WIDTH 12U 4443#define LPDDR4__ZQCL_F1__REG DENALI_CTL_260 4444#define LPDDR4__ZQCL_F1__FLD LPDDR4__DENALI_CTL_260__ZQCL_F1 4445 4446#define LPDDR4__DENALI_CTL_260__ZQCS_F1_MASK 0x0FFF0000U 4447#define LPDDR4__DENALI_CTL_260__ZQCS_F1_SHIFT 16U 4448#define LPDDR4__DENALI_CTL_260__ZQCS_F1_WIDTH 12U 4449#define LPDDR4__ZQCS_F1__REG DENALI_CTL_260 4450#define LPDDR4__ZQCS_F1__FLD LPDDR4__DENALI_CTL_260__ZQCS_F1 4451 4452#define LPDDR4__DENALI_CTL_261_READ_MASK 0x007F0FFFU 4453#define LPDDR4__DENALI_CTL_261_WRITE_MASK 0x007F0FFFU 4454#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_MASK 0x00000FFFU 4455#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_SHIFT 0U 4456#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_WIDTH 12U 4457#define LPDDR4__TZQCAL_F1__REG DENALI_CTL_261 4458#define LPDDR4__TZQCAL_F1__FLD LPDDR4__DENALI_CTL_261__TZQCAL_F1 4459 4460#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_MASK 0x007F0000U 4461#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_SHIFT 16U 4462#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_WIDTH 7U 4463#define LPDDR4__TZQLAT_F1__REG DENALI_CTL_261 4464#define LPDDR4__TZQLAT_F1__FLD LPDDR4__DENALI_CTL_261__TZQLAT_F1 4465 4466#define LPDDR4__DENALI_CTL_262_READ_MASK 0x0FFF0FFFU 4467#define LPDDR4__DENALI_CTL_262_WRITE_MASK 0x0FFF0FFFU 4468#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_MASK 0x00000FFFU 4469#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_SHIFT 0U 4470#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_WIDTH 12U 4471#define LPDDR4__ZQINIT_F2__REG DENALI_CTL_262 4472#define LPDDR4__ZQINIT_F2__FLD LPDDR4__DENALI_CTL_262__ZQINIT_F2 4473 4474#define LPDDR4__DENALI_CTL_262__ZQCL_F2_MASK 0x0FFF0000U 4475#define LPDDR4__DENALI_CTL_262__ZQCL_F2_SHIFT 16U 4476#define LPDDR4__DENALI_CTL_262__ZQCL_F2_WIDTH 12U 4477#define LPDDR4__ZQCL_F2__REG DENALI_CTL_262 4478#define LPDDR4__ZQCL_F2__FLD LPDDR4__DENALI_CTL_262__ZQCL_F2 4479 4480#define LPDDR4__DENALI_CTL_263_READ_MASK 0x0FFF0FFFU 4481#define LPDDR4__DENALI_CTL_263_WRITE_MASK 0x0FFF0FFFU 4482#define LPDDR4__DENALI_CTL_263__ZQCS_F2_MASK 0x00000FFFU 4483#define LPDDR4__DENALI_CTL_263__ZQCS_F2_SHIFT 0U 4484#define LPDDR4__DENALI_CTL_263__ZQCS_F2_WIDTH 12U 4485#define LPDDR4__ZQCS_F2__REG DENALI_CTL_263 4486#define LPDDR4__ZQCS_F2__FLD LPDDR4__DENALI_CTL_263__ZQCS_F2 4487 4488#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_MASK 0x0FFF0000U 4489#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_SHIFT 16U 4490#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_WIDTH 12U 4491#define LPDDR4__TZQCAL_F2__REG DENALI_CTL_263 4492#define LPDDR4__TZQCAL_F2__FLD LPDDR4__DENALI_CTL_263__TZQCAL_F2 4493 4494#define LPDDR4__DENALI_CTL_264_READ_MASK 0x0100037FU 4495#define LPDDR4__DENALI_CTL_264_WRITE_MASK 0x0100037FU 4496#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_MASK 0x0000007FU 4497#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_SHIFT 0U 4498#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_WIDTH 7U 4499#define LPDDR4__TZQLAT_F2__REG DENALI_CTL_264 4500#define LPDDR4__TZQLAT_F2__FLD LPDDR4__DENALI_CTL_264__TZQLAT_F2 4501 4502#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_MASK 0x00000300U 4503#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_SHIFT 8U 4504#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_WIDTH 2U 4505#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__REG DENALI_CTL_264 4506#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__FLD LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP 4507 4508#define LPDDR4__DENALI_CTL_264__ZQ_REQ_MASK 0x000F0000U 4509#define LPDDR4__DENALI_CTL_264__ZQ_REQ_SHIFT 16U 4510#define LPDDR4__DENALI_CTL_264__ZQ_REQ_WIDTH 4U 4511#define LPDDR4__ZQ_REQ__REG DENALI_CTL_264 4512#define LPDDR4__ZQ_REQ__FLD LPDDR4__DENALI_CTL_264__ZQ_REQ 4513 4514#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_MASK 0x01000000U 4515#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_SHIFT 24U 4516#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WIDTH 1U 4517#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOCLR 0U 4518#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOSET 0U 4519#define LPDDR4__ZQ_REQ_PENDING__REG DENALI_CTL_264 4520#define LPDDR4__ZQ_REQ_PENDING__FLD LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING 4521 4522#define LPDDR4__DENALI_CTL_265_READ_MASK 0x0FFF0FFFU 4523#define LPDDR4__DENALI_CTL_265_WRITE_MASK 0x0FFF0FFFU 4524#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_MASK 0x00000FFFU 4525#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_SHIFT 0U 4526#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_WIDTH 12U 4527#define LPDDR4__ZQRESET_F0__REG DENALI_CTL_265 4528#define LPDDR4__ZQRESET_F0__FLD LPDDR4__DENALI_CTL_265__ZQRESET_F0 4529 4530#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_MASK 0x0FFF0000U 4531#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_SHIFT 16U 4532#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_WIDTH 12U 4533#define LPDDR4__ZQRESET_F1__REG DENALI_CTL_265 4534#define LPDDR4__ZQRESET_F1__FLD LPDDR4__DENALI_CTL_265__ZQRESET_F1 4535 4536#define LPDDR4__DENALI_CTL_266_READ_MASK 0x01010FFFU 4537#define LPDDR4__DENALI_CTL_266_WRITE_MASK 0x01010FFFU 4538#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_MASK 0x00000FFFU 4539#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_SHIFT 0U 4540#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_WIDTH 12U 4541#define LPDDR4__ZQRESET_F2__REG DENALI_CTL_266 4542#define LPDDR4__ZQRESET_F2__FLD LPDDR4__DENALI_CTL_266__ZQRESET_F2 4543 4544#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_MASK 0x00010000U 4545#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_SHIFT 16U 4546#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WIDTH 1U 4547#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOCLR 0U 4548#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOSET 0U 4549#define LPDDR4__NO_ZQ_INIT__REG DENALI_CTL_266 4550#define LPDDR4__NO_ZQ_INIT__FLD LPDDR4__DENALI_CTL_266__NO_ZQ_INIT 4551 4552#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_MASK 0x01000000U 4553#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_SHIFT 24U 4554#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WIDTH 1U 4555#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOCLR 0U 4556#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOSET 0U 4557#define LPDDR4__ZQCS_ROTATE__REG DENALI_CTL_266 4558#define LPDDR4__ZQCS_ROTATE__FLD LPDDR4__DENALI_CTL_266__ZQCS_ROTATE 4559 4560#define LPDDR4__DENALI_CTL_267_READ_MASK 0x03030303U 4561#define LPDDR4__DENALI_CTL_267_WRITE_MASK 0x03030303U 4562#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_MASK 0x00000003U 4563#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_SHIFT 0U 4564#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_WIDTH 2U 4565#define LPDDR4__ZQ_CAL_START_MAP_0__REG DENALI_CTL_267 4566#define LPDDR4__ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0 4567 4568#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_MASK 0x00000300U 4569#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_SHIFT 8U 4570#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_WIDTH 2U 4571#define LPDDR4__ZQ_CAL_LATCH_MAP_0__REG DENALI_CTL_267 4572#define LPDDR4__ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0 4573 4574#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_MASK 0x00030000U 4575#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_SHIFT 16U 4576#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_WIDTH 2U 4577#define LPDDR4__ZQ_CAL_START_MAP_1__REG DENALI_CTL_267 4578#define LPDDR4__ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1 4579 4580#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_MASK 0x03000000U 4581#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_SHIFT 24U 4582#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_WIDTH 2U 4583#define LPDDR4__ZQ_CAL_LATCH_MAP_1__REG DENALI_CTL_267 4584#define LPDDR4__ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1 4585 4586#define LPDDR4__DENALI_CTL_268_READ_MASK 0x07070303U 4587#define LPDDR4__DENALI_CTL_268_WRITE_MASK 0x07070303U 4588#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_MASK 0x00000003U 4589#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_SHIFT 0U 4590#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_WIDTH 2U 4591#define LPDDR4__BANK_DIFF_0__REG DENALI_CTL_268 4592#define LPDDR4__BANK_DIFF_0__FLD LPDDR4__DENALI_CTL_268__BANK_DIFF_0 4593 4594#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_MASK 0x00000300U 4595#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_SHIFT 8U 4596#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_WIDTH 2U 4597#define LPDDR4__BANK_DIFF_1__REG DENALI_CTL_268 4598#define LPDDR4__BANK_DIFF_1__FLD LPDDR4__DENALI_CTL_268__BANK_DIFF_1 4599 4600#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_MASK 0x00070000U 4601#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_SHIFT 16U 4602#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_WIDTH 3U 4603#define LPDDR4__ROW_DIFF_0__REG DENALI_CTL_268 4604#define LPDDR4__ROW_DIFF_0__FLD LPDDR4__DENALI_CTL_268__ROW_DIFF_0 4605 4606#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_MASK 0x07000000U 4607#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_SHIFT 24U 4608#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_WIDTH 3U 4609#define LPDDR4__ROW_DIFF_1__REG DENALI_CTL_268 4610#define LPDDR4__ROW_DIFF_1__FLD LPDDR4__DENALI_CTL_268__ROW_DIFF_1 4611 4612#define LPDDR4__DENALI_CTL_269_READ_MASK 0xFFFF0F0FU 4613#define LPDDR4__DENALI_CTL_269_WRITE_MASK 0xFFFF0F0FU 4614#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_MASK 0x0000000FU 4615#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_SHIFT 0U 4616#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_WIDTH 4U 4617#define LPDDR4__COL_DIFF_0__REG DENALI_CTL_269 4618#define LPDDR4__COL_DIFF_0__FLD LPDDR4__DENALI_CTL_269__COL_DIFF_0 4619 4620#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_MASK 0x00000F00U 4621#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_SHIFT 8U 4622#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_WIDTH 4U 4623#define LPDDR4__COL_DIFF_1__REG DENALI_CTL_269 4624#define LPDDR4__COL_DIFF_1__FLD LPDDR4__DENALI_CTL_269__COL_DIFF_1 4625 4626#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_MASK 0xFFFF0000U 4627#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_SHIFT 16U 4628#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_WIDTH 16U 4629#define LPDDR4__CS_VAL_LOWER_0__REG DENALI_CTL_269 4630#define LPDDR4__CS_VAL_LOWER_0__FLD LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0 4631 4632#define LPDDR4__DENALI_CTL_270_READ_MASK 0x0007FFFFU 4633#define LPDDR4__DENALI_CTL_270_WRITE_MASK 0x0007FFFFU 4634#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_MASK 0x0000FFFFU 4635#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_SHIFT 0U 4636#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_WIDTH 16U 4637#define LPDDR4__CS_VAL_UPPER_0__REG DENALI_CTL_270 4638#define LPDDR4__CS_VAL_UPPER_0__FLD LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0 4639 4640#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_MASK 0x00070000U 4641#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_SHIFT 16U 4642#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_WIDTH 3U 4643#define LPDDR4__ROW_START_VAL_0__REG DENALI_CTL_270 4644#define LPDDR4__ROW_START_VAL_0__FLD LPDDR4__DENALI_CTL_270__ROW_START_VAL_0 4645 4646#define LPDDR4__DENALI_CTL_271_READ_MASK 0xFFFFFFFFU 4647#define LPDDR4__DENALI_CTL_271_WRITE_MASK 0xFFFFFFFFU 4648#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_MASK 0x0000FFFFU 4649#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_SHIFT 0U 4650#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_WIDTH 16U 4651#define LPDDR4__CS_VAL_LOWER_1__REG DENALI_CTL_271 4652#define LPDDR4__CS_VAL_LOWER_1__FLD LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1 4653 4654#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_MASK 0xFFFF0000U 4655#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_SHIFT 16U 4656#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_WIDTH 16U 4657#define LPDDR4__CS_VAL_UPPER_1__REG DENALI_CTL_271 4658#define LPDDR4__CS_VAL_UPPER_1__FLD LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1 4659 4660#define LPDDR4__DENALI_CTL_272_READ_MASK 0xFFFF0307U 4661#define LPDDR4__DENALI_CTL_272_WRITE_MASK 0xFFFF0307U 4662#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_MASK 0x00000007U 4663#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_SHIFT 0U 4664#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_WIDTH 3U 4665#define LPDDR4__ROW_START_VAL_1__REG DENALI_CTL_272 4666#define LPDDR4__ROW_START_VAL_1__FLD LPDDR4__DENALI_CTL_272__ROW_START_VAL_1 4667 4668#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_MASK 0x00000300U 4669#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_SHIFT 8U 4670#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_WIDTH 2U 4671#define LPDDR4__CS_MAP_NON_POW2__REG DENALI_CTL_272 4672#define LPDDR4__CS_MAP_NON_POW2__FLD LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2 4673 4674#define LPDDR4__DENALI_CTL_272__CS_MSK_0_MASK 0xFFFF0000U 4675#define LPDDR4__DENALI_CTL_272__CS_MSK_0_SHIFT 16U 4676#define LPDDR4__DENALI_CTL_272__CS_MSK_0_WIDTH 16U 4677#define LPDDR4__CS_MSK_0__REG DENALI_CTL_272 4678#define LPDDR4__CS_MSK_0__FLD LPDDR4__DENALI_CTL_272__CS_MSK_0 4679 4680#define LPDDR4__DENALI_CTL_273_READ_MASK 0x1F01FFFFU 4681#define LPDDR4__DENALI_CTL_273_WRITE_MASK 0x1F01FFFFU 4682#define LPDDR4__DENALI_CTL_273__CS_MSK_1_MASK 0x0000FFFFU 4683#define LPDDR4__DENALI_CTL_273__CS_MSK_1_SHIFT 0U 4684#define LPDDR4__DENALI_CTL_273__CS_MSK_1_WIDTH 16U 4685#define LPDDR4__CS_MSK_1__REG DENALI_CTL_273 4686#define LPDDR4__CS_MSK_1__FLD LPDDR4__DENALI_CTL_273__CS_MSK_1 4687 4688#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_MASK 0x00010000U 4689#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_SHIFT 16U 4690#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WIDTH 1U 4691#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOCLR 0U 4692#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOSET 0U 4693#define LPDDR4__CS_LOWER_ADDR_EN__REG DENALI_CTL_273 4694#define LPDDR4__CS_LOWER_ADDR_EN__FLD LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN 4695 4696#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_MASK 0x1F000000U 4697#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_SHIFT 24U 4698#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_WIDTH 5U 4699#define LPDDR4__MC_RESERVED24__REG DENALI_CTL_273 4700#define LPDDR4__MC_RESERVED24__FLD LPDDR4__DENALI_CTL_273__MC_RESERVED24 4701 4702#define LPDDR4__DENALI_CTL_274_READ_MASK 0xFFFF1F01U 4703#define LPDDR4__DENALI_CTL_274_WRITE_MASK 0xFFFF1F01U 4704#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_MASK 0x00000001U 4705#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_SHIFT 0U 4706#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WIDTH 1U 4707#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOCLR 0U 4708#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOSET 0U 4709#define LPDDR4__MC_RESERVED25__REG DENALI_CTL_274 4710#define LPDDR4__MC_RESERVED25__FLD LPDDR4__DENALI_CTL_274__MC_RESERVED25 4711 4712#define LPDDR4__DENALI_CTL_274__APREBIT_MASK 0x00001F00U 4713#define LPDDR4__DENALI_CTL_274__APREBIT_SHIFT 8U 4714#define LPDDR4__DENALI_CTL_274__APREBIT_WIDTH 5U 4715#define LPDDR4__APREBIT__REG DENALI_CTL_274 4716#define LPDDR4__APREBIT__FLD LPDDR4__DENALI_CTL_274__APREBIT 4717 4718#define LPDDR4__DENALI_CTL_274__AGE_COUNT_MASK 0x00FF0000U 4719#define LPDDR4__DENALI_CTL_274__AGE_COUNT_SHIFT 16U 4720#define LPDDR4__DENALI_CTL_274__AGE_COUNT_WIDTH 8U 4721#define LPDDR4__AGE_COUNT__REG DENALI_CTL_274 4722#define LPDDR4__AGE_COUNT__FLD LPDDR4__DENALI_CTL_274__AGE_COUNT 4723 4724#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_MASK 0xFF000000U 4725#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_SHIFT 24U 4726#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_WIDTH 8U 4727#define LPDDR4__COMMAND_AGE_COUNT__REG DENALI_CTL_274 4728#define LPDDR4__COMMAND_AGE_COUNT__FLD LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT 4729 4730#define LPDDR4__DENALI_CTL_275_READ_MASK 0x01010101U 4731#define LPDDR4__DENALI_CTL_275_WRITE_MASK 0x01010101U 4732#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_MASK 0x00000001U 4733#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_SHIFT 0U 4734#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WIDTH 1U 4735#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOCLR 0U 4736#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOSET 0U 4737#define LPDDR4__ADDR_CMP_EN__REG DENALI_CTL_275 4738#define LPDDR4__ADDR_CMP_EN__FLD LPDDR4__DENALI_CTL_275__ADDR_CMP_EN 4739 4740#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_MASK 0x00000100U 4741#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_SHIFT 8U 4742#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WIDTH 1U 4743#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOCLR 0U 4744#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOSET 0U 4745#define LPDDR4__ADDR_COLLISION_MPM_DIS__REG DENALI_CTL_275 4746#define LPDDR4__ADDR_COLLISION_MPM_DIS__FLD LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS 4747 4748#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_MASK 0x00010000U 4749#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_SHIFT 16U 4750#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WIDTH 1U 4751#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOCLR 0U 4752#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOSET 0U 4753#define LPDDR4__BANK_SPLIT_EN__REG DENALI_CTL_275 4754#define LPDDR4__BANK_SPLIT_EN__FLD LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN 4755 4756#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_MASK 0x01000000U 4757#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_SHIFT 24U 4758#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WIDTH 1U 4759#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOCLR 0U 4760#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOSET 0U 4761#define LPDDR4__PLACEMENT_EN__REG DENALI_CTL_275 4762#define LPDDR4__PLACEMENT_EN__FLD LPDDR4__DENALI_CTL_275__PLACEMENT_EN 4763 4764#define LPDDR4__DENALI_CTL_276_READ_MASK 0x01010101U 4765#define LPDDR4__DENALI_CTL_276_WRITE_MASK 0x01010101U 4766#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_MASK 0x00000001U 4767#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_SHIFT 0U 4768#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WIDTH 1U 4769#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOCLR 0U 4770#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOSET 0U 4771#define LPDDR4__PRIORITY_EN__REG DENALI_CTL_276 4772#define LPDDR4__PRIORITY_EN__FLD LPDDR4__DENALI_CTL_276__PRIORITY_EN 4773 4774#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_MASK 0x00000100U 4775#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_SHIFT 8U 4776#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WIDTH 1U 4777#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOCLR 0U 4778#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOSET 0U 4779#define LPDDR4__RW_SAME_EN__REG DENALI_CTL_276 4780#define LPDDR4__RW_SAME_EN__FLD LPDDR4__DENALI_CTL_276__RW_SAME_EN 4781 4782#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_MASK 0x00010000U 4783#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_SHIFT 16U 4784#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WIDTH 1U 4785#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOCLR 0U 4786#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOSET 0U 4787#define LPDDR4__RW_SAME_PAGE_EN__REG DENALI_CTL_276 4788#define LPDDR4__RW_SAME_PAGE_EN__FLD LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN 4789 4790#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_MASK 0x01000000U 4791#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_SHIFT 24U 4792#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WIDTH 1U 4793#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOCLR 0U 4794#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOSET 0U 4795#define LPDDR4__CS_SAME_EN__REG DENALI_CTL_276 4796#define LPDDR4__CS_SAME_EN__FLD LPDDR4__DENALI_CTL_276__CS_SAME_EN 4797 4798#define LPDDR4__DENALI_CTL_277_READ_MASK 0x011F0301U 4799#define LPDDR4__DENALI_CTL_277_WRITE_MASK 0x011F0301U 4800#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_MASK 0x00000001U 4801#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_SHIFT 0U 4802#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WIDTH 1U 4803#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOCLR 0U 4804#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOSET 0U 4805#define LPDDR4__W2R_SPLIT_EN__REG DENALI_CTL_277 4806#define LPDDR4__W2R_SPLIT_EN__FLD LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN 4807 4808#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_MASK 0x00000300U 4809#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_SHIFT 8U 4810#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_WIDTH 2U 4811#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__REG DENALI_CTL_277 4812#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__FLD LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT 4813 4814#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_MASK 0x001F0000U 4815#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_SHIFT 16U 4816#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_WIDTH 5U 4817#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__REG DENALI_CTL_277 4818#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__FLD LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE 4819 4820#define LPDDR4__DENALI_CTL_277__SWAP_EN_MASK 0x01000000U 4821#define LPDDR4__DENALI_CTL_277__SWAP_EN_SHIFT 24U 4822#define LPDDR4__DENALI_CTL_277__SWAP_EN_WIDTH 1U 4823#define LPDDR4__DENALI_CTL_277__SWAP_EN_WOCLR 0U 4824#define LPDDR4__DENALI_CTL_277__SWAP_EN_WOSET 0U 4825#define LPDDR4__SWAP_EN__REG DENALI_CTL_277 4826#define LPDDR4__SWAP_EN__FLD LPDDR4__DENALI_CTL_277__SWAP_EN 4827 4828#define LPDDR4__DENALI_CTL_278_READ_MASK 0x01030301U 4829#define LPDDR4__DENALI_CTL_278_WRITE_MASK 0x01030301U 4830#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_MASK 0x00000001U 4831#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_SHIFT 0U 4832#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WIDTH 1U 4833#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOCLR 0U 4834#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOSET 0U 4835#define LPDDR4__DISABLE_RD_INTERLEAVE__REG DENALI_CTL_278 4836#define LPDDR4__DISABLE_RD_INTERLEAVE__FLD LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE 4837 4838#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_MASK 0x00000300U 4839#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_SHIFT 8U 4840#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_WIDTH 2U 4841#define LPDDR4__INHIBIT_DRAM_CMD__REG DENALI_CTL_278 4842#define LPDDR4__INHIBIT_DRAM_CMD__FLD LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD 4843 4844#define LPDDR4__DENALI_CTL_278__CS_MAP_MASK 0x00030000U 4845#define LPDDR4__DENALI_CTL_278__CS_MAP_SHIFT 16U 4846#define LPDDR4__DENALI_CTL_278__CS_MAP_WIDTH 2U 4847#define LPDDR4__CS_MAP__REG DENALI_CTL_278 4848#define LPDDR4__CS_MAP__FLD LPDDR4__DENALI_CTL_278__CS_MAP 4849 4850#define LPDDR4__DENALI_CTL_278__REDUC_MASK 0x01000000U 4851#define LPDDR4__DENALI_CTL_278__REDUC_SHIFT 24U 4852#define LPDDR4__DENALI_CTL_278__REDUC_WIDTH 1U 4853#define LPDDR4__DENALI_CTL_278__REDUC_WOCLR 0U 4854#define LPDDR4__DENALI_CTL_278__REDUC_WOSET 0U 4855#define LPDDR4__REDUC__REG DENALI_CTL_278 4856#define LPDDR4__REDUC__FLD LPDDR4__DENALI_CTL_278__REDUC 4857 4858#define LPDDR4__DENALI_CTL_279_READ_MASK 0x0003FFFFU 4859#define LPDDR4__DENALI_CTL_279_WRITE_MASK 0x0003FFFFU 4860#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_MASK 0x0003FFFFU 4861#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_SHIFT 0U 4862#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_WIDTH 18U 4863#define LPDDR4__FAULT_FIFO_PROTECTION_EN__REG DENALI_CTL_279 4864#define LPDDR4__FAULT_FIFO_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN 4865 4866#define LPDDR4__DENALI_CTL_280_READ_MASK 0x0003FFFFU 4867#define LPDDR4__DENALI_CTL_280_WRITE_MASK 0x0003FFFFU 4868#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_MASK 0x0003FFFFU 4869#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_SHIFT 0U 4870#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_WIDTH 18U 4871#define LPDDR4__FAULT_FIFO_PROTECTION_STATUS__REG DENALI_CTL_280 4872#define LPDDR4__FAULT_FIFO_PROTECTION_STATUS__FLD LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS 4873 4874#define LPDDR4__DENALI_CTL_281_READ_MASK 0x0103FFFFU 4875#define LPDDR4__DENALI_CTL_281_WRITE_MASK 0x0103FFFFU 4876#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_MASK 0x0003FFFFU 4877#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_SHIFT 0U 4878#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_WIDTH 18U 4879#define LPDDR4__FAULT_FIFO_PROTECTION_INJECTION_EN__REG DENALI_CTL_281 4880#define LPDDR4__FAULT_FIFO_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN 4881 4882#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_MASK 0x01000000U 4883#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_SHIFT 24U 4884#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WIDTH 1U 4885#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WOCLR 0U 4886#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WOSET 0U 4887#define LPDDR4__WRITE_ADDR_CHAN_PARITY_EN__REG DENALI_CTL_281 4888#define LPDDR4__WRITE_ADDR_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN 4889 4890#define LPDDR4__DENALI_CTL_282_READ_MASK 0x01010103U 4891#define LPDDR4__DENALI_CTL_282_WRITE_MASK 0x01010103U 4892#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_MASK 0x00000003U 4893#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_SHIFT 0U 4894#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_WIDTH 2U 4895#define LPDDR4__WRITE_DATA_CHAN_PARITY_EN__REG DENALI_CTL_282 4896#define LPDDR4__WRITE_DATA_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN 4897 4898#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_MASK 0x00000100U 4899#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_SHIFT 8U 4900#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WIDTH 1U 4901#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WOCLR 0U 4902#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WOSET 0U 4903#define LPDDR4__WRITE_RESP_CHAN_PARITY_EN__REG DENALI_CTL_282 4904#define LPDDR4__WRITE_RESP_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN 4905 4906#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_MASK 0x00010000U 4907#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_SHIFT 16U 4908#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WIDTH 1U 4909#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOCLR 0U 4910#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOSET 0U 4911#define LPDDR4__READ_ADDR_CHAN_PARITY_EN__REG DENALI_CTL_282 4912#define LPDDR4__READ_ADDR_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN 4913 4914#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_MASK 0x01000000U 4915#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_SHIFT 24U 4916#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WIDTH 1U 4917#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOCLR 0U 4918#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOSET 0U 4919#define LPDDR4__READ_DATA_CHAN_PARITY_EN__REG DENALI_CTL_282 4920#define LPDDR4__READ_DATA_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN 4921 4922#define LPDDR4__DENALI_CTL_283_READ_MASK 0x01010101U 4923#define LPDDR4__DENALI_CTL_283_WRITE_MASK 0x01010101U 4924#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_MASK 0x00000001U 4925#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_SHIFT 0U 4926#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WIDTH 1U 4927#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOCLR 0U 4928#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOSET 0U 4929#define LPDDR4__MC_RESERVED26__REG DENALI_CTL_283 4930#define LPDDR4__MC_RESERVED26__FLD LPDDR4__DENALI_CTL_283__MC_RESERVED26 4931 4932#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_MASK 0x00000100U 4933#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_SHIFT 8U 4934#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WIDTH 1U 4935#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOCLR 0U 4936#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOSET 0U 4937#define LPDDR4__MC_RESERVED27__REG DENALI_CTL_283 4938#define LPDDR4__MC_RESERVED27__FLD LPDDR4__DENALI_CTL_283__MC_RESERVED27 4939 4940#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_MASK 0x00010000U 4941#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_SHIFT 16U 4942#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WIDTH 1U 4943#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WOCLR 0U 4944#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WOSET 0U 4945#define LPDDR4__WRITE_PARITY_ERR_BRESP_EN__REG DENALI_CTL_283 4946#define LPDDR4__WRITE_PARITY_ERR_BRESP_EN__FLD LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN 4947 4948#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_MASK 0x01000000U 4949#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_SHIFT 24U 4950#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WIDTH 1U 4951#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOCLR 0U 4952#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOSET 0U 4953#define LPDDR4__READ_PARITY_ERR_RRESP_EN__REG DENALI_CTL_283 4954#define LPDDR4__READ_PARITY_ERR_RRESP_EN__FLD LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN 4955 4956#define LPDDR4__DENALI_CTL_284_READ_MASK 0x01010101U 4957#define LPDDR4__DENALI_CTL_284_WRITE_MASK 0x01010101U 4958#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_MASK 0x00000001U 4959#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_SHIFT 0U 4960#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WIDTH 1U 4961#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WOCLR 0U 4962#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WOSET 0U 4963#define LPDDR4__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284 4964#define LPDDR4__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN 4965 4966#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_MASK 0x00000100U 4967#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_SHIFT 8U 4968#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WIDTH 1U 4969#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WOCLR 0U 4970#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WOSET 0U 4971#define LPDDR4__WRITE_DATA_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284 4972#define LPDDR4__WRITE_DATA_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN 4973 4974#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_MASK 0x00010000U 4975#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_SHIFT 16U 4976#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WIDTH 1U 4977#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WOCLR 0U 4978#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WOSET 0U 4979#define LPDDR4__WRITE_RESP_CHAN_CORRUPT_PARITY_EN__REG DENALI_CTL_284 4980#define LPDDR4__WRITE_RESP_CHAN_CORRUPT_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN 4981 4982#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_MASK 0x01000000U 4983#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_SHIFT 24U 4984#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WIDTH 1U 4985#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WOCLR 0U 4986#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WOSET 0U 4987#define LPDDR4__READ_ADDR_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284 4988#define LPDDR4__READ_ADDR_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN 4989 4990#define LPDDR4__DENALI_CTL_285_READ_MASK 0x01010101U 4991#define LPDDR4__DENALI_CTL_285_WRITE_MASK 0x01010101U 4992#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_MASK 0x00000001U 4993#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_SHIFT 0U 4994#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WIDTH 1U 4995#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WOCLR 0U 4996#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WOSET 0U 4997#define LPDDR4__READ_DATA_CHAN_CORRUPT_PARITY_EN__REG DENALI_CTL_285 4998#define LPDDR4__READ_DATA_CHAN_CORRUPT_PARITY_EN__FLD LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN 4999 5000#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_MASK 0x00000100U
5001#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_SHIFT 8U 5002#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WIDTH 1U 5003#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WOCLR 0U 5004#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WOSET 0U 5005#define LPDDR4__ECC_AXI_ERROR_RESPONSE_INHIBIT__REG DENALI_CTL_285 5006#define LPDDR4__ECC_AXI_ERROR_RESPONSE_INHIBIT__FLD LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT 5007 5008#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_MASK 0x00010000U 5009#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_SHIFT 16U 5010#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WIDTH 1U 5011#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WOCLR 0U 5012#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WOSET 0U 5013#define LPDDR4__WRITE_PARITY_ERR_CORRUPT_ECC_EN__REG DENALI_CTL_285 5014#define LPDDR4__WRITE_PARITY_ERR_CORRUPT_ECC_EN__FLD LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN 5015 5016#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_MASK 0x01000000U 5017#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_SHIFT 24U 5018#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WIDTH 1U 5019#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WOCLR 0U 5020#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WOSET 0U 5021#define LPDDR4__ENHANCED_PARITY_PROTECTION_EN__REG DENALI_CTL_285 5022#define LPDDR4__ENHANCED_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN 5023 5024#define LPDDR4__DENALI_CTL_286_READ_MASK 0x0F0F0F07U 5025#define LPDDR4__DENALI_CTL_286_WRITE_MASK 0x0F0F0F07U 5026#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_MASK 0x00000007U 5027#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_SHIFT 0U 5028#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_WIDTH 3U 5029#define LPDDR4__MEMDATA_RATIO_0__REG DENALI_CTL_286 5030#define LPDDR4__MEMDATA_RATIO_0__FLD LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0 5031 5032#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_MASK 0x00000F00U 5033#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_SHIFT 8U 5034#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_WIDTH 4U 5035#define LPDDR4__DEVICE0_BYTE0_CS0__REG DENALI_CTL_286 5036#define LPDDR4__DEVICE0_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0 5037 5038#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_MASK 0x000F0000U 5039#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_SHIFT 16U 5040#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_WIDTH 4U 5041#define LPDDR4__DEVICE1_BYTE0_CS0__REG DENALI_CTL_286 5042#define LPDDR4__DEVICE1_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0 5043 5044#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_MASK 0x0F000000U 5045#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_SHIFT 24U 5046#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_WIDTH 4U 5047#define LPDDR4__DEVICE2_BYTE0_CS0__REG DENALI_CTL_286 5048#define LPDDR4__DEVICE2_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0 5049 5050#define LPDDR4__DENALI_CTL_287_READ_MASK 0x0F0F070FU 5051#define LPDDR4__DENALI_CTL_287_WRITE_MASK 0x0F0F070FU 5052#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_MASK 0x0000000FU 5053#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_SHIFT 0U 5054#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_WIDTH 4U 5055#define LPDDR4__DEVICE3_BYTE0_CS0__REG DENALI_CTL_287 5056#define LPDDR4__DEVICE3_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0 5057 5058#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_MASK 0x00000700U 5059#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_SHIFT 8U 5060#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_WIDTH 3U 5061#define LPDDR4__MEMDATA_RATIO_1__REG DENALI_CTL_287 5062#define LPDDR4__MEMDATA_RATIO_1__FLD LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1 5063 5064#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_MASK 0x000F0000U 5065#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_SHIFT 16U 5066#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_WIDTH 4U 5067#define LPDDR4__DEVICE0_BYTE0_CS1__REG DENALI_CTL_287 5068#define LPDDR4__DEVICE0_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1 5069 5070#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_MASK 0x0F000000U 5071#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_SHIFT 24U 5072#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_WIDTH 4U 5073#define LPDDR4__DEVICE1_BYTE0_CS1__REG DENALI_CTL_287 5074#define LPDDR4__DEVICE1_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1 5075 5076#define LPDDR4__DENALI_CTL_288_READ_MASK 0x011F0F0FU 5077#define LPDDR4__DENALI_CTL_288_WRITE_MASK 0x011F0F0FU 5078#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_MASK 0x0000000FU 5079#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_SHIFT 0U 5080#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_WIDTH 4U 5081#define LPDDR4__DEVICE2_BYTE0_CS1__REG DENALI_CTL_288 5082#define LPDDR4__DEVICE2_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1 5083 5084#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_MASK 0x00000F00U 5085#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_SHIFT 8U 5086#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_WIDTH 4U 5087#define LPDDR4__DEVICE3_BYTE0_CS1__REG DENALI_CTL_288 5088#define LPDDR4__DEVICE3_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1 5089 5090#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_MASK 0x001F0000U 5091#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_SHIFT 16U 5092#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_WIDTH 5U 5093#define LPDDR4__Q_FULLNESS__REG DENALI_CTL_288 5094#define LPDDR4__Q_FULLNESS__FLD LPDDR4__DENALI_CTL_288__Q_FULLNESS 5095 5096#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_MASK 0x01000000U 5097#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_SHIFT 24U 5098#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WIDTH 1U 5099#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOCLR 0U 5100#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOSET 0U 5101#define LPDDR4__IN_ORDER_ACCEPT__REG DENALI_CTL_288 5102#define LPDDR4__IN_ORDER_ACCEPT__FLD LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT 5103 5104#define LPDDR4__DENALI_CTL_289_READ_MASK 0x01000103U 5105#define LPDDR4__DENALI_CTL_289_WRITE_MASK 0x01000103U 5106#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_MASK 0x00000003U 5107#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_SHIFT 0U 5108#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_WIDTH 2U 5109#define LPDDR4__WR_ORDER_REQ__REG DENALI_CTL_289 5110#define LPDDR4__WR_ORDER_REQ__FLD LPDDR4__DENALI_CTL_289__WR_ORDER_REQ 5111 5112#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_MASK 0x00000100U 5113#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_SHIFT 8U 5114#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WIDTH 1U 5115#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOCLR 0U 5116#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOSET 0U 5117#define LPDDR4__CONTROLLER_BUSY__REG DENALI_CTL_289 5118#define LPDDR4__CONTROLLER_BUSY__FLD LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY 5119 5120#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_MASK 0x00010000U 5121#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_SHIFT 16U 5122#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WIDTH 1U 5123#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOCLR 0U 5124#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOSET 0U 5125#define LPDDR4__CTRLUPD_REQ__REG DENALI_CTL_289 5126#define LPDDR4__CTRLUPD_REQ__FLD LPDDR4__DENALI_CTL_289__CTRLUPD_REQ 5127 5128#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_MASK 0x01000000U 5129#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_SHIFT 24U 5130#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U 5131#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U 5132#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOSET 0U 5133#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__REG DENALI_CTL_289 5134#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN 5135 5136#define LPDDR4__DENALI_CTL_290_READ_MASK 0x03030301U 5137#define LPDDR4__DENALI_CTL_290_WRITE_MASK 0x03030301U 5138#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_MASK 0x00000001U 5139#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_SHIFT 0U 5140#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WIDTH 1U 5141#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOCLR 0U 5142#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOSET 0U 5143#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__REG DENALI_CTL_290 5144#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__FLD LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE 5145 5146#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_MASK 0x00000300U 5147#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_SHIFT 8U 5148#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_WIDTH 2U 5149#define LPDDR4__PREAMBLE_SUPPORT_F0__REG DENALI_CTL_290 5150#define LPDDR4__PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0 5151 5152#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_MASK 0x00030000U 5153#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_SHIFT 16U 5154#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_WIDTH 2U 5155#define LPDDR4__PREAMBLE_SUPPORT_F1__REG DENALI_CTL_290 5156#define LPDDR4__PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1 5157 5158#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_MASK 0x03000000U 5159#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_SHIFT 24U 5160#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_WIDTH 2U 5161#define LPDDR4__PREAMBLE_SUPPORT_F2__REG DENALI_CTL_290 5162#define LPDDR4__PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2 5163 5164#define LPDDR4__DENALI_CTL_291_READ_MASK 0x1F010101U 5165#define LPDDR4__DENALI_CTL_291_WRITE_MASK 0x1F010101U 5166#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_MASK 0x00000001U 5167#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_SHIFT 0U 5168#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WIDTH 1U 5169#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOCLR 0U 5170#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOSET 0U 5171#define LPDDR4__RD_PREAMBLE_TRAINING_EN__REG DENALI_CTL_291 5172#define LPDDR4__RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN 5173 5174#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_MASK 0x00000100U 5175#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_SHIFT 8U 5176#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WIDTH 1U 5177#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOCLR 0U 5178#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOSET 0U 5179#define LPDDR4__WR_DBI_EN__REG DENALI_CTL_291 5180#define LPDDR4__WR_DBI_EN__FLD LPDDR4__DENALI_CTL_291__WR_DBI_EN 5181 5182#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_MASK 0x00010000U 5183#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_SHIFT 16U 5184#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WIDTH 1U 5185#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOCLR 0U 5186#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOSET 0U 5187#define LPDDR4__RD_DBI_EN__REG DENALI_CTL_291 5188#define LPDDR4__RD_DBI_EN__FLD LPDDR4__DENALI_CTL_291__RD_DBI_EN 5189 5190#define LPDDR4__DENALI_CTL_291__DFI_ERROR_MASK 0x1F000000U 5191#define LPDDR4__DENALI_CTL_291__DFI_ERROR_SHIFT 24U 5192#define LPDDR4__DENALI_CTL_291__DFI_ERROR_WIDTH 5U 5193#define LPDDR4__DFI_ERROR__REG DENALI_CTL_291 5194#define LPDDR4__DFI_ERROR__FLD LPDDR4__DENALI_CTL_291__DFI_ERROR 5195 5196#define LPDDR4__DENALI_CTL_292_READ_MASK 0x000FFFFFU 5197#define LPDDR4__DENALI_CTL_292_WRITE_MASK 0x000FFFFFU 5198#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_MASK 0x000FFFFFU 5199#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_SHIFT 0U 5200#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_WIDTH 20U 5201#define LPDDR4__DFI_ERROR_INFO__REG DENALI_CTL_292 5202#define LPDDR4__DFI_ERROR_INFO__FLD LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO 5203 5204#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_MASK 0x01000000U 5205#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_SHIFT 24U 5206#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WIDTH 1U 5207#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOCLR 0U 5208#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOSET 0U 5209#define LPDDR4__MC_RESERVED28__REG DENALI_CTL_292 5210#define LPDDR4__MC_RESERVED28__FLD LPDDR4__DENALI_CTL_292__MC_RESERVED28 5211 5212#define LPDDR4__DENALI_CTL_293_READ_MASK 0xFFFFFFFFU 5213#define LPDDR4__DENALI_CTL_293_WRITE_MASK 0xFFFFFFFFU 5214#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_MASK 0xFFFFFFFFU 5215#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_SHIFT 0U 5216#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_WIDTH 32U 5217#define LPDDR4__INT_STATUS_0__REG DENALI_CTL_293 5218#define LPDDR4__INT_STATUS_0__FLD LPDDR4__DENALI_CTL_293__INT_STATUS_0 5219 5220#define LPDDR4__DENALI_CTL_294_READ_MASK 0x00001FFFU 5221#define LPDDR4__DENALI_CTL_294_WRITE_MASK 0x00001FFFU 5222#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_MASK 0x00001FFFU 5223#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_SHIFT 0U 5224#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_WIDTH 13U 5225#define LPDDR4__INT_STATUS_1__REG DENALI_CTL_294 5226#define LPDDR4__INT_STATUS_1__FLD LPDDR4__DENALI_CTL_294__INT_STATUS_1 5227 5228#define LPDDR4__DENALI_CTL_295__INT_ACK_0_MASK 0xFFFFFFFFU 5229#define LPDDR4__DENALI_CTL_295__INT_ACK_0_SHIFT 0U 5230#define LPDDR4__DENALI_CTL_295__INT_ACK_0_WIDTH 32U 5231#define LPDDR4__INT_ACK_0__REG DENALI_CTL_295 5232#define LPDDR4__INT_ACK_0__FLD LPDDR4__DENALI_CTL_295__INT_ACK_0 5233 5234#define LPDDR4__DENALI_CTL_296__INT_ACK_1_MASK 0x00000FFFU 5235#define LPDDR4__DENALI_CTL_296__INT_ACK_1_SHIFT 0U 5236#define LPDDR4__DENALI_CTL_296__INT_ACK_1_WIDTH 12U 5237#define LPDDR4__INT_ACK_1__REG DENALI_CTL_296 5238#define LPDDR4__INT_ACK_1__FLD LPDDR4__DENALI_CTL_296__INT_ACK_1 5239 5240#define LPDDR4__DENALI_CTL_297_READ_MASK 0xFFFFFFFFU 5241#define LPDDR4__DENALI_CTL_297_WRITE_MASK 0xFFFFFFFFU 5242#define LPDDR4__DENALI_CTL_297__INT_MASK_0_MASK 0xFFFFFFFFU 5243#define LPDDR4__DENALI_CTL_297__INT_MASK_0_SHIFT 0U 5244#define LPDDR4__DENALI_CTL_297__INT_MASK_0_WIDTH 32U 5245#define LPDDR4__INT_MASK_0__REG DENALI_CTL_297 5246#define LPDDR4__INT_MASK_0__FLD LPDDR4__DENALI_CTL_297__INT_MASK_0 5247 5248#define LPDDR4__DENALI_CTL_298_READ_MASK 0x00001FFFU 5249#define LPDDR4__DENALI_CTL_298_WRITE_MASK 0x00001FFFU 5250#define LPDDR4__DENALI_CTL_298__INT_MASK_1_MASK 0x00001FFFU 5251#define LPDDR4__DENALI_CTL_298__INT_MASK_1_SHIFT 0U 5252#define LPDDR4__DENALI_CTL_298__INT_MASK_1_WIDTH 13U 5253#define LPDDR4__INT_MASK_1__REG DENALI_CTL_298 5254#define LPDDR4__INT_MASK_1__FLD LPDDR4__DENALI_CTL_298__INT_MASK_1 5255 5256#define LPDDR4__DENALI_CTL_299_READ_MASK 0xFFFFFFFFU 5257#define LPDDR4__DENALI_CTL_299_WRITE_MASK 0xFFFFFFFFU 5258#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_MASK 0xFFFFFFFFU 5259#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_SHIFT 0U 5260#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_WIDTH 32U 5261#define LPDDR4__OUT_OF_RANGE_ADDR_0__REG DENALI_CTL_299 5262#define LPDDR4__OUT_OF_RANGE_ADDR_0__FLD LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0 5263 5264#define LPDDR4__DENALI_CTL_300_READ_MASK 0x7F0FFF07U 5265#define LPDDR4__DENALI_CTL_300_WRITE_MASK 0x7F0FFF07U 5266#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_MASK 0x00000007U 5267#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_SHIFT 0U 5268#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_WIDTH 3U 5269#define LPDDR4__OUT_OF_RANGE_ADDR_1__REG DENALI_CTL_300 5270#define LPDDR4__OUT_OF_RANGE_ADDR_1__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1 5271 5272#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_MASK 0x000FFF00U 5273#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_SHIFT 8U 5274#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_WIDTH 12U 5275#define LPDDR4__OUT_OF_RANGE_LENGTH__REG DENALI_CTL_300 5276#define LPDDR4__OUT_OF_RANGE_LENGTH__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH 5277 5278#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_MASK 0x7F000000U 5279#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_SHIFT 24U 5280#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_WIDTH 7U 5281#define LPDDR4__OUT_OF_RANGE_TYPE__REG DENALI_CTL_300 5282#define LPDDR4__OUT_OF_RANGE_TYPE__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE 5283 5284#define LPDDR4__DENALI_CTL_301_READ_MASK 0x0000003FU 5285#define LPDDR4__DENALI_CTL_301_WRITE_MASK 0x0000003FU 5286#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_MASK 0x0000003FU 5287#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_SHIFT 0U 5288#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_WIDTH 6U 5289#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__REG DENALI_CTL_301 5290#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__FLD LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID 5291 5292#define LPDDR4__DENALI_CTL_302_READ_MASK 0xFFFFFFFFU 5293#define LPDDR4__DENALI_CTL_302_WRITE_MASK 0xFFFFFFFFU 5294#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_MASK 0xFFFFFFFFU 5295#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_SHIFT 0U 5296#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_WIDTH 32U 5297#define LPDDR4__BIST_EXP_DATA_0__REG DENALI_CTL_302 5298#define LPDDR4__BIST_EXP_DATA_0__FLD LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0 5299 5300#define LPDDR4__DENALI_CTL_303_READ_MASK 0xFFFFFFFFU 5301#define LPDDR4__DENALI_CTL_303_WRITE_MASK 0xFFFFFFFFU 5302#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_MASK 0xFFFFFFFFU 5303#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_SHIFT 0U 5304#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_WIDTH 32U 5305#define LPDDR4__BIST_EXP_DATA_1__REG DENALI_CTL_303 5306#define LPDDR4__BIST_EXP_DATA_1__FLD LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1 5307 5308#define LPDDR4__DENALI_CTL_304_READ_MASK 0xFFFFFFFFU 5309#define LPDDR4__DENALI_CTL_304_WRITE_MASK 0xFFFFFFFFU 5310#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_MASK 0xFFFFFFFFU 5311#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_SHIFT 0U 5312#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_WIDTH 32U 5313#define LPDDR4__BIST_EXP_DATA_2__REG DENALI_CTL_304 5314#define LPDDR4__BIST_EXP_DATA_2__FLD LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2 5315 5316#define LPDDR4__DENALI_CTL_305_READ_MASK 0xFFFFFFFFU 5317#define LPDDR4__DENALI_CTL_305_WRITE_MASK 0xFFFFFFFFU 5318#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_MASK 0xFFFFFFFFU 5319#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_SHIFT 0U 5320#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_WIDTH 32U 5321#define LPDDR4__BIST_EXP_DATA_3__REG DENALI_CTL_305 5322#define LPDDR4__BIST_EXP_DATA_3__FLD LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3 5323 5324#define LPDDR4__DENALI_CTL_306_READ_MASK 0xFFFFFFFFU 5325#define LPDDR4__DENALI_CTL_306_WRITE_MASK 0xFFFFFFFFU 5326#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU 5327#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_SHIFT 0U 5328#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_WIDTH 32U 5329#define LPDDR4__BIST_FAIL_DATA_0__REG DENALI_CTL_306 5330#define LPDDR4__BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0 5331 5332#define LPDDR4__DENALI_CTL_307_READ_MASK 0xFFFFFFFFU 5333#define LPDDR4__DENALI_CTL_307_WRITE_MASK 0xFFFFFFFFU 5334#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU 5335#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_SHIFT 0U 5336#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_WIDTH 32U 5337#define LPDDR4__BIST_FAIL_DATA_1__REG DENALI_CTL_307 5338#define LPDDR4__BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1 5339 5340#define LPDDR4__DENALI_CTL_308_READ_MASK 0xFFFFFFFFU 5341#define LPDDR4__DENALI_CTL_308_WRITE_MASK 0xFFFFFFFFU 5342#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_MASK 0xFFFFFFFFU 5343#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_SHIFT 0U 5344#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_WIDTH 32U 5345#define LPDDR4__BIST_FAIL_DATA_2__REG DENALI_CTL_308 5346#define LPDDR4__BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2 5347 5348#define LPDDR4__DENALI_CTL_309_READ_MASK 0xFFFFFFFFU 5349#define LPDDR4__DENALI_CTL_309_WRITE_MASK 0xFFFFFFFFU 5350#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_MASK 0xFFFFFFFFU 5351#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_SHIFT 0U 5352#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_WIDTH 32U 5353#define LPDDR4__BIST_FAIL_DATA_3__REG DENALI_CTL_309 5354#define LPDDR4__BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3 5355 5356#define LPDDR4__DENALI_CTL_310_READ_MASK 0xFFFFFFFFU 5357#define LPDDR4__DENALI_CTL_310_WRITE_MASK 0xFFFFFFFFU 5358#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU 5359#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_SHIFT 0U 5360#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_WIDTH 32U 5361#define LPDDR4__BIST_FAIL_ADDR_0__REG DENALI_CTL_310 5362#define LPDDR4__BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0 5363 5364#define LPDDR4__DENALI_CTL_311_READ_MASK 0x00000007U 5365#define LPDDR4__DENALI_CTL_311_WRITE_MASK 0x00000007U 5366#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_MASK 0x00000007U 5367#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_SHIFT 0U 5368#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_WIDTH 3U 5369#define LPDDR4__BIST_FAIL_ADDR_1__REG DENALI_CTL_311 5370#define LPDDR4__BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1 5371 5372#define LPDDR4__DENALI_CTL_312_READ_MASK 0xFFFFFFFFU 5373#define LPDDR4__DENALI_CTL_312_WRITE_MASK 0xFFFFFFFFU 5374#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_MASK 0xFFFFFFFFU 5375#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_SHIFT 0U 5376#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_WIDTH 32U 5377#define LPDDR4__PORT_CMD_ERROR_ADDR_0__REG DENALI_CTL_312 5378#define LPDDR4__PORT_CMD_ERROR_ADDR_0__FLD LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0 5379 5380#define LPDDR4__DENALI_CTL_313_READ_MASK 0x03033F07U 5381#define LPDDR4__DENALI_CTL_313_WRITE_MASK 0x03033F07U 5382#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_MASK 0x00000007U 5383#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_SHIFT 0U 5384#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_WIDTH 3U 5385#define LPDDR4__PORT_CMD_ERROR_ADDR_1__REG DENALI_CTL_313 5386#define LPDDR4__PORT_CMD_ERROR_ADDR_1__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1 5387 5388#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_MASK 0x00003F00U 5389#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_SHIFT 8U 5390#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_WIDTH 6U 5391#define LPDDR4__PORT_CMD_ERROR_ID__REG DENALI_CTL_313 5392#define LPDDR4__PORT_CMD_ERROR_ID__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID 5393 5394#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_MASK 0x00030000U 5395#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_SHIFT 16U 5396#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_WIDTH 2U 5397#define LPDDR4__PORT_CMD_ERROR_TYPE__REG DENALI_CTL_313 5398#define LPDDR4__PORT_CMD_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE 5399 5400#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_MASK 0x03000000U 5401#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_SHIFT 24U 5402#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_WIDTH 2U 5403#define LPDDR4__ODT_RD_MAP_CS0__REG DENALI_CTL_313 5404#define LPDDR4__ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0 5405 5406#define LPDDR4__DENALI_CTL_314_READ_MASK 0xFF030303U 5407#define LPDDR4__DENALI_CTL_314_WRITE_MASK 0xFF030303U 5408#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_MASK 0x00000003U 5409#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_SHIFT 0U 5410#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_WIDTH 2U 5411#define LPDDR4__ODT_WR_MAP_CS0__REG DENALI_CTL_314 5412#define LPDDR4__ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0 5413 5414#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_MASK 0x00000300U 5415#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_SHIFT 8U 5416#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_WIDTH 2U 5417#define LPDDR4__ODT_RD_MAP_CS1__REG DENALI_CTL_314 5418#define LPDDR4__ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1 5419 5420#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_MASK 0x00030000U 5421#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_SHIFT 16U 5422#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_WIDTH 2U 5423#define LPDDR4__ODT_WR_MAP_CS1__REG DENALI_CTL_314 5424#define LPDDR4__ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1 5425 5426#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_MASK 0xFF000000U 5427#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_SHIFT 24U 5428#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_WIDTH 8U 5429#define LPDDR4__TODTL_2CMD_F0__REG DENALI_CTL_314 5430#define LPDDR4__TODTL_2CMD_F0__FLD LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0 5431 5432#define LPDDR4__DENALI_CTL_315_READ_MASK 0x0FFF0F0FU 5433#define LPDDR4__DENALI_CTL_315_WRITE_MASK 0x0FFF0F0FU 5434#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_MASK 0x0000000FU 5435#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_SHIFT 0U 5436#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_WIDTH 4U 5437#define LPDDR4__TODTH_WR_F0__REG DENALI_CTL_315 5438#define LPDDR4__TODTH_WR_F0__FLD LPDDR4__DENALI_CTL_315__TODTH_WR_F0 5439 5440#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_MASK 0x00000F00U 5441#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_SHIFT 8U 5442#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_WIDTH 4U 5443#define LPDDR4__TODTH_RD_F0__REG DENALI_CTL_315 5444#define LPDDR4__TODTH_RD_F0__FLD LPDDR4__DENALI_CTL_315__TODTH_RD_F0 5445 5446#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_MASK 0x00FF0000U 5447#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_SHIFT 16U 5448#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_WIDTH 8U 5449#define LPDDR4__TODTL_2CMD_F1__REG DENALI_CTL_315 5450#define LPDDR4__TODTL_2CMD_F1__FLD LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1 5451 5452#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_MASK 0x0F000000U 5453#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_SHIFT 24U 5454#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_WIDTH 4U 5455#define LPDDR4__TODTH_WR_F1__REG DENALI_CTL_315 5456#define LPDDR4__TODTH_WR_F1__FLD LPDDR4__DENALI_CTL_315__TODTH_WR_F1 5457 5458#define LPDDR4__DENALI_CTL_316_READ_MASK 0x0F0FFF0FU 5459#define LPDDR4__DENALI_CTL_316_WRITE_MASK 0x0F0FFF0FU 5460#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_MASK 0x0000000FU 5461#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_SHIFT 0U 5462#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_WIDTH 4U 5463#define LPDDR4__TODTH_RD_F1__REG DENALI_CTL_316 5464#define LPDDR4__TODTH_RD_F1__FLD LPDDR4__DENALI_CTL_316__TODTH_RD_F1 5465 5466#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_MASK 0x0000FF00U 5467#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_SHIFT 8U 5468#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_WIDTH 8U 5469#define LPDDR4__TODTL_2CMD_F2__REG DENALI_CTL_316 5470#define LPDDR4__TODTL_2CMD_F2__FLD LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2 5471 5472#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_MASK 0x000F0000U 5473#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_SHIFT 16U 5474#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_WIDTH 4U 5475#define LPDDR4__TODTH_WR_F2__REG DENALI_CTL_316 5476#define LPDDR4__TODTH_WR_F2__FLD LPDDR4__DENALI_CTL_316__TODTH_WR_F2 5477 5478#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_MASK 0x0F000000U 5479#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_SHIFT 24U 5480#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_WIDTH 4U 5481#define LPDDR4__TODTH_RD_F2__REG DENALI_CTL_316 5482#define LPDDR4__TODTH_RD_F2__FLD LPDDR4__DENALI_CTL_316__TODTH_RD_F2 5483 5484#define LPDDR4__DENALI_CTL_317_READ_MASK 0x01010101U 5485#define LPDDR4__DENALI_CTL_317_WRITE_MASK 0x01010101U 5486#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_MASK 0x00000001U 5487#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_SHIFT 0U 5488#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WIDTH 1U 5489#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOCLR 0U 5490#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOSET 0U 5491#define LPDDR4__ODT_EN_F0__REG DENALI_CTL_317 5492#define LPDDR4__ODT_EN_F0__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F0 5493 5494#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_MASK 0x00000100U 5495#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_SHIFT 8U 5496#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WIDTH 1U 5497#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOCLR 0U 5498#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOSET 0U 5499#define LPDDR4__ODT_EN_F1__REG DENALI_CTL_317 5500#define LPDDR4__ODT_EN_F1__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F1 5501 5502#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_MASK 0x00010000U 5503#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_SHIFT 16U 5504#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WIDTH 1U 5505#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOCLR 0U 5506#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOSET 0U 5507#define LPDDR4__ODT_EN_F2__REG DENALI_CTL_317 5508#define LPDDR4__ODT_EN_F2__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F2 5509 5510#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_MASK 0x01000000U 5511#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_SHIFT 24U 5512#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WIDTH 1U 5513#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOCLR 0U 5514#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOSET 0U 5515#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__REG DENALI_CTL_317 5516#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__FLD LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD 5517 5518#define LPDDR4__DENALI_CTL_318_READ_MASK 0x3F3F3F3FU 5519#define LPDDR4__DENALI_CTL_318_WRITE_MASK 0x3F3F3F3FU 5520#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_MASK 0x0000003FU 5521#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_SHIFT 0U 5522#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_WIDTH 6U 5523#define LPDDR4__WR_TO_ODTH_F0__REG DENALI_CTL_318 5524#define LPDDR4__WR_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0 5525 5526#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_MASK 0x00003F00U 5527#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_SHIFT 8U 5528#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_WIDTH 6U 5529#define LPDDR4__WR_TO_ODTH_F1__REG DENALI_CTL_318 5530#define LPDDR4__WR_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1 5531 5532#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_MASK 0x003F0000U 5533#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_SHIFT 16U 5534#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_WIDTH 6U 5535#define LPDDR4__WR_TO_ODTH_F2__REG DENALI_CTL_318 5536#define LPDDR4__WR_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2 5537 5538#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_MASK 0x3F000000U 5539#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_SHIFT 24U 5540#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_WIDTH 6U 5541#define LPDDR4__RD_TO_ODTH_F0__REG DENALI_CTL_318 5542#define LPDDR4__RD_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0 5543 5544#define LPDDR4__DENALI_CTL_319_READ_MASK 0x1F1F3F3FU 5545#define LPDDR4__DENALI_CTL_319_WRITE_MASK 0x1F1F3F3FU 5546#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_MASK 0x0000003FU 5547#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_SHIFT 0U 5548#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_WIDTH 6U 5549#define LPDDR4__RD_TO_ODTH_F1__REG DENALI_CTL_319 5550#define LPDDR4__RD_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1 5551 5552#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_MASK 0x00003F00U 5553#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_SHIFT 8U 5554#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_WIDTH 6U 5555#define LPDDR4__RD_TO_ODTH_F2__REG DENALI_CTL_319 5556#define LPDDR4__RD_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2 5557 5558#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_MASK 0x001F0000U 5559#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_SHIFT 16U 5560#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_WIDTH 5U 5561#define LPDDR4__RW2MRW_DLY_F0__REG DENALI_CTL_319 5562#define LPDDR4__RW2MRW_DLY_F0__FLD LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0 5563 5564#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_MASK 0x1F000000U 5565#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_SHIFT 24U 5566#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_WIDTH 5U 5567#define LPDDR4__RW2MRW_DLY_F1__REG DENALI_CTL_319 5568#define LPDDR4__RW2MRW_DLY_F1__FLD LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1 5569 5570#define LPDDR4__DENALI_CTL_320_READ_MASK 0x1F1F1F1FU 5571#define LPDDR4__DENALI_CTL_320_WRITE_MASK 0x1F1F1F1FU 5572#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_MASK 0x0000001FU 5573#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_SHIFT 0U 5574#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_WIDTH 5U 5575#define LPDDR4__RW2MRW_DLY_F2__REG DENALI_CTL_320 5576#define LPDDR4__RW2MRW_DLY_F2__FLD LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2 5577 5578#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_MASK 0x00001F00U 5579#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_SHIFT 8U 5580#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_WIDTH 5U 5581#define LPDDR4__R2R_DIFFCS_DLY_F0__REG DENALI_CTL_320 5582#define LPDDR4__R2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0 5583 5584#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_MASK 0x001F0000U 5585#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_SHIFT 16U 5586#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_WIDTH 5U 5587#define LPDDR4__R2W_DIFFCS_DLY_F0__REG DENALI_CTL_320 5588#define LPDDR4__R2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0 5589 5590#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_MASK 0x1F000000U 5591#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_SHIFT 24U 5592#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_WIDTH 5U 5593#define LPDDR4__W2R_DIFFCS_DLY_F0__REG DENALI_CTL_320 5594#define LPDDR4__W2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0 5595 5596#define LPDDR4__DENALI_CTL_321_READ_MASK 0x1F1F1F1FU 5597#define LPDDR4__DENALI_CTL_321_WRITE_MASK 0x1F1F1F1FU 5598#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_MASK 0x0000001FU 5599#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_SHIFT 0U 5600#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_WIDTH 5U 5601#define LPDDR4__W2W_DIFFCS_DLY_F0__REG DENALI_CTL_321 5602#define LPDDR4__W2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0 5603 5604#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_MASK 0x00001F00U 5605#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_SHIFT 8U 5606#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_WIDTH 5U 5607#define LPDDR4__R2R_DIFFCS_DLY_F1__REG DENALI_CTL_321 5608#define LPDDR4__R2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1 5609 5610#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_MASK 0x001F0000U 5611#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_SHIFT 16U 5612#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_WIDTH 5U 5613#define LPDDR4__R2W_DIFFCS_DLY_F1__REG DENALI_CTL_321 5614#define LPDDR4__R2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1 5615 5616#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_MASK 0x1F000000U 5617#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_SHIFT 24U 5618#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_WIDTH 5U 5619#define LPDDR4__W2R_DIFFCS_DLY_F1__REG DENALI_CTL_321 5620#define LPDDR4__W2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1 5621 5622#define LPDDR4__DENALI_CTL_322_READ_MASK 0x1F1F1F1FU 5623#define LPDDR4__DENALI_CTL_322_WRITE_MASK 0x1F1F1F1FU 5624#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_MASK 0x0000001FU 5625#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_SHIFT 0U 5626#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_WIDTH 5U 5627#define LPDDR4__W2W_DIFFCS_DLY_F1__REG DENALI_CTL_322 5628#define LPDDR4__W2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1 5629 5630#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_MASK 0x00001F00U 5631#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_SHIFT 8U 5632#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_WIDTH 5U 5633#define LPDDR4__R2R_DIFFCS_DLY_F2__REG DENALI_CTL_322 5634#define LPDDR4__R2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2 5635 5636#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_MASK 0x001F0000U 5637#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_SHIFT 16U 5638#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_WIDTH 5U 5639#define LPDDR4__R2W_DIFFCS_DLY_F2__REG DENALI_CTL_322 5640#define LPDDR4__R2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2 5641 5642#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_MASK 0x1F000000U 5643#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_SHIFT 24U 5644#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_WIDTH 5U 5645#define LPDDR4__W2R_DIFFCS_DLY_F2__REG DENALI_CTL_322 5646#define LPDDR4__W2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2 5647 5648#define LPDDR4__DENALI_CTL_323_READ_MASK 0x1F1F1F1FU 5649#define LPDDR4__DENALI_CTL_323_WRITE_MASK 0x1F1F1F1FU 5650#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_MASK 0x0000001FU 5651#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_SHIFT 0U 5652#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_WIDTH 5U 5653#define LPDDR4__W2W_DIFFCS_DLY_F2__REG DENALI_CTL_323 5654#define LPDDR4__W2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2 5655 5656#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_MASK 0x00001F00U 5657#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_SHIFT 8U 5658#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_WIDTH 5U 5659#define LPDDR4__R2R_SAMECS_DLY__REG DENALI_CTL_323 5660#define LPDDR4__R2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY 5661 5662#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_MASK 0x001F0000U 5663#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_SHIFT 16U 5664#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_WIDTH 5U 5665#define LPDDR4__R2W_SAMECS_DLY_F0__REG DENALI_CTL_323 5666#define LPDDR4__R2W_SAMECS_DLY_F0__FLD LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0 5667 5668#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_MASK 0x1F000000U 5669#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_SHIFT 24U 5670#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_WIDTH 5U 5671#define LPDDR4__R2W_SAMECS_DLY_F1__REG DENALI_CTL_323 5672#define LPDDR4__R2W_SAMECS_DLY_F1__FLD LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1 5673 5674#define LPDDR4__DENALI_CTL_324_READ_MASK 0x0F1F1F1FU 5675#define LPDDR4__DENALI_CTL_324_WRITE_MASK 0x0F1F1F1FU 5676#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_MASK 0x0000001FU 5677#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_SHIFT 0U 5678#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_WIDTH 5U 5679#define LPDDR4__R2W_SAMECS_DLY_F2__REG DENALI_CTL_324 5680#define LPDDR4__R2W_SAMECS_DLY_F2__FLD LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2 5681 5682#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_MASK 0x00001F00U 5683#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_SHIFT 8U 5684#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_WIDTH 5U 5685#define LPDDR4__W2R_SAMECS_DLY__REG DENALI_CTL_324 5686#define LPDDR4__W2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY 5687 5688#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_MASK 0x001F0000U 5689#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_SHIFT 16U 5690#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_WIDTH 5U 5691#define LPDDR4__W2W_SAMECS_DLY__REG DENALI_CTL_324 5692#define LPDDR4__W2W_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY 5693 5694#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_MASK 0x0F000000U 5695#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_SHIFT 24U 5696#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_WIDTH 4U 5697#define LPDDR4__TDQSCK_MAX_F0__REG DENALI_CTL_324 5698#define LPDDR4__TDQSCK_MAX_F0__FLD LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0 5699 5700#define LPDDR4__DENALI_CTL_325_READ_MASK 0x0F070F07U 5701#define LPDDR4__DENALI_CTL_325_WRITE_MASK 0x0F070F07U 5702#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_MASK 0x00000007U 5703#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_SHIFT 0U 5704#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_WIDTH 3U 5705#define LPDDR4__TDQSCK_MIN_F0__REG DENALI_CTL_325 5706#define LPDDR4__TDQSCK_MIN_F0__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0 5707 5708#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_MASK 0x00000F00U 5709#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_SHIFT 8U 5710#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_WIDTH 4U 5711#define LPDDR4__TDQSCK_MAX_F1__REG DENALI_CTL_325 5712#define LPDDR4__TDQSCK_MAX_F1__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1 5713 5714#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_MASK 0x00070000U 5715#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_SHIFT 16U 5716#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_WIDTH 3U 5717#define LPDDR4__TDQSCK_MIN_F1__REG DENALI_CTL_325 5718#define LPDDR4__TDQSCK_MIN_F1__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1 5719 5720#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_MASK 0x0F000000U 5721#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_SHIFT 24U 5722#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_WIDTH 4U 5723#define LPDDR4__TDQSCK_MAX_F2__REG DENALI_CTL_325 5724#define LPDDR4__TDQSCK_MAX_F2__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2 5725 5726#define LPDDR4__DENALI_CTL_326_READ_MASK 0x00000707U 5727#define LPDDR4__DENALI_CTL_326_WRITE_MASK 0x00000707U 5728#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_MASK 0x00000007U 5729#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_SHIFT 0U 5730#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_WIDTH 3U 5731#define LPDDR4__TDQSCK_MIN_F2__REG DENALI_CTL_326 5732#define LPDDR4__TDQSCK_MIN_F2__FLD LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2 5733 5734#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_MASK 0x00000700U 5735#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_SHIFT 8U 5736#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_WIDTH 3U 5737#define LPDDR4__SW_LEVELING_MODE__REG DENALI_CTL_326 5738#define LPDDR4__SW_LEVELING_MODE__FLD LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE 5739 5740#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_MASK 0x00010000U 5741#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_SHIFT 16U 5742#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WIDTH 1U 5743#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOCLR 0U 5744#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOSET 0U 5745#define LPDDR4__SWLVL_LOAD__REG DENALI_CTL_326 5746#define LPDDR4__SWLVL_LOAD__FLD LPDDR4__DENALI_CTL_326__SWLVL_LOAD 5747 5748#define LPDDR4__DENALI_CTL_326__SWLVL_START_MASK 0x01000000U 5749#define LPDDR4__DENALI_CTL_326__SWLVL_START_SHIFT 24U 5750#define LPDDR4__DENALI_CTL_326__SWLVL_START_WIDTH 1U 5751#define LPDDR4__DENALI_CTL_326__SWLVL_START_WOCLR 0U 5752#define LPDDR4__DENALI_CTL_326__SWLVL_START_WOSET 0U 5753#define LPDDR4__SWLVL_START__REG DENALI_CTL_326 5754#define LPDDR4__SWLVL_START__FLD LPDDR4__DENALI_CTL_326__SWLVL_START 5755 5756#define LPDDR4__DENALI_CTL_327_READ_MASK 0x01010100U 5757#define LPDDR4__DENALI_CTL_327_WRITE_MASK 0x01010100U 5758#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_MASK 0x00000001U 5759#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_SHIFT 0U 5760#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WIDTH 1U 5761#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOCLR 0U 5762#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOSET 0U 5763#define LPDDR4__SWLVL_EXIT__REG DENALI_CTL_327 5764#define LPDDR4__SWLVL_EXIT__FLD LPDDR4__DENALI_CTL_327__SWLVL_EXIT 5765 5766#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_MASK 0x00000100U 5767#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_SHIFT 8U 5768#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WIDTH 1U 5769#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOCLR 0U 5770#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOSET 0U 5771#define LPDDR4__SWLVL_OP_DONE__REG DENALI_CTL_327 5772#define LPDDR4__SWLVL_OP_DONE__FLD LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE 5773 5774#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_MASK 0x00010000U 5775#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_SHIFT 16U 5776#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WIDTH 1U 5777#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOCLR 0U 5778#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOSET 0U 5779#define LPDDR4__SWLVL_RESP_0__REG DENALI_CTL_327 5780#define LPDDR4__SWLVL_RESP_0__FLD LPDDR4__DENALI_CTL_327__SWLVL_RESP_0 5781 5782#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_MASK 0x01000000U 5783#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_SHIFT 24U 5784#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WIDTH 1U 5785#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOCLR 0U 5786#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOSET 0U 5787#define LPDDR4__SWLVL_RESP_1__REG DENALI_CTL_327 5788#define LPDDR4__SWLVL_RESP_1__FLD LPDDR4__DENALI_CTL_327__SWLVL_RESP_1 5789 5790#define LPDDR4__DENALI_CTL_328_READ_MASK 0x00010101U 5791#define LPDDR4__DENALI_CTL_328_WRITE_MASK 0x00010101U 5792#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_MASK 0x00000001U 5793#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_SHIFT 0U 5794#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WIDTH 1U 5795#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOCLR 0U 5796#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOSET 0U 5797#define LPDDR4__SWLVL_RESP_2__REG DENALI_CTL_328 5798#define LPDDR4__SWLVL_RESP_2__FLD LPDDR4__DENALI_CTL_328__SWLVL_RESP_2 5799 5800#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_MASK 0x00000100U 5801#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_SHIFT 8U 5802#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WIDTH 1U 5803#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOCLR 0U 5804#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOSET 0U 5805#define LPDDR4__SWLVL_RESP_3__REG DENALI_CTL_328 5806#define LPDDR4__SWLVL_RESP_3__FLD LPDDR4__DENALI_CTL_328__SWLVL_RESP_3 5807 5808#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_MASK 0x00010000U 5809#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_SHIFT 16U 5810#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WIDTH 1U 5811#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOCLR 0U 5812#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOSET 0U 5813#define LPDDR4__PHYUPD_APPEND_EN__REG DENALI_CTL_328 5814#define LPDDR4__PHYUPD_APPEND_EN__FLD LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN 5815 5816#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_MASK 0x01000000U 5817#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_SHIFT 24U 5818#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WIDTH 1U 5819#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOCLR 0U 5820#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOSET 0U 5821#define LPDDR4__WRLVL_REQ__REG DENALI_CTL_328 5822#define LPDDR4__WRLVL_REQ__FLD LPDDR4__DENALI_CTL_328__WRLVL_REQ 5823 5824#define LPDDR4__DENALI_CTL_329_READ_MASK 0x013F3F01U 5825#define LPDDR4__DENALI_CTL_329_WRITE_MASK 0x013F3F01U 5826#define LPDDR4__DENALI_CTL_329__WRLVL_CS_MASK 0x00000001U 5827#define LPDDR4__DENALI_CTL_329__WRLVL_CS_SHIFT 0U 5828#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WIDTH 1U 5829#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOCLR 0U 5830#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOSET 0U 5831#define LPDDR4__WRLVL_CS__REG DENALI_CTL_329 5832#define LPDDR4__WRLVL_CS__FLD LPDDR4__DENALI_CTL_329__WRLVL_CS 5833 5834#define LPDDR4__DENALI_CTL_329__WLDQSEN_MASK 0x00003F00U 5835#define LPDDR4__DENALI_CTL_329__WLDQSEN_SHIFT 8U 5836#define LPDDR4__DENALI_CTL_329__WLDQSEN_WIDTH 6U 5837#define LPDDR4__WLDQSEN__REG DENALI_CTL_329 5838#define LPDDR4__WLDQSEN__FLD LPDDR4__DENALI_CTL_329__WLDQSEN 5839 5840#define LPDDR4__DENALI_CTL_329__WLMRD_MASK 0x003F0000U 5841#define LPDDR4__DENALI_CTL_329__WLMRD_SHIFT 16U 5842#define LPDDR4__DENALI_CTL_329__WLMRD_WIDTH 6U 5843#define LPDDR4__WLMRD__REG DENALI_CTL_329 5844#define LPDDR4__WLMRD__FLD LPDDR4__DENALI_CTL_329__WLMRD 5845 5846#define LPDDR4__DENALI_CTL_329__WRLVL_EN_MASK 0x01000000U 5847#define LPDDR4__DENALI_CTL_329__WRLVL_EN_SHIFT 24U 5848#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WIDTH 1U 5849#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOCLR 0U 5850#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOSET 0U 5851#define LPDDR4__WRLVL_EN__REG DENALI_CTL_329 5852#define LPDDR4__WRLVL_EN__FLD LPDDR4__DENALI_CTL_329__WRLVL_EN 5853 5854#define LPDDR4__DENALI_CTL_330_READ_MASK 0x0F010101U 5855#define LPDDR4__DENALI_CTL_330_WRITE_MASK 0x0F010101U 5856#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_MASK 0x00000001U 5857#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_SHIFT 0U 5858#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WIDTH 1U 5859#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOCLR 0U 5860#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOSET 0U 5861#define LPDDR4__DFI_PHY_WRLVL_MODE__REG DENALI_CTL_330 5862#define LPDDR4__DFI_PHY_WRLVL_MODE__FLD LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE 5863 5864#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_MASK 0x00000100U 5865#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_SHIFT 8U 5866#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WIDTH 1U 5867#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOCLR 0U 5868#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOSET 0U 5869#define LPDDR4__WRLVL_PERIODIC__REG DENALI_CTL_330 5870#define LPDDR4__WRLVL_PERIODIC__FLD LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC 5871 5872#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_MASK 0x00010000U 5873#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_SHIFT 16U 5874#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WIDTH 1U 5875#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOCLR 0U 5876#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOSET 0U 5877#define LPDDR4__WRLVL_ON_SREF_EXIT__REG DENALI_CTL_330 5878#define LPDDR4__WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT 5879 5880#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_MASK 0x0F000000U 5881#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_SHIFT 24U 5882#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_WIDTH 4U 5883#define LPDDR4__WRLVL_RESP_MASK__REG DENALI_CTL_330 5884#define LPDDR4__WRLVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK 5885 5886#define LPDDR4__DENALI_CTL_331_READ_MASK 0x07030101U 5887#define LPDDR4__DENALI_CTL_331_WRITE_MASK 0x07030101U 5888#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_MASK 0x00000001U 5889#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_SHIFT 0U 5890#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WIDTH 1U 5891#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOCLR 0U 5892#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOSET 0U 5893#define LPDDR4__WRLVL_AREF_EN__REG DENALI_CTL_331 5894#define LPDDR4__WRLVL_AREF_EN__FLD LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN 5895 5896#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_MASK 0x00000100U 5897#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_SHIFT 8U 5898#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WIDTH 1U 5899#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOCLR 0U 5900#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOSET 0U 5901#define LPDDR4__WRLVL_ROTATE__REG DENALI_CTL_331 5902#define LPDDR4__WRLVL_ROTATE__FLD LPDDR4__DENALI_CTL_331__WRLVL_ROTATE 5903 5904#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_MASK 0x00030000U 5905#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_SHIFT 16U 5906#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_WIDTH 2U 5907#define LPDDR4__WRLVL_CS_MAP__REG DENALI_CTL_331 5908#define LPDDR4__WRLVL_CS_MAP__FLD LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP 5909 5910#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_MASK 0x07000000U 5911#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_SHIFT 24U 5912#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_WIDTH 3U 5913#define LPDDR4__WRLVL_ERROR_STATUS__REG DENALI_CTL_331 5914#define LPDDR4__WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS 5915 5916#define LPDDR4__DENALI_CTL_332_READ_MASK 0xFFFFFFFFU 5917#define LPDDR4__DENALI_CTL_332_WRITE_MASK 0xFFFFFFFFU 5918#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_MASK 0x0000FFFFU 5919#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_SHIFT 0U 5920#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_WIDTH 16U 5921#define LPDDR4__WRLVL_NORM_THRESHOLD_F0__REG DENALI_CTL_332 5922#define LPDDR4__WRLVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0 5923 5924#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U 5925#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_SHIFT 16U 5926#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_WIDTH 16U 5927#define LPDDR4__WRLVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_332 5928#define LPDDR4__WRLVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0 5929 5930#define LPDDR4__DENALI_CTL_333_READ_MASK 0xFFFFFFFFU 5931#define LPDDR4__DENALI_CTL_333_WRITE_MASK 0xFFFFFFFFU 5932#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_MASK 0x0000FFFFU 5933#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_SHIFT 0U 5934#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_WIDTH 16U 5935#define LPDDR4__WRLVL_TIMEOUT_F0__REG DENALI_CTL_333 5936#define LPDDR4__WRLVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0 5937 5938#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U 5939#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U 5940#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U 5941#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_333 5942#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0 5943 5944#define LPDDR4__DENALI_CTL_334_READ_MASK 0xFFFFFFFFU 5945#define LPDDR4__DENALI_CTL_334_WRITE_MASK 0xFFFFFFFFU 5946#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU 5947#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U 5948#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U 5949#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_334 5950#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0 5951 5952#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_MASK 0xFFFF0000U 5953#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_SHIFT 16U 5954#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_WIDTH 16U 5955#define LPDDR4__WRLVL_NORM_THRESHOLD_F1__REG DENALI_CTL_334 5956#define LPDDR4__WRLVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1 5957 5958#define LPDDR4__DENALI_CTL_335_READ_MASK 0xFFFFFFFFU 5959#define LPDDR4__DENALI_CTL_335_WRITE_MASK 0xFFFFFFFFU 5960#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU 5961#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_SHIFT 0U 5962#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_WIDTH 16U 5963#define LPDDR4__WRLVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_335 5964#define LPDDR4__WRLVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1 5965 5966#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_MASK 0xFFFF0000U 5967#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_SHIFT 16U 5968#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_WIDTH 16U 5969#define LPDDR4__WRLVL_TIMEOUT_F1__REG DENALI_CTL_335 5970#define LPDDR4__WRLVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1 5971 5972#define LPDDR4__DENALI_CTL_336_READ_MASK 0xFFFFFFFFU 5973#define LPDDR4__DENALI_CTL_336_WRITE_MASK 0xFFFFFFFFU 5974#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU 5975#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U 5976#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U 5977#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_336 5978#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1 5979 5980#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U 5981#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U 5982#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U 5983#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_336 5984#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1 5985 5986#define LPDDR4__DENALI_CTL_337_READ_MASK 0xFFFFFFFFU 5987#define LPDDR4__DENALI_CTL_337_WRITE_MASK 0xFFFFFFFFU 5988#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_MASK 0x0000FFFFU 5989#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_SHIFT 0U 5990#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_WIDTH 16U 5991#define LPDDR4__WRLVL_NORM_THRESHOLD_F2__REG DENALI_CTL_337 5992#define LPDDR4__WRLVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2 5993 5994#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U 5995#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_SHIFT 16U 5996#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_WIDTH 16U 5997#define LPDDR4__WRLVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_337 5998#define LPDDR4__WRLVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2 5999 6000#define LPDDR4__DENALI_CTL_338_READ_MASK 0xFFFFFFFFU
6001#define LPDDR4__DENALI_CTL_338_WRITE_MASK 0xFFFFFFFFU 6002#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_MASK 0x0000FFFFU 6003#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_SHIFT 0U 6004#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_WIDTH 16U 6005#define LPDDR4__WRLVL_TIMEOUT_F2__REG DENALI_CTL_338 6006#define LPDDR4__WRLVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2 6007 6008#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U 6009#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U 6010#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U 6011#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_338 6012#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2 6013 6014#define LPDDR4__DENALI_CTL_339_READ_MASK 0x0000FFFFU 6015#define LPDDR4__DENALI_CTL_339_WRITE_MASK 0x0000FFFFU 6016#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU 6017#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U 6018#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U 6019#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_339 6020#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2 6021 6022#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_MASK 0x00010000U 6023#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_SHIFT 16U 6024#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WIDTH 1U 6025#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOCLR 0U 6026#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOSET 0U 6027#define LPDDR4__RDLVL_REQ__REG DENALI_CTL_339 6028#define LPDDR4__RDLVL_REQ__FLD LPDDR4__DENALI_CTL_339__RDLVL_REQ 6029 6030#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_MASK 0x01000000U 6031#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_SHIFT 24U 6032#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WIDTH 1U 6033#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOCLR 0U 6034#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOSET 0U 6035#define LPDDR4__RDLVL_GATE_REQ__REG DENALI_CTL_339 6036#define LPDDR4__RDLVL_GATE_REQ__FLD LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ 6037 6038#define LPDDR4__DENALI_CTL_340_READ_MASK 0x010F0F01U 6039#define LPDDR4__DENALI_CTL_340_WRITE_MASK 0x010F0F01U 6040#define LPDDR4__DENALI_CTL_340__RDLVL_CS_MASK 0x00000001U 6041#define LPDDR4__DENALI_CTL_340__RDLVL_CS_SHIFT 0U 6042#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WIDTH 1U 6043#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOCLR 0U 6044#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOSET 0U 6045#define LPDDR4__RDLVL_CS__REG DENALI_CTL_340 6046#define LPDDR4__RDLVL_CS__FLD LPDDR4__DENALI_CTL_340__RDLVL_CS 6047 6048#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_MASK 0x00000F00U 6049#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_SHIFT 8U 6050#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_WIDTH 4U 6051#define LPDDR4__RDLVL_SEQ_EN__REG DENALI_CTL_340 6052#define LPDDR4__RDLVL_SEQ_EN__FLD LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN 6053 6054#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_MASK 0x000F0000U 6055#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_SHIFT 16U 6056#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_WIDTH 4U 6057#define LPDDR4__RDLVL_GATE_SEQ_EN__REG DENALI_CTL_340 6058#define LPDDR4__RDLVL_GATE_SEQ_EN__FLD LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN 6059 6060#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_MASK 0x01000000U 6061#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_SHIFT 24U 6062#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WIDTH 1U 6063#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOCLR 0U 6064#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOSET 0U 6065#define LPDDR4__DFI_PHY_RDLVL_MODE__REG DENALI_CTL_340 6066#define LPDDR4__DFI_PHY_RDLVL_MODE__FLD LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE 6067 6068#define LPDDR4__DENALI_CTL_341_READ_MASK 0x01010101U 6069#define LPDDR4__DENALI_CTL_341_WRITE_MASK 0x01010101U 6070#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_MASK 0x00000001U 6071#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_SHIFT 0U 6072#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WIDTH 1U 6073#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOCLR 0U 6074#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOSET 0U 6075#define LPDDR4__DFI_PHY_RDLVL_GATE_MODE__REG DENALI_CTL_341 6076#define LPDDR4__DFI_PHY_RDLVL_GATE_MODE__FLD LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE 6077 6078#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_MASK 0x00000100U 6079#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_SHIFT 8U 6080#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WIDTH 1U 6081#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOCLR 0U 6082#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOSET 0U 6083#define LPDDR4__RDLVL_PERIODIC__REG DENALI_CTL_341 6084#define LPDDR4__RDLVL_PERIODIC__FLD LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC 6085 6086#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_MASK 0x00010000U 6087#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_SHIFT 16U 6088#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WIDTH 1U 6089#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOCLR 0U 6090#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOSET 0U 6091#define LPDDR4__RDLVL_ON_SREF_EXIT__REG DENALI_CTL_341 6092#define LPDDR4__RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT 6093 6094#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_MASK 0x01000000U 6095#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_SHIFT 24U 6096#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WIDTH 1U 6097#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOCLR 0U 6098#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOSET 0U 6099#define LPDDR4__RDLVL_GATE_PERIODIC__REG DENALI_CTL_341 6100#define LPDDR4__RDLVL_GATE_PERIODIC__FLD LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC 6101 6102#define LPDDR4__DENALI_CTL_342_READ_MASK 0x01010101U 6103#define LPDDR4__DENALI_CTL_342_WRITE_MASK 0x01010101U 6104#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_MASK 0x00000001U 6105#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_SHIFT 0U 6106#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WIDTH 1U 6107#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOCLR 0U 6108#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOSET 0U 6109#define LPDDR4__RDLVL_GATE_ON_SREF_EXIT__REG DENALI_CTL_342 6110#define LPDDR4__RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT 6111 6112#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_MASK 0x00000100U 6113#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_SHIFT 8U 6114#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WIDTH 1U 6115#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOCLR 0U 6116#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOSET 0U 6117#define LPDDR4__RDLVL_AREF_EN__REG DENALI_CTL_342 6118#define LPDDR4__RDLVL_AREF_EN__FLD LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN 6119 6120#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_MASK 0x00010000U 6121#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_SHIFT 16U 6122#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WIDTH 1U 6123#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOCLR 0U 6124#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOSET 0U 6125#define LPDDR4__RDLVL_GATE_AREF_EN__REG DENALI_CTL_342 6126#define LPDDR4__RDLVL_GATE_AREF_EN__FLD LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN 6127 6128#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_MASK 0x01000000U 6129#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_SHIFT 24U 6130#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WIDTH 1U 6131#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOCLR 0U 6132#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOSET 0U 6133#define LPDDR4__MC_RESERVED29__REG DENALI_CTL_342 6134#define LPDDR4__MC_RESERVED29__FLD LPDDR4__DENALI_CTL_342__MC_RESERVED29 6135 6136#define LPDDR4__DENALI_CTL_343_READ_MASK 0x03030101U 6137#define LPDDR4__DENALI_CTL_343_WRITE_MASK 0x03030101U 6138#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_MASK 0x00000001U 6139#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_SHIFT 0U 6140#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WIDTH 1U 6141#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOCLR 0U 6142#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOSET 0U 6143#define LPDDR4__RDLVL_ROTATE__REG DENALI_CTL_343 6144#define LPDDR4__RDLVL_ROTATE__FLD LPDDR4__DENALI_CTL_343__RDLVL_ROTATE 6145 6146#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_MASK 0x00000100U 6147#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_SHIFT 8U 6148#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WIDTH 1U 6149#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOCLR 0U 6150#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOSET 0U 6151#define LPDDR4__RDLVL_GATE_ROTATE__REG DENALI_CTL_343 6152#define LPDDR4__RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE 6153 6154#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_MASK 0x00030000U 6155#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_SHIFT 16U 6156#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_WIDTH 2U 6157#define LPDDR4__RDLVL_CS_MAP__REG DENALI_CTL_343 6158#define LPDDR4__RDLVL_CS_MAP__FLD LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP 6159 6160#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_MASK 0x03000000U 6161#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_SHIFT 24U 6162#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_WIDTH 2U 6163#define LPDDR4__RDLVL_GATE_CS_MAP__REG DENALI_CTL_343 6164#define LPDDR4__RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP 6165 6166#define LPDDR4__DENALI_CTL_344_READ_MASK 0xFFFFFFFFU 6167#define LPDDR4__DENALI_CTL_344_WRITE_MASK 0xFFFFFFFFU 6168#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_MASK 0x0000FFFFU 6169#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_SHIFT 0U 6170#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_WIDTH 16U 6171#define LPDDR4__RDLVL_NORM_THRESHOLD_F0__REG DENALI_CTL_344 6172#define LPDDR4__RDLVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0 6173 6174#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U 6175#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_SHIFT 16U 6176#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_WIDTH 16U 6177#define LPDDR4__RDLVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_344 6178#define LPDDR4__RDLVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0 6179 6180#define LPDDR4__DENALI_CTL_345_READ_MASK 0xFFFFFFFFU 6181#define LPDDR4__DENALI_CTL_345_WRITE_MASK 0xFFFFFFFFU 6182#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_MASK 0x0000FFFFU 6183#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_SHIFT 0U 6184#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_WIDTH 16U 6185#define LPDDR4__RDLVL_TIMEOUT_F0__REG DENALI_CTL_345 6186#define LPDDR4__RDLVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0 6187 6188#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U 6189#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U 6190#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U 6191#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_345 6192#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0 6193 6194#define LPDDR4__DENALI_CTL_346_READ_MASK 0xFFFFFFFFU 6195#define LPDDR4__DENALI_CTL_346_WRITE_MASK 0xFFFFFFFFU 6196#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU 6197#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U 6198#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U 6199#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_346 6200#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0 6201 6202#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_MASK 0xFFFF0000U 6203#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_SHIFT 16U 6204#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_WIDTH 16U 6205#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F0__REG DENALI_CTL_346 6206#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0 6207 6208#define LPDDR4__DENALI_CTL_347_READ_MASK 0xFFFFFFFFU 6209#define LPDDR4__DENALI_CTL_347_WRITE_MASK 0xFFFFFFFFU 6210#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU 6211#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_SHIFT 0U 6212#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_WIDTH 16U 6213#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F0__REG DENALI_CTL_347 6214#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0 6215 6216#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_MASK 0xFFFF0000U 6217#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_SHIFT 16U 6218#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_WIDTH 16U 6219#define LPDDR4__RDLVL_GATE_TIMEOUT_F0__REG DENALI_CTL_347 6220#define LPDDR4__RDLVL_GATE_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0 6221 6222#define LPDDR4__DENALI_CTL_348_READ_MASK 0xFFFFFFFFU 6223#define LPDDR4__DENALI_CTL_348_WRITE_MASK 0xFFFFFFFFU 6224#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU 6225#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_SHIFT 0U 6226#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U 6227#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_348 6228#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0 6229 6230#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U 6231#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_SHIFT 16U 6232#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U 6233#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_348 6234#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0 6235 6236#define LPDDR4__DENALI_CTL_349_READ_MASK 0xFFFFFFFFU 6237#define LPDDR4__DENALI_CTL_349_WRITE_MASK 0xFFFFFFFFU 6238#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_MASK 0x0000FFFFU 6239#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_SHIFT 0U 6240#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_WIDTH 16U 6241#define LPDDR4__RDLVL_NORM_THRESHOLD_F1__REG DENALI_CTL_349 6242#define LPDDR4__RDLVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1 6243 6244#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U 6245#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_SHIFT 16U 6246#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_WIDTH 16U 6247#define LPDDR4__RDLVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_349 6248#define LPDDR4__RDLVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1 6249 6250#define LPDDR4__DENALI_CTL_350_READ_MASK 0xFFFFFFFFU 6251#define LPDDR4__DENALI_CTL_350_WRITE_MASK 0xFFFFFFFFU 6252#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_MASK 0x0000FFFFU 6253#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_SHIFT 0U 6254#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_WIDTH 16U 6255#define LPDDR4__RDLVL_TIMEOUT_F1__REG DENALI_CTL_350 6256#define LPDDR4__RDLVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1 6257 6258#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U 6259#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_SHIFT 16U 6260#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U 6261#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_350 6262#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1 6263 6264#define LPDDR4__DENALI_CTL_351_READ_MASK 0xFFFFFFFFU 6265#define LPDDR4__DENALI_CTL_351_WRITE_MASK 0xFFFFFFFFU 6266#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU 6267#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT 0U 6268#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U 6269#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_351 6270#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1 6271 6272#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_MASK 0xFFFF0000U 6273#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_SHIFT 16U 6274#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_WIDTH 16U 6275#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F1__REG DENALI_CTL_351 6276#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1 6277 6278#define LPDDR4__DENALI_CTL_352_READ_MASK 0xFFFFFFFFU 6279#define LPDDR4__DENALI_CTL_352_WRITE_MASK 0xFFFFFFFFU 6280#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU 6281#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_SHIFT 0U 6282#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_WIDTH 16U 6283#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F1__REG DENALI_CTL_352 6284#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1 6285 6286#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_MASK 0xFFFF0000U 6287#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_SHIFT 16U 6288#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_WIDTH 16U 6289#define LPDDR4__RDLVL_GATE_TIMEOUT_F1__REG DENALI_CTL_352 6290#define LPDDR4__RDLVL_GATE_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1 6291 6292#define LPDDR4__DENALI_CTL_353_READ_MASK 0xFFFFFFFFU 6293#define LPDDR4__DENALI_CTL_353_WRITE_MASK 0xFFFFFFFFU 6294#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU 6295#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U 6296#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U 6297#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_353 6298#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1 6299 6300#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U 6301#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U 6302#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U 6303#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_353 6304#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1 6305 6306#define LPDDR4__DENALI_CTL_354_READ_MASK 0xFFFFFFFFU 6307#define LPDDR4__DENALI_CTL_354_WRITE_MASK 0xFFFFFFFFU 6308#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_MASK 0x0000FFFFU 6309#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_SHIFT 0U 6310#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_WIDTH 16U 6311#define LPDDR4__RDLVL_NORM_THRESHOLD_F2__REG DENALI_CTL_354 6312#define LPDDR4__RDLVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2 6313 6314#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U 6315#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_SHIFT 16U 6316#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_WIDTH 16U 6317#define LPDDR4__RDLVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_354 6318#define LPDDR4__RDLVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2 6319 6320#define LPDDR4__DENALI_CTL_355_READ_MASK 0xFFFFFFFFU 6321#define LPDDR4__DENALI_CTL_355_WRITE_MASK 0xFFFFFFFFU 6322#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_MASK 0x0000FFFFU 6323#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_SHIFT 0U 6324#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_WIDTH 16U 6325#define LPDDR4__RDLVL_TIMEOUT_F2__REG DENALI_CTL_355 6326#define LPDDR4__RDLVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2 6327 6328#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U 6329#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U 6330#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U 6331#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_355 6332#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2 6333 6334#define LPDDR4__DENALI_CTL_356_READ_MASK 0xFFFFFFFFU 6335#define LPDDR4__DENALI_CTL_356_WRITE_MASK 0xFFFFFFFFU 6336#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU 6337#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U 6338#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U 6339#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_356 6340#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2 6341 6342#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_MASK 0xFFFF0000U 6343#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_SHIFT 16U 6344#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_WIDTH 16U 6345#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F2__REG DENALI_CTL_356 6346#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2 6347 6348#define LPDDR4__DENALI_CTL_357_READ_MASK 0xFFFFFFFFU 6349#define LPDDR4__DENALI_CTL_357_WRITE_MASK 0xFFFFFFFFU 6350#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU 6351#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_SHIFT 0U 6352#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_WIDTH 16U 6353#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F2__REG DENALI_CTL_357 6354#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2 6355 6356#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_MASK 0xFFFF0000U 6357#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_SHIFT 16U 6358#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_WIDTH 16U 6359#define LPDDR4__RDLVL_GATE_TIMEOUT_F2__REG DENALI_CTL_357 6360#define LPDDR4__RDLVL_GATE_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2 6361 6362#define LPDDR4__DENALI_CTL_358_READ_MASK 0xFFFFFFFFU 6363#define LPDDR4__DENALI_CTL_358_WRITE_MASK 0xFFFFFFFFU 6364#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU 6365#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_SHIFT 0U 6366#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U 6367#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_358 6368#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2 6369 6370#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U 6371#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_SHIFT 16U 6372#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U 6373#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_358 6374#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2 6375 6376#define LPDDR4__DENALI_CTL_359_READ_MASK 0x00000100U 6377#define LPDDR4__DENALI_CTL_359_WRITE_MASK 0x00000100U 6378#define LPDDR4__DENALI_CTL_359__CALVL_REQ_MASK 0x00000001U 6379#define LPDDR4__DENALI_CTL_359__CALVL_REQ_SHIFT 0U 6380#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WIDTH 1U 6381#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOCLR 0U 6382#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOSET 0U 6383#define LPDDR4__CALVL_REQ__REG DENALI_CTL_359 6384#define LPDDR4__CALVL_REQ__FLD LPDDR4__DENALI_CTL_359__CALVL_REQ 6385 6386#define LPDDR4__DENALI_CTL_359__CALVL_CS_MASK 0x00000100U 6387#define LPDDR4__DENALI_CTL_359__CALVL_CS_SHIFT 8U 6388#define LPDDR4__DENALI_CTL_359__CALVL_CS_WIDTH 1U 6389#define LPDDR4__DENALI_CTL_359__CALVL_CS_WOCLR 0U 6390#define LPDDR4__DENALI_CTL_359__CALVL_CS_WOSET 0U 6391#define LPDDR4__CALVL_CS__REG DENALI_CTL_359 6392#define LPDDR4__CALVL_CS__FLD LPDDR4__DENALI_CTL_359__CALVL_CS 6393 6394#define LPDDR4__DENALI_CTL_360_READ_MASK 0x000FFFFFU 6395#define LPDDR4__DENALI_CTL_360_WRITE_MASK 0x000FFFFFU 6396#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_MASK 0x000FFFFFU 6397#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_SHIFT 0U 6398#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_WIDTH 20U 6399#define LPDDR4__CALVL_PAT_0__REG DENALI_CTL_360 6400#define LPDDR4__CALVL_PAT_0__FLD LPDDR4__DENALI_CTL_360__CALVL_PAT_0 6401 6402#define LPDDR4__DENALI_CTL_361_READ_MASK 0x000FFFFFU 6403#define LPDDR4__DENALI_CTL_361_WRITE_MASK 0x000FFFFFU 6404#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_MASK 0x000FFFFFU 6405#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_SHIFT 0U 6406#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_WIDTH 20U 6407#define LPDDR4__CALVL_BG_PAT_0__REG DENALI_CTL_361 6408#define LPDDR4__CALVL_BG_PAT_0__FLD LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0 6409 6410#define LPDDR4__DENALI_CTL_362_READ_MASK 0x000FFFFFU 6411#define LPDDR4__DENALI_CTL_362_WRITE_MASK 0x000FFFFFU 6412#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_MASK 0x000FFFFFU 6413#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_SHIFT 0U 6414#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_WIDTH 20U 6415#define LPDDR4__CALVL_PAT_1__REG DENALI_CTL_362 6416#define LPDDR4__CALVL_PAT_1__FLD LPDDR4__DENALI_CTL_362__CALVL_PAT_1 6417 6418#define LPDDR4__DENALI_CTL_363_READ_MASK 0x000FFFFFU 6419#define LPDDR4__DENALI_CTL_363_WRITE_MASK 0x000FFFFFU 6420#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_MASK 0x000FFFFFU 6421#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_SHIFT 0U 6422#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_WIDTH 20U 6423#define LPDDR4__CALVL_BG_PAT_1__REG DENALI_CTL_363 6424#define LPDDR4__CALVL_BG_PAT_1__FLD LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1 6425 6426#define LPDDR4__DENALI_CTL_364_READ_MASK 0x000FFFFFU 6427#define LPDDR4__DENALI_CTL_364_WRITE_MASK 0x000FFFFFU 6428#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_MASK 0x000FFFFFU 6429#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_SHIFT 0U 6430#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_WIDTH 20U 6431#define LPDDR4__CALVL_PAT_2__REG DENALI_CTL_364 6432#define LPDDR4__CALVL_PAT_2__FLD LPDDR4__DENALI_CTL_364__CALVL_PAT_2 6433 6434#define LPDDR4__DENALI_CTL_365_READ_MASK 0x000FFFFFU 6435#define LPDDR4__DENALI_CTL_365_WRITE_MASK 0x000FFFFFU 6436#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_MASK 0x000FFFFFU 6437#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_SHIFT 0U 6438#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_WIDTH 20U 6439#define LPDDR4__CALVL_BG_PAT_2__REG DENALI_CTL_365 6440#define LPDDR4__CALVL_BG_PAT_2__FLD LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2 6441 6442#define LPDDR4__DENALI_CTL_366_READ_MASK 0x000FFFFFU 6443#define LPDDR4__DENALI_CTL_366_WRITE_MASK 0x000FFFFFU 6444#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_MASK 0x000FFFFFU 6445#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_SHIFT 0U 6446#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_WIDTH 20U 6447#define LPDDR4__CALVL_PAT_3__REG DENALI_CTL_366 6448#define LPDDR4__CALVL_PAT_3__FLD LPDDR4__DENALI_CTL_366__CALVL_PAT_3 6449 6450#define LPDDR4__DENALI_CTL_367_READ_MASK 0x010FFFFFU 6451#define LPDDR4__DENALI_CTL_367_WRITE_MASK 0x010FFFFFU 6452#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_MASK 0x000FFFFFU 6453#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_SHIFT 0U 6454#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_WIDTH 20U 6455#define LPDDR4__CALVL_BG_PAT_3__REG DENALI_CTL_367 6456#define LPDDR4__CALVL_BG_PAT_3__FLD LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3 6457 6458#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_MASK 0x01000000U 6459#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_SHIFT 24U 6460#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WIDTH 1U 6461#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOCLR 0U 6462#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOSET 0U 6463#define LPDDR4__MC_RESERVED30__REG DENALI_CTL_367 6464#define LPDDR4__MC_RESERVED30__FLD LPDDR4__DENALI_CTL_367__MC_RESERVED30 6465 6466#define LPDDR4__DENALI_CTL_368_READ_MASK 0x0101030FU 6467#define LPDDR4__DENALI_CTL_368_WRITE_MASK 0x0101030FU 6468#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_MASK 0x0000000FU 6469#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_SHIFT 0U 6470#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_WIDTH 4U 6471#define LPDDR4__MC_RESERVED31__REG DENALI_CTL_368 6472#define LPDDR4__MC_RESERVED31__FLD LPDDR4__DENALI_CTL_368__MC_RESERVED31 6473 6474#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_MASK 0x00000300U 6475#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_SHIFT 8U 6476#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_WIDTH 2U 6477#define LPDDR4__CALVL_SEQ_EN__REG DENALI_CTL_368 6478#define LPDDR4__CALVL_SEQ_EN__FLD LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN 6479 6480#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_MASK 0x00010000U 6481#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_SHIFT 16U 6482#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WIDTH 1U 6483#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOCLR 0U 6484#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOSET 0U 6485#define LPDDR4__DFI_PHY_CALVL_MODE__REG DENALI_CTL_368 6486#define LPDDR4__DFI_PHY_CALVL_MODE__FLD LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE 6487 6488#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_MASK 0x01000000U 6489#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_SHIFT 24U 6490#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WIDTH 1U 6491#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOCLR 0U 6492#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOSET 0U 6493#define LPDDR4__CALVL_PERIODIC__REG DENALI_CTL_368 6494#define LPDDR4__CALVL_PERIODIC__FLD LPDDR4__DENALI_CTL_368__CALVL_PERIODIC 6495 6496#define LPDDR4__DENALI_CTL_369_READ_MASK 0x03010101U 6497#define LPDDR4__DENALI_CTL_369_WRITE_MASK 0x03010101U 6498#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_MASK 0x00000001U 6499#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_SHIFT 0U 6500#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WIDTH 1U 6501#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOCLR 0U 6502#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOSET 0U 6503#define LPDDR4__CALVL_ON_SREF_EXIT__REG DENALI_CTL_369 6504#define LPDDR4__CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT 6505 6506#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_MASK 0x00000100U 6507#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_SHIFT 8U 6508#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WIDTH 1U 6509#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOCLR 0U 6510#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOSET 0U 6511#define LPDDR4__CALVL_AREF_EN__REG DENALI_CTL_369 6512#define LPDDR4__CALVL_AREF_EN__FLD LPDDR4__DENALI_CTL_369__CALVL_AREF_EN 6513 6514#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_MASK 0x00010000U 6515#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_SHIFT 16U 6516#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WIDTH 1U 6517#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOCLR 0U 6518#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOSET 0U 6519#define LPDDR4__CALVL_ROTATE__REG DENALI_CTL_369 6520#define LPDDR4__CALVL_ROTATE__FLD LPDDR4__DENALI_CTL_369__CALVL_ROTATE 6521 6522#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_MASK 0x03000000U 6523#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_SHIFT 24U 6524#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_WIDTH 2U 6525#define LPDDR4__CALVL_CS_MAP__REG DENALI_CTL_369 6526#define LPDDR4__CALVL_CS_MAP__FLD LPDDR4__DENALI_CTL_369__CALVL_CS_MAP 6527 6528#define LPDDR4__DENALI_CTL_370_READ_MASK 0xFFFFFFFFU 6529#define LPDDR4__DENALI_CTL_370_WRITE_MASK 0xFFFFFFFFU 6530#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_MASK 0x0000FFFFU 6531#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_SHIFT 0U 6532#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_WIDTH 16U 6533#define LPDDR4__CALVL_NORM_THRESHOLD_F0__REG DENALI_CTL_370 6534#define LPDDR4__CALVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0 6535 6536#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U 6537#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_SHIFT 16U 6538#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_WIDTH 16U 6539#define LPDDR4__CALVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_370 6540#define LPDDR4__CALVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0 6541 6542#define LPDDR4__DENALI_CTL_371_READ_MASK 0xFFFFFFFFU 6543#define LPDDR4__DENALI_CTL_371_WRITE_MASK 0xFFFFFFFFU 6544#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_MASK 0x0000FFFFU 6545#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_SHIFT 0U 6546#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_WIDTH 16U 6547#define LPDDR4__CALVL_TIMEOUT_F0__REG DENALI_CTL_371 6548#define LPDDR4__CALVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0 6549 6550#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U 6551#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U 6552#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U 6553#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_371 6554#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0 6555 6556#define LPDDR4__DENALI_CTL_372_READ_MASK 0xFFFFFFFFU 6557#define LPDDR4__DENALI_CTL_372_WRITE_MASK 0xFFFFFFFFU 6558#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU 6559#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U 6560#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U 6561#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_372 6562#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0 6563 6564#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_MASK 0xFFFF0000U 6565#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_SHIFT 16U 6566#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_WIDTH 16U 6567#define LPDDR4__CALVL_NORM_THRESHOLD_F1__REG DENALI_CTL_372 6568#define LPDDR4__CALVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1 6569 6570#define LPDDR4__DENALI_CTL_373_READ_MASK 0xFFFFFFFFU 6571#define LPDDR4__DENALI_CTL_373_WRITE_MASK 0xFFFFFFFFU 6572#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU 6573#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_SHIFT 0U 6574#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_WIDTH 16U 6575#define LPDDR4__CALVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_373 6576#define LPDDR4__CALVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1 6577 6578#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_MASK 0xFFFF0000U 6579#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_SHIFT 16U 6580#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_WIDTH 16U 6581#define LPDDR4__CALVL_TIMEOUT_F1__REG DENALI_CTL_373 6582#define LPDDR4__CALVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1 6583 6584#define LPDDR4__DENALI_CTL_374_READ_MASK 0xFFFFFFFFU 6585#define LPDDR4__DENALI_CTL_374_WRITE_MASK 0xFFFFFFFFU 6586#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU 6587#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U 6588#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U 6589#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_374 6590#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1 6591 6592#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U 6593#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U 6594#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U 6595#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_374 6596#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1 6597 6598#define LPDDR4__DENALI_CTL_375_READ_MASK 0xFFFFFFFFU 6599#define LPDDR4__DENALI_CTL_375_WRITE_MASK 0xFFFFFFFFU 6600#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_MASK 0x0000FFFFU 6601#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_SHIFT 0U 6602#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_WIDTH 16U 6603#define LPDDR4__CALVL_NORM_THRESHOLD_F2__REG DENALI_CTL_375 6604#define LPDDR4__CALVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2 6605 6606#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U 6607#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_SHIFT 16U 6608#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_WIDTH 16U 6609#define LPDDR4__CALVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_375 6610#define LPDDR4__CALVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2 6611 6612#define LPDDR4__DENALI_CTL_376_READ_MASK 0xFFFFFFFFU 6613#define LPDDR4__DENALI_CTL_376_WRITE_MASK 0xFFFFFFFFU 6614#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_MASK 0x0000FFFFU 6615#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_SHIFT 0U 6616#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_WIDTH 16U 6617#define LPDDR4__CALVL_TIMEOUT_F2__REG DENALI_CTL_376 6618#define LPDDR4__CALVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2 6619 6620#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U 6621#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U 6622#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U 6623#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_376 6624#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2 6625 6626#define LPDDR4__DENALI_CTL_377_READ_MASK 0x0101FFFFU 6627#define LPDDR4__DENALI_CTL_377_WRITE_MASK 0x0101FFFFU 6628#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU 6629#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U 6630#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U 6631#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_377 6632#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2 6633 6634#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_MASK 0x00010000U 6635#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_SHIFT 16U 6636#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WIDTH 1U 6637#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WOCLR 0U 6638#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WOSET 0U 6639#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__REG DENALI_CTL_377 6640#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__FLD LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE 6641 6642#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_MASK 0x01000000U 6643#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_SHIFT 24U 6644#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WIDTH 1U 6645#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOCLR 0U 6646#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOSET 0U 6647#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__REG DENALI_CTL_377 6648#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__FLD LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE 6649 6650#define LPDDR4__DENALI_CTL_378_READ_MASK 0x00000707U 6651#define LPDDR4__DENALI_CTL_378_WRITE_MASK 0x00000707U 6652#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_MASK 0x00000007U 6653#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_SHIFT 0U 6654#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_WIDTH 3U 6655#define LPDDR4__AXI0_R_PRIORITY__REG DENALI_CTL_378 6656#define LPDDR4__AXI0_R_PRIORITY__FLD LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY 6657 6658#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_MASK 0x00000700U 6659#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_SHIFT 8U 6660#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_WIDTH 3U 6661#define LPDDR4__AXI0_W_PRIORITY__REG DENALI_CTL_378 6662#define LPDDR4__AXI0_W_PRIORITY__FLD LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY 6663 6664#define LPDDR4__DENALI_CTL_379_READ_MASK 0xFFFFFFFFU 6665#define LPDDR4__DENALI_CTL_379_WRITE_MASK 0xFFFFFFFFU 6666#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_MASK 0xFFFFFFFFU 6667#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_SHIFT 0U 6668#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_WIDTH 32U 6669#define LPDDR4__PARITY_ERROR_ADDRESS_0__REG DENALI_CTL_379 6670#define LPDDR4__PARITY_ERROR_ADDRESS_0__FLD LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0 6671 6672#define LPDDR4__DENALI_CTL_380_READ_MASK 0x1FFF3F07U 6673#define LPDDR4__DENALI_CTL_380_WRITE_MASK 0x1FFF3F07U 6674#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_MASK 0x00000007U 6675#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_SHIFT 0U 6676#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_WIDTH 3U 6677#define LPDDR4__PARITY_ERROR_ADDRESS_1__REG DENALI_CTL_380 6678#define LPDDR4__PARITY_ERROR_ADDRESS_1__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1 6679 6680#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_MASK 0x00003F00U 6681#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_SHIFT 8U 6682#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_WIDTH 6U 6683#define LPDDR4__PARITY_ERROR_MASTER_ID__REG DENALI_CTL_380 6684#define LPDDR4__PARITY_ERROR_MASTER_ID__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID 6685 6686#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_MASK 0x1FFF0000U 6687#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_SHIFT 16U 6688#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_WIDTH 13U 6689#define LPDDR4__PARITY_ERROR_BUS_CHANNEL__REG DENALI_CTL_380 6690#define LPDDR4__PARITY_ERROR_BUS_CHANNEL__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL 6691 6692#define LPDDR4__DENALI_CTL_381_READ_MASK 0xFFFFFFFFU 6693#define LPDDR4__DENALI_CTL_381_WRITE_MASK 0xFFFFFFFFU 6694#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_MASK 0xFFFFFFFFU 6695#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_SHIFT 0U 6696#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_WIDTH 32U 6697#define LPDDR4__PARITY_ERROR_WRITE_DATA_0__REG DENALI_CTL_381 6698#define LPDDR4__PARITY_ERROR_WRITE_DATA_0__FLD LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0 6699 6700#define LPDDR4__DENALI_CTL_382_READ_MASK 0xFFFFFFFFU 6701#define LPDDR4__DENALI_CTL_382_WRITE_MASK 0xFFFFFFFFU 6702#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_MASK 0xFFFFFFFFU 6703#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_SHIFT 0U 6704#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_WIDTH 32U 6705#define LPDDR4__PARITY_ERROR_WRITE_DATA_1__REG DENALI_CTL_382 6706#define LPDDR4__PARITY_ERROR_WRITE_DATA_1__FLD LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1 6707 6708#define LPDDR4__DENALI_CTL_383_READ_MASK 0xFFFFFFFFU 6709#define LPDDR4__DENALI_CTL_383_WRITE_MASK 0xFFFFFFFFU 6710#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_MASK 0xFFFFFFFFU 6711#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_SHIFT 0U 6712#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_WIDTH 32U 6713#define LPDDR4__PARITY_ERROR_WRITE_DATA_2__REG DENALI_CTL_383 6714#define LPDDR4__PARITY_ERROR_WRITE_DATA_2__FLD LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2 6715 6716#define LPDDR4__DENALI_CTL_384_READ_MASK 0xFFFFFFFFU 6717#define LPDDR4__DENALI_CTL_384_WRITE_MASK 0xFFFFFFFFU 6718#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_MASK 0xFFFFFFFFU 6719#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_SHIFT 0U 6720#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_WIDTH 32U 6721#define LPDDR4__PARITY_ERROR_WRITE_DATA_3__REG DENALI_CTL_384 6722#define LPDDR4__PARITY_ERROR_WRITE_DATA_3__FLD LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3 6723 6724#define LPDDR4__DENALI_CTL_385_READ_MASK 0x0103FFFFU 6725#define LPDDR4__DENALI_CTL_385_WRITE_MASK 0x0103FFFFU 6726#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_MASK 0x0000FFFFU 6727#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_SHIFT 0U 6728#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_WIDTH 16U 6729#define LPDDR4__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR__REG DENALI_CTL_385 6730#define LPDDR4__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR__FLD LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR 6731 6732#define LPDDR4__DENALI_CTL_385__CKE_STATUS_MASK 0x00030000U 6733#define LPDDR4__DENALI_CTL_385__CKE_STATUS_SHIFT 16U 6734#define LPDDR4__DENALI_CTL_385__CKE_STATUS_WIDTH 2U 6735#define LPDDR4__CKE_STATUS__REG DENALI_CTL_385 6736#define LPDDR4__CKE_STATUS__FLD LPDDR4__DENALI_CTL_385__CKE_STATUS 6737 6738#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_MASK 0x01000000U 6739#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_SHIFT 24U 6740#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WIDTH 1U 6741#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOCLR 0U 6742#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOSET 0U 6743#define LPDDR4__MEM_RST_VALID__REG DENALI_CTL_385 6744#define LPDDR4__MEM_RST_VALID__FLD LPDDR4__DENALI_CTL_385__MEM_RST_VALID 6745 6746#define LPDDR4__DENALI_CTL_386_READ_MASK 0x7FFFFFFFU 6747#define LPDDR4__DENALI_CTL_386_WRITE_MASK 0x7FFFFFFFU 6748#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_MASK 0x0000FFFFU 6749#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_SHIFT 0U 6750#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_WIDTH 16U 6751#define LPDDR4__DLL_RST_DELAY__REG DENALI_CTL_386 6752#define LPDDR4__DLL_RST_DELAY__FLD LPDDR4__DENALI_CTL_386__DLL_RST_DELAY 6753 6754#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_MASK 0x00FF0000U 6755#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_SHIFT 16U 6756#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_WIDTH 8U 6757#define LPDDR4__DLL_RST_ADJ_DLY__REG DENALI_CTL_386 6758#define LPDDR4__DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY 6759 6760#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_MASK 0x7F000000U 6761#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_SHIFT 24U 6762#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_WIDTH 7U 6763#define LPDDR4__TDFI_PHY_WRLAT__REG DENALI_CTL_386 6764#define LPDDR4__TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT 6765 6766#define LPDDR4__DENALI_CTL_387_READ_MASK 0x7F7F7F7FU 6767#define LPDDR4__DENALI_CTL_387_WRITE_MASK 0x7F7F7F7FU 6768#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_MASK 0x0000007FU 6769#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_SHIFT 0U 6770#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_WIDTH 7U 6771#define LPDDR4__UPDATE_ERROR_STATUS__REG DENALI_CTL_387 6772#define LPDDR4__UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS 6773 6774#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_MASK 0x00007F00U 6775#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_SHIFT 8U 6776#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_WIDTH 7U 6777#define LPDDR4__TDFI_PHY_RDLAT_F0__REG DENALI_CTL_387 6778#define LPDDR4__TDFI_PHY_RDLAT_F0__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0 6779 6780#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_MASK 0x007F0000U 6781#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_SHIFT 16U 6782#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_WIDTH 7U 6783#define LPDDR4__TDFI_PHY_RDLAT_F1__REG DENALI_CTL_387 6784#define LPDDR4__TDFI_PHY_RDLAT_F1__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1 6785 6786#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_MASK 0x7F000000U 6787#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_SHIFT 24U 6788#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_WIDTH 7U 6789#define LPDDR4__TDFI_PHY_RDLAT_F2__REG DENALI_CTL_387 6790#define LPDDR4__TDFI_PHY_RDLAT_F2__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2 6791 6792#define LPDDR4__DENALI_CTL_388_READ_MASK 0x00FF037FU 6793#define LPDDR4__DENALI_CTL_388_WRITE_MASK 0x00FF037FU 6794#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_MASK 0x0000007FU 6795#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_SHIFT 0U 6796#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_WIDTH 7U 6797#define LPDDR4__TDFI_RDDATA_EN__REG DENALI_CTL_388 6798#define LPDDR4__TDFI_RDDATA_EN__FLD LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN 6799 6800#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_MASK 0x00000300U 6801#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_SHIFT 8U 6802#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_WIDTH 2U 6803#define LPDDR4__DRAM_CLK_DISABLE__REG DENALI_CTL_388 6804#define LPDDR4__DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE 6805 6806#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_MASK 0x00FF0000U 6807#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_SHIFT 16U 6808#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_WIDTH 8U 6809#define LPDDR4__TDFI_CTRLUPD_MIN__REG DENALI_CTL_388 6810#define LPDDR4__TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN 6811 6812#define LPDDR4__DENALI_CTL_389_READ_MASK 0x001FFFFFU 6813#define LPDDR4__DENALI_CTL_389_WRITE_MASK 0x001FFFFFU 6814#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_MASK 0x001FFFFFU 6815#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_SHIFT 0U 6816#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_WIDTH 21U 6817#define LPDDR4__TDFI_CTRLUPD_MAX_F0__REG DENALI_CTL_389 6818#define LPDDR4__TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0 6819 6820#define LPDDR4__DENALI_CTL_390_READ_MASK 0xFFFFFFFFU 6821#define LPDDR4__DENALI_CTL_390_WRITE_MASK 0xFFFFFFFFU 6822#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_MASK 0xFFFFFFFFU 6823#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_SHIFT 0U 6824#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_WIDTH 32U 6825#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__REG DENALI_CTL_390 6826#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__FLD LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0 6827 6828#define LPDDR4__DENALI_CTL_391_READ_MASK 0xFFFFFFFFU 6829#define LPDDR4__DENALI_CTL_391_WRITE_MASK 0xFFFFFFFFU 6830#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_MASK 0xFFFFFFFFU 6831#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_SHIFT 0U 6832#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_WIDTH 32U 6833#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__REG DENALI_CTL_391 6834#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__FLD LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0 6835 6836#define LPDDR4__DENALI_CTL_392_READ_MASK 0xFFFFFFFFU 6837#define LPDDR4__DENALI_CTL_392_WRITE_MASK 0xFFFFFFFFU 6838#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_MASK 0xFFFFFFFFU 6839#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_SHIFT 0U 6840#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_WIDTH 32U 6841#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__REG DENALI_CTL_392 6842#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0 6843 6844#define LPDDR4__DENALI_CTL_393_READ_MASK 0xFFFFFFFFU 6845#define LPDDR4__DENALI_CTL_393_WRITE_MASK 0xFFFFFFFFU 6846#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_MASK 0xFFFFFFFFU 6847#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_SHIFT 0U 6848#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_WIDTH 32U 6849#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__REG DENALI_CTL_393 6850#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__FLD LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0 6851 6852#define LPDDR4__DENALI_CTL_394_READ_MASK 0x007FFFFFU 6853#define LPDDR4__DENALI_CTL_394_WRITE_MASK 0x007FFFFFU 6854#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_MASK 0x007FFFFFU 6855#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_SHIFT 0U 6856#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_WIDTH 23U 6857#define LPDDR4__TDFI_PHYUPD_RESP_F0__REG DENALI_CTL_394 6858#define LPDDR4__TDFI_PHYUPD_RESP_F0__FLD LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0 6859 6860#define LPDDR4__DENALI_CTL_395_READ_MASK 0xFFFFFFFFU 6861#define LPDDR4__DENALI_CTL_395_WRITE_MASK 0xFFFFFFFFU 6862#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU 6863#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U 6864#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U 6865#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_CTL_395 6866#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0 6867 6868#define LPDDR4__DENALI_CTL_396_READ_MASK 0x00007F7FU 6869#define LPDDR4__DENALI_CTL_396_WRITE_MASK 0x00007F7FU 6870#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_MASK 0x0000007FU 6871#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_SHIFT 0U 6872#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_WIDTH 7U 6873#define LPDDR4__RDLAT_ADJ_F0__REG DENALI_CTL_396 6874#define LPDDR4__RDLAT_ADJ_F0__FLD LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0 6875 6876#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_MASK 0x00007F00U 6877#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_SHIFT 8U 6878#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_WIDTH 7U 6879#define LPDDR4__WRLAT_ADJ_F0__REG DENALI_CTL_396 6880#define LPDDR4__WRLAT_ADJ_F0__FLD LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0 6881 6882#define LPDDR4__DENALI_CTL_397_READ_MASK 0x001FFFFFU 6883#define LPDDR4__DENALI_CTL_397_WRITE_MASK 0x001FFFFFU 6884#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU 6885#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_SHIFT 0U 6886#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_WIDTH 21U 6887#define LPDDR4__TDFI_CTRLUPD_MAX_F1__REG DENALI_CTL_397 6888#define LPDDR4__TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1 6889 6890#define LPDDR4__DENALI_CTL_398_READ_MASK 0xFFFFFFFFU 6891#define LPDDR4__DENALI_CTL_398_WRITE_MASK 0xFFFFFFFFU 6892#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_MASK 0xFFFFFFFFU 6893#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_SHIFT 0U 6894#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_WIDTH 32U 6895#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__REG DENALI_CTL_398 6896#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__FLD LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1 6897 6898#define LPDDR4__DENALI_CTL_399_READ_MASK 0xFFFFFFFFU 6899#define LPDDR4__DENALI_CTL_399_WRITE_MASK 0xFFFFFFFFU 6900#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_MASK 0xFFFFFFFFU 6901#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_SHIFT 0U 6902#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_WIDTH 32U 6903#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__REG DENALI_CTL_399 6904#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__FLD LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1 6905 6906#define LPDDR4__DENALI_CTL_400_READ_MASK 0xFFFFFFFFU 6907#define LPDDR4__DENALI_CTL_400_WRITE_MASK 0xFFFFFFFFU 6908#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_MASK 0xFFFFFFFFU 6909#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_SHIFT 0U 6910#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_WIDTH 32U 6911#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__REG DENALI_CTL_400 6912#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__FLD LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1 6913 6914#define LPDDR4__DENALI_CTL_401_READ_MASK 0xFFFFFFFFU 6915#define LPDDR4__DENALI_CTL_401_WRITE_MASK 0xFFFFFFFFU 6916#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_MASK 0xFFFFFFFFU 6917#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_SHIFT 0U 6918#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_WIDTH 32U 6919#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__REG DENALI_CTL_401 6920#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1 6921 6922#define LPDDR4__DENALI_CTL_402_READ_MASK 0x007FFFFFU 6923#define LPDDR4__DENALI_CTL_402_WRITE_MASK 0x007FFFFFU 6924#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_MASK 0x007FFFFFU 6925#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_SHIFT 0U 6926#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_WIDTH 23U 6927#define LPDDR4__TDFI_PHYUPD_RESP_F1__REG DENALI_CTL_402 6928#define LPDDR4__TDFI_PHYUPD_RESP_F1__FLD LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1 6929 6930#define LPDDR4__DENALI_CTL_403_READ_MASK 0xFFFFFFFFU 6931#define LPDDR4__DENALI_CTL_403_WRITE_MASK 0xFFFFFFFFU 6932#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU 6933#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U 6934#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U 6935#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_CTL_403 6936#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1 6937 6938#define LPDDR4__DENALI_CTL_404_READ_MASK 0x00007F7FU 6939#define LPDDR4__DENALI_CTL_404_WRITE_MASK 0x00007F7FU 6940#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_MASK 0x0000007FU 6941#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_SHIFT 0U 6942#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_WIDTH 7U 6943#define LPDDR4__RDLAT_ADJ_F1__REG DENALI_CTL_404 6944#define LPDDR4__RDLAT_ADJ_F1__FLD LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1 6945 6946#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_MASK 0x00007F00U 6947#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_SHIFT 8U 6948#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_WIDTH 7U 6949#define LPDDR4__WRLAT_ADJ_F1__REG DENALI_CTL_404 6950#define LPDDR4__WRLAT_ADJ_F1__FLD LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1 6951 6952#define LPDDR4__DENALI_CTL_405_READ_MASK 0x001FFFFFU 6953#define LPDDR4__DENALI_CTL_405_WRITE_MASK 0x001FFFFFU 6954#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU 6955#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_SHIFT 0U 6956#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_WIDTH 21U 6957#define LPDDR4__TDFI_CTRLUPD_MAX_F2__REG DENALI_CTL_405 6958#define LPDDR4__TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2 6959 6960#define LPDDR4__DENALI_CTL_406_READ_MASK 0xFFFFFFFFU 6961#define LPDDR4__DENALI_CTL_406_WRITE_MASK 0xFFFFFFFFU 6962#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_MASK 0xFFFFFFFFU 6963#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_SHIFT 0U 6964#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_WIDTH 32U 6965#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__REG DENALI_CTL_406 6966#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__FLD LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2 6967 6968#define LPDDR4__DENALI_CTL_407_READ_MASK 0xFFFFFFFFU 6969#define LPDDR4__DENALI_CTL_407_WRITE_MASK 0xFFFFFFFFU 6970#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_MASK 0xFFFFFFFFU 6971#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_SHIFT 0U 6972#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_WIDTH 32U 6973#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__REG DENALI_CTL_407 6974#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__FLD LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2 6975 6976#define LPDDR4__DENALI_CTL_408_READ_MASK 0xFFFFFFFFU 6977#define LPDDR4__DENALI_CTL_408_WRITE_MASK 0xFFFFFFFFU 6978#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_MASK 0xFFFFFFFFU 6979#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_SHIFT 0U 6980#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_WIDTH 32U 6981#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__REG DENALI_CTL_408 6982#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__FLD LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2 6983 6984#define LPDDR4__DENALI_CTL_409_READ_MASK 0xFFFFFFFFU 6985#define LPDDR4__DENALI_CTL_409_WRITE_MASK 0xFFFFFFFFU 6986#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_MASK 0xFFFFFFFFU 6987#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_SHIFT 0U 6988#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_WIDTH 32U 6989#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__REG DENALI_CTL_409 6990#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__FLD LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2 6991 6992#define LPDDR4__DENALI_CTL_410_READ_MASK 0x007FFFFFU 6993#define LPDDR4__DENALI_CTL_410_WRITE_MASK 0x007FFFFFU 6994#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_MASK 0x007FFFFFU 6995#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_SHIFT 0U 6996#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_WIDTH 23U 6997#define LPDDR4__TDFI_PHYUPD_RESP_F2__REG DENALI_CTL_410 6998#define LPDDR4__TDFI_PHYUPD_RESP_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2 6999 7000#define LPDDR4__DENALI_CTL_411_READ_MASK 0xFFFFFFFFU
7001#define LPDDR4__DENALI_CTL_411_WRITE_MASK 0xFFFFFFFFU 7002#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU 7003#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U 7004#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U 7005#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_CTL_411 7006#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2 7007 7008#define LPDDR4__DENALI_CTL_412_READ_MASK 0x0F0F7F7FU 7009#define LPDDR4__DENALI_CTL_412_WRITE_MASK 0x0F0F7F7FU 7010#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_MASK 0x0000007FU 7011#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_SHIFT 0U 7012#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_WIDTH 7U 7013#define LPDDR4__RDLAT_ADJ_F2__REG DENALI_CTL_412 7014#define LPDDR4__RDLAT_ADJ_F2__FLD LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2 7015 7016#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_MASK 0x00007F00U 7017#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_SHIFT 8U 7018#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_WIDTH 7U 7019#define LPDDR4__WRLAT_ADJ_F2__REG DENALI_CTL_412 7020#define LPDDR4__WRLAT_ADJ_F2__FLD LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2 7021 7022#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_MASK 0x000F0000U 7023#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_SHIFT 16U 7024#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_WIDTH 4U 7025#define LPDDR4__TDFI_CTRL_DELAY_F0__REG DENALI_CTL_412 7026#define LPDDR4__TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0 7027 7028#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_MASK 0x0F000000U 7029#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_SHIFT 24U 7030#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_WIDTH 4U 7031#define LPDDR4__TDFI_CTRL_DELAY_F1__REG DENALI_CTL_412 7032#define LPDDR4__TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1 7033 7034#define LPDDR4__DENALI_CTL_413_READ_MASK 0xFF0F0F0FU 7035#define LPDDR4__DENALI_CTL_413_WRITE_MASK 0xFF0F0F0FU 7036#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_MASK 0x0000000FU 7037#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_SHIFT 0U 7038#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_WIDTH 4U 7039#define LPDDR4__TDFI_CTRL_DELAY_F2__REG DENALI_CTL_413 7040#define LPDDR4__TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2 7041 7042#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_MASK 0x00000F00U 7043#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_SHIFT 8U 7044#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_WIDTH 4U 7045#define LPDDR4__TDFI_DRAM_CLK_DISABLE__REG DENALI_CTL_413 7046#define LPDDR4__TDFI_DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE 7047 7048#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_MASK 0x000F0000U 7049#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_SHIFT 16U 7050#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_WIDTH 4U 7051#define LPDDR4__TDFI_DRAM_CLK_ENABLE__REG DENALI_CTL_413 7052#define LPDDR4__TDFI_DRAM_CLK_ENABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE 7053 7054#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_MASK 0xFF000000U 7055#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_SHIFT 24U 7056#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_WIDTH 8U 7057#define LPDDR4__TDFI_WRLVL_EN__REG DENALI_CTL_413 7058#define LPDDR4__TDFI_WRLVL_EN__FLD LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN 7059 7060#define LPDDR4__DENALI_CTL_414_READ_MASK 0x000003FFU 7061#define LPDDR4__DENALI_CTL_414_WRITE_MASK 0x000003FFU 7062#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_MASK 0x000003FFU 7063#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_SHIFT 0U 7064#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_WIDTH 10U 7065#define LPDDR4__TDFI_WRLVL_WW__REG DENALI_CTL_414 7066#define LPDDR4__TDFI_WRLVL_WW__FLD LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW 7067 7068#define LPDDR4__DENALI_CTL_415_READ_MASK 0xFFFFFFFFU 7069#define LPDDR4__DENALI_CTL_415_WRITE_MASK 0xFFFFFFFFU 7070#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_MASK 0xFFFFFFFFU 7071#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_SHIFT 0U 7072#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_WIDTH 32U 7073#define LPDDR4__TDFI_WRLVL_RESP__REG DENALI_CTL_415 7074#define LPDDR4__TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP 7075 7076#define LPDDR4__DENALI_CTL_416_READ_MASK 0xFFFFFFFFU 7077#define LPDDR4__DENALI_CTL_416_WRITE_MASK 0xFFFFFFFFU 7078#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_MASK 0xFFFFFFFFU 7079#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_SHIFT 0U 7080#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_WIDTH 32U 7081#define LPDDR4__TDFI_WRLVL_MAX__REG DENALI_CTL_416 7082#define LPDDR4__TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX 7083 7084#define LPDDR4__DENALI_CTL_417_READ_MASK 0x0003FFFFU 7085#define LPDDR4__DENALI_CTL_417_WRITE_MASK 0x0003FFFFU 7086#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_MASK 0x000000FFU 7087#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_SHIFT 0U 7088#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_WIDTH 8U 7089#define LPDDR4__TDFI_RDLVL_EN__REG DENALI_CTL_417 7090#define LPDDR4__TDFI_RDLVL_EN__FLD LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN 7091 7092#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_MASK 0x0003FF00U 7093#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_SHIFT 8U 7094#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_WIDTH 10U 7095#define LPDDR4__TDFI_RDLVL_RR__REG DENALI_CTL_417 7096#define LPDDR4__TDFI_RDLVL_RR__FLD LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR 7097 7098#define LPDDR4__DENALI_CTL_418_READ_MASK 0xFFFFFFFFU 7099#define LPDDR4__DENALI_CTL_418_WRITE_MASK 0xFFFFFFFFU 7100#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_MASK 0xFFFFFFFFU 7101#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_SHIFT 0U 7102#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_WIDTH 32U 7103#define LPDDR4__TDFI_RDLVL_RESP__REG DENALI_CTL_418 7104#define LPDDR4__TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP 7105 7106#define LPDDR4__DENALI_CTL_419_READ_MASK 0x000101FFU 7107#define LPDDR4__DENALI_CTL_419_WRITE_MASK 0x000101FFU 7108#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_MASK 0x000000FFU 7109#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_SHIFT 0U 7110#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_WIDTH 8U 7111#define LPDDR4__RDLVL_RESP_MASK__REG DENALI_CTL_419 7112#define LPDDR4__RDLVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK 7113 7114#define LPDDR4__DENALI_CTL_419__RDLVL_EN_MASK 0x00000100U 7115#define LPDDR4__DENALI_CTL_419__RDLVL_EN_SHIFT 8U 7116#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WIDTH 1U 7117#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOCLR 0U 7118#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOSET 0U 7119#define LPDDR4__RDLVL_EN__REG DENALI_CTL_419 7120#define LPDDR4__RDLVL_EN__FLD LPDDR4__DENALI_CTL_419__RDLVL_EN 7121 7122#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_MASK 0x00010000U 7123#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_SHIFT 16U 7124#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WIDTH 1U 7125#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOCLR 0U 7126#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOSET 0U 7127#define LPDDR4__RDLVL_GATE_EN__REG DENALI_CTL_419 7128#define LPDDR4__RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN 7129 7130#define LPDDR4__DENALI_CTL_420_READ_MASK 0xFFFFFFFFU 7131#define LPDDR4__DENALI_CTL_420_WRITE_MASK 0xFFFFFFFFU 7132#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_MASK 0xFFFFFFFFU 7133#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_SHIFT 0U 7134#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_WIDTH 32U 7135#define LPDDR4__TDFI_RDLVL_MAX__REG DENALI_CTL_420 7136#define LPDDR4__TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX 7137 7138#define LPDDR4__DENALI_CTL_421_READ_MASK 0x00FF0707U 7139#define LPDDR4__DENALI_CTL_421_WRITE_MASK 0x00FF0707U 7140#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_MASK 0x00000007U 7141#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_SHIFT 0U 7142#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_WIDTH 3U 7143#define LPDDR4__RDLVL_ERROR_STATUS__REG DENALI_CTL_421 7144#define LPDDR4__RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS 7145 7146#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_MASK 0x00000700U 7147#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_SHIFT 8U 7148#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_WIDTH 3U 7149#define LPDDR4__RDLVL_GATE_ERROR_STATUS__REG DENALI_CTL_421 7150#define LPDDR4__RDLVL_GATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS 7151 7152#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_MASK 0x00FF0000U 7153#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_SHIFT 16U 7154#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_WIDTH 8U 7155#define LPDDR4__TDFI_CALVL_EN__REG DENALI_CTL_421 7156#define LPDDR4__TDFI_CALVL_EN__FLD LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN 7157 7158#define LPDDR4__DENALI_CTL_422_READ_MASK 0x03FF03FFU 7159#define LPDDR4__DENALI_CTL_422_WRITE_MASK 0x03FF03FFU 7160#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_MASK 0x000003FFU 7161#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_SHIFT 0U 7162#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_WIDTH 10U 7163#define LPDDR4__TDFI_CALVL_CC_F0__REG DENALI_CTL_422 7164#define LPDDR4__TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0 7165 7166#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_MASK 0x03FF0000U 7167#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_SHIFT 16U 7168#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_WIDTH 10U 7169#define LPDDR4__TDFI_CALVL_CAPTURE_F0__REG DENALI_CTL_422 7170#define LPDDR4__TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0 7171 7172#define LPDDR4__DENALI_CTL_423_READ_MASK 0x03FF03FFU 7173#define LPDDR4__DENALI_CTL_423_WRITE_MASK 0x03FF03FFU 7174#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_MASK 0x000003FFU 7175#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_SHIFT 0U 7176#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_WIDTH 10U 7177#define LPDDR4__TDFI_CALVL_CC_F1__REG DENALI_CTL_423 7178#define LPDDR4__TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1 7179 7180#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_MASK 0x03FF0000U 7181#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_SHIFT 16U 7182#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_WIDTH 10U 7183#define LPDDR4__TDFI_CALVL_CAPTURE_F1__REG DENALI_CTL_423 7184#define LPDDR4__TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1 7185 7186#define LPDDR4__DENALI_CTL_424_READ_MASK 0x03FF03FFU 7187#define LPDDR4__DENALI_CTL_424_WRITE_MASK 0x03FF03FFU 7188#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_MASK 0x000003FFU 7189#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_SHIFT 0U 7190#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_WIDTH 10U 7191#define LPDDR4__TDFI_CALVL_CC_F2__REG DENALI_CTL_424 7192#define LPDDR4__TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2 7193 7194#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_MASK 0x03FF0000U 7195#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_SHIFT 16U 7196#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_WIDTH 10U 7197#define LPDDR4__TDFI_CALVL_CAPTURE_F2__REG DENALI_CTL_424 7198#define LPDDR4__TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2 7199 7200#define LPDDR4__DENALI_CTL_425_READ_MASK 0xFFFFFFFFU 7201#define LPDDR4__DENALI_CTL_425_WRITE_MASK 0xFFFFFFFFU 7202#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_MASK 0xFFFFFFFFU 7203#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_SHIFT 0U 7204#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_WIDTH 32U 7205#define LPDDR4__TDFI_CALVL_RESP__REG DENALI_CTL_425 7206#define LPDDR4__TDFI_CALVL_RESP__FLD LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP 7207 7208#define LPDDR4__DENALI_CTL_426_READ_MASK 0xFFFFFFFFU 7209#define LPDDR4__DENALI_CTL_426_WRITE_MASK 0xFFFFFFFFU 7210#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_MASK 0xFFFFFFFFU 7211#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_SHIFT 0U 7212#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_WIDTH 32U 7213#define LPDDR4__TDFI_CALVL_MAX__REG DENALI_CTL_426 7214#define LPDDR4__TDFI_CALVL_MAX__FLD LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX 7215 7216#define LPDDR4__DENALI_CTL_427_READ_MASK 0x070F0101U 7217#define LPDDR4__DENALI_CTL_427_WRITE_MASK 0x070F0101U 7218#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_MASK 0x00000001U 7219#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_SHIFT 0U 7220#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WIDTH 1U 7221#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOCLR 0U 7222#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOSET 0U 7223#define LPDDR4__CALVL_RESP_MASK__REG DENALI_CTL_427 7224#define LPDDR4__CALVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK 7225 7226#define LPDDR4__DENALI_CTL_427__CALVL_EN_MASK 0x00000100U 7227#define LPDDR4__DENALI_CTL_427__CALVL_EN_SHIFT 8U 7228#define LPDDR4__DENALI_CTL_427__CALVL_EN_WIDTH 1U 7229#define LPDDR4__DENALI_CTL_427__CALVL_EN_WOCLR 0U 7230#define LPDDR4__DENALI_CTL_427__CALVL_EN_WOSET 0U 7231#define LPDDR4__CALVL_EN__REG DENALI_CTL_427 7232#define LPDDR4__CALVL_EN__FLD LPDDR4__DENALI_CTL_427__CALVL_EN 7233 7234#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_MASK 0x000F0000U 7235#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_SHIFT 16U 7236#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_WIDTH 4U 7237#define LPDDR4__CALVL_ERROR_STATUS__REG DENALI_CTL_427 7238#define LPDDR4__CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS 7239 7240#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_MASK 0x07000000U 7241#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_SHIFT 24U 7242#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_WIDTH 3U 7243#define LPDDR4__TDFI_PHY_WRDATA_F0__REG DENALI_CTL_427 7244#define LPDDR4__TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0 7245 7246#define LPDDR4__DENALI_CTL_428_READ_MASK 0x7F7F0707U 7247#define LPDDR4__DENALI_CTL_428_WRITE_MASK 0x7F7F0707U 7248#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_MASK 0x00000007U 7249#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_SHIFT 0U 7250#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_WIDTH 3U 7251#define LPDDR4__TDFI_PHY_WRDATA_F1__REG DENALI_CTL_428 7252#define LPDDR4__TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1 7253 7254#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_MASK 0x00000700U 7255#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_SHIFT 8U 7256#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_WIDTH 3U 7257#define LPDDR4__TDFI_PHY_WRDATA_F2__REG DENALI_CTL_428 7258#define LPDDR4__TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2 7259 7260#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_MASK 0x007F0000U 7261#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_SHIFT 16U 7262#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_WIDTH 7U 7263#define LPDDR4__TDFI_RDCSLAT_F0__REG DENALI_CTL_428 7264#define LPDDR4__TDFI_RDCSLAT_F0__FLD LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0 7265 7266#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_MASK 0x7F000000U 7267#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_SHIFT 24U 7268#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_WIDTH 7U 7269#define LPDDR4__TDFI_WRCSLAT_F0__REG DENALI_CTL_428 7270#define LPDDR4__TDFI_WRCSLAT_F0__FLD LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0 7271 7272#define LPDDR4__DENALI_CTL_429_READ_MASK 0x7F7F7F7FU 7273#define LPDDR4__DENALI_CTL_429_WRITE_MASK 0x7F7F7F7FU 7274#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_MASK 0x0000007FU 7275#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_SHIFT 0U 7276#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_WIDTH 7U 7277#define LPDDR4__TDFI_RDCSLAT_F1__REG DENALI_CTL_429 7278#define LPDDR4__TDFI_RDCSLAT_F1__FLD LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1 7279 7280#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_MASK 0x00007F00U 7281#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_SHIFT 8U 7282#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_WIDTH 7U 7283#define LPDDR4__TDFI_WRCSLAT_F1__REG DENALI_CTL_429 7284#define LPDDR4__TDFI_WRCSLAT_F1__FLD LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1 7285 7286#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_MASK 0x007F0000U 7287#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_SHIFT 16U 7288#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_WIDTH 7U 7289#define LPDDR4__TDFI_RDCSLAT_F2__REG DENALI_CTL_429 7290#define LPDDR4__TDFI_RDCSLAT_F2__FLD LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2 7291 7292#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_MASK 0x7F000000U 7293#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_SHIFT 24U 7294#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_WIDTH 7U 7295#define LPDDR4__TDFI_WRCSLAT_F2__REG DENALI_CTL_429 7296#define LPDDR4__TDFI_WRCSLAT_F2__FLD LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2 7297 7298#define LPDDR4__DENALI_CTL_430_READ_MASK 0x010101FFU 7299#define LPDDR4__DENALI_CTL_430_WRITE_MASK 0x010101FFU 7300#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_MASK 0x000000FFU 7301#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_SHIFT 0U 7302#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_WIDTH 8U 7303#define LPDDR4__TDFI_WRDATA_DELAY__REG DENALI_CTL_430 7304#define LPDDR4__TDFI_WRDATA_DELAY__FLD LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY 7305 7306#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_MASK 0x00000100U 7307#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_SHIFT 8U 7308#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WIDTH 1U 7309#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOCLR 0U 7310#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOSET 0U 7311#define LPDDR4__EN_1T_TIMING__REG DENALI_CTL_430 7312#define LPDDR4__EN_1T_TIMING__FLD LPDDR4__DENALI_CTL_430__EN_1T_TIMING 7313 7314#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_MASK 0x00010000U 7315#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_SHIFT 16U 7316#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WIDTH 1U 7317#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WOCLR 0U 7318#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WOSET 0U 7319#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__REG DENALI_CTL_430 7320#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__FLD LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE 7321 7322#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_MASK 0x01000000U 7323#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_SHIFT 24U 7324#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WIDTH 1U 7325#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOCLR 0U 7326#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOSET 0U 7327#define LPDDR4__BL_ON_FLY_ENABLE__REG DENALI_CTL_430 7328#define LPDDR4__BL_ON_FLY_ENABLE__FLD LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE 7329 7330#define LPDDR4__DENALI_CTL_431_READ_MASK 0x07070701U 7331#define LPDDR4__DENALI_CTL_431_WRITE_MASK 0x07070701U 7332#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_MASK 0x00000001U 7333#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_SHIFT 0U 7334#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WIDTH 1U 7335#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOCLR 0U 7336#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOSET 0U 7337#define LPDDR4__MC_RESERVED32__REG DENALI_CTL_431 7338#define LPDDR4__MC_RESERVED32__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED32 7339 7340#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_MASK 0x00000700U 7341#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_SHIFT 8U 7342#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_WIDTH 3U 7343#define LPDDR4__MC_RESERVED33__REG DENALI_CTL_431 7344#define LPDDR4__MC_RESERVED33__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED33 7345 7346#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_MASK 0x00070000U 7347#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_SHIFT 16U 7348#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_WIDTH 3U 7349#define LPDDR4__MC_RESERVED34__REG DENALI_CTL_431 7350#define LPDDR4__MC_RESERVED34__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED34 7351 7352#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_MASK 0x07000000U 7353#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_SHIFT 24U 7354#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_WIDTH 3U 7355#define LPDDR4__MC_RESERVED35__REG DENALI_CTL_431 7356#define LPDDR4__MC_RESERVED35__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED35 7357 7358#define LPDDR4__DENALI_CTL_432_READ_MASK 0x0F070707U 7359#define LPDDR4__DENALI_CTL_432_WRITE_MASK 0x0F070707U 7360#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_MASK 0x00000007U 7361#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_SHIFT 0U 7362#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_WIDTH 3U 7363#define LPDDR4__MC_RESERVED36__REG DENALI_CTL_432 7364#define LPDDR4__MC_RESERVED36__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED36 7365 7366#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_MASK 0x00000700U 7367#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_SHIFT 8U 7368#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_WIDTH 3U 7369#define LPDDR4__MC_RESERVED37__REG DENALI_CTL_432 7370#define LPDDR4__MC_RESERVED37__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED37 7371 7372#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_MASK 0x00070000U 7373#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_SHIFT 16U 7374#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_WIDTH 3U 7375#define LPDDR4__MC_RESERVED38__REG DENALI_CTL_432 7376#define LPDDR4__MC_RESERVED38__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED38 7377 7378#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_MASK 0x0F000000U 7379#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_SHIFT 24U 7380#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_WIDTH 4U 7381#define LPDDR4__MC_RESERVED39__REG DENALI_CTL_432 7382#define LPDDR4__MC_RESERVED39__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED39 7383 7384#define LPDDR4__DENALI_CTL_433_READ_MASK 0x0F0F0F0FU 7385#define LPDDR4__DENALI_CTL_433_WRITE_MASK 0x0F0F0F0FU 7386#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_MASK 0x0000000FU 7387#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_SHIFT 0U 7388#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_WIDTH 4U 7389#define LPDDR4__MC_RESERVED40__REG DENALI_CTL_433 7390#define LPDDR4__MC_RESERVED40__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED40 7391 7392#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_MASK 0x00000F00U 7393#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_SHIFT 8U 7394#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_WIDTH 4U 7395#define LPDDR4__MC_RESERVED41__REG DENALI_CTL_433 7396#define LPDDR4__MC_RESERVED41__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED41 7397 7398#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_MASK 0x000F0000U 7399#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_SHIFT 16U 7400#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_WIDTH 4U 7401#define LPDDR4__MC_RESERVED42__REG DENALI_CTL_433 7402#define LPDDR4__MC_RESERVED42__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED42 7403 7404#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_MASK 0x0F000000U 7405#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_SHIFT 24U 7406#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_WIDTH 4U 7407#define LPDDR4__MC_RESERVED43__REG DENALI_CTL_433 7408#define LPDDR4__MC_RESERVED43__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED43 7409 7410#define LPDDR4__DENALI_CTL_434_READ_MASK 0x0F0F0F0FU 7411#define LPDDR4__DENALI_CTL_434_WRITE_MASK 0x0F0F0F0FU 7412#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_MASK 0x0000000FU 7413#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_SHIFT 0U 7414#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_WIDTH 4U 7415#define LPDDR4__MC_RESERVED44__REG DENALI_CTL_434 7416#define LPDDR4__MC_RESERVED44__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED44 7417 7418#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_MASK 0x00000F00U 7419#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_SHIFT 8U 7420#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_WIDTH 4U 7421#define LPDDR4__MC_RESERVED45__REG DENALI_CTL_434 7422#define LPDDR4__MC_RESERVED45__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED45 7423 7424#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_MASK 0x000F0000U 7425#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_SHIFT 16U 7426#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_WIDTH 4U 7427#define LPDDR4__MC_RESERVED46__REG DENALI_CTL_434 7428#define LPDDR4__MC_RESERVED46__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED46 7429 7430#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_MASK 0x0F000000U 7431#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_SHIFT 24U 7432#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_WIDTH 4U 7433#define LPDDR4__MC_RESERVED47__REG DENALI_CTL_434 7434#define LPDDR4__MC_RESERVED47__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED47 7435 7436#define LPDDR4__DENALI_CTL_435_READ_MASK 0x0F0F0F0FU 7437#define LPDDR4__DENALI_CTL_435_WRITE_MASK 0x0F0F0F0FU 7438#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_MASK 0x0000000FU 7439#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_SHIFT 0U 7440#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_WIDTH 4U 7441#define LPDDR4__MC_RESERVED48__REG DENALI_CTL_435 7442#define LPDDR4__MC_RESERVED48__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED48 7443 7444#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_MASK 0x00000F00U 7445#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_SHIFT 8U 7446#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_WIDTH 4U 7447#define LPDDR4__MC_RESERVED49__REG DENALI_CTL_435 7448#define LPDDR4__MC_RESERVED49__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED49 7449 7450#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_MASK 0x000F0000U 7451#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_SHIFT 16U 7452#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_WIDTH 4U 7453#define LPDDR4__MC_RESERVED50__REG DENALI_CTL_435 7454#define LPDDR4__MC_RESERVED50__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED50 7455 7456#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_MASK 0x0F000000U 7457#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_SHIFT 24U 7458#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_WIDTH 4U 7459#define LPDDR4__MC_RESERVED51__REG DENALI_CTL_435 7460#define LPDDR4__MC_RESERVED51__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED51 7461 7462#define LPDDR4__DENALI_CTL_436_READ_MASK 0x0F0F0F0FU 7463#define LPDDR4__DENALI_CTL_436_WRITE_MASK 0x0F0F0F0FU 7464#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_MASK 0x0000000FU 7465#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_SHIFT 0U 7466#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_WIDTH 4U 7467#define LPDDR4__MC_RESERVED52__REG DENALI_CTL_436 7468#define LPDDR4__MC_RESERVED52__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED52 7469 7470#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_MASK 0x00000F00U 7471#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_SHIFT 8U 7472#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_WIDTH 4U 7473#define LPDDR4__MC_RESERVED53__REG DENALI_CTL_436 7474#define LPDDR4__MC_RESERVED53__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED53 7475 7476#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_MASK 0x000F0000U 7477#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_SHIFT 16U 7478#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_WIDTH 4U 7479#define LPDDR4__MC_RESERVED54__REG DENALI_CTL_436 7480#define LPDDR4__MC_RESERVED54__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED54 7481 7482#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_MASK 0x0F000000U 7483#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_SHIFT 24U 7484#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_WIDTH 4U 7485#define LPDDR4__MC_RESERVED55__REG DENALI_CTL_436 7486#define LPDDR4__MC_RESERVED55__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED55 7487 7488#define LPDDR4__DENALI_CTL_437_READ_MASK 0xFF0F0F0FU 7489#define LPDDR4__DENALI_CTL_437_WRITE_MASK 0xFF0F0F0FU 7490#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_MASK 0x0000000FU 7491#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_SHIFT 0U 7492#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_WIDTH 4U 7493#define LPDDR4__MC_RESERVED56__REG DENALI_CTL_437 7494#define LPDDR4__MC_RESERVED56__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED56 7495 7496#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_MASK 0x00000F00U 7497#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_SHIFT 8U 7498#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_WIDTH 4U 7499#define LPDDR4__MC_RESERVED57__REG DENALI_CTL_437 7500#define LPDDR4__MC_RESERVED57__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED57 7501 7502#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_MASK 0x000F0000U 7503#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_SHIFT 16U 7504#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_WIDTH 4U 7505#define LPDDR4__MC_RESERVED58__REG DENALI_CTL_437 7506#define LPDDR4__MC_RESERVED58__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED58 7507 7508#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_MASK 0xFF000000U 7509#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_SHIFT 24U 7510#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_WIDTH 8U 7511#define LPDDR4__GLOBAL_ERROR_INFO__REG DENALI_CTL_437 7512#define LPDDR4__GLOBAL_ERROR_INFO__FLD LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO 7513 7514#define LPDDR4__DENALI_CTL_438_READ_MASK 0xFFFF03FFU 7515#define LPDDR4__DENALI_CTL_438_WRITE_MASK 0xFFFF03FFU 7516#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_MASK 0x000000FFU 7517#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_SHIFT 0U 7518#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_WIDTH 8U 7519#define LPDDR4__GLOBAL_ERROR_MASK__REG DENALI_CTL_438 7520#define LPDDR4__GLOBAL_ERROR_MASK__FLD LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK 7521 7522#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_MASK 0x00000300U 7523#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_SHIFT 8U 7524#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_WIDTH 2U 7525#define LPDDR4__AXI_PARITY_ERROR_STATUS__REG DENALI_CTL_438 7526#define LPDDR4__AXI_PARITY_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS 7527 7528#define LPDDR4__DENALI_CTL_438__NWR_F0_MASK 0x00FF0000U 7529#define LPDDR4__DENALI_CTL_438__NWR_F0_SHIFT 16U 7530#define LPDDR4__DENALI_CTL_438__NWR_F0_WIDTH 8U 7531#define LPDDR4__NWR_F0__REG DENALI_CTL_438 7532#define LPDDR4__NWR_F0__FLD LPDDR4__DENALI_CTL_438__NWR_F0 7533 7534#define LPDDR4__DENALI_CTL_438__NWR_F1_MASK 0xFF000000U 7535#define LPDDR4__DENALI_CTL_438__NWR_F1_SHIFT 24U 7536#define LPDDR4__DENALI_CTL_438__NWR_F1_WIDTH 8U 7537#define LPDDR4__NWR_F1__REG DENALI_CTL_438 7538#define LPDDR4__NWR_F1__FLD LPDDR4__DENALI_CTL_438__NWR_F1 7539 7540#define LPDDR4__DENALI_CTL_439_READ_MASK 0x001F01FFU 7541#define LPDDR4__DENALI_CTL_439_WRITE_MASK 0x001F01FFU 7542#define LPDDR4__DENALI_CTL_439__NWR_F2_MASK 0x000000FFU 7543#define LPDDR4__DENALI_CTL_439__NWR_F2_SHIFT 0U 7544#define LPDDR4__DENALI_CTL_439__NWR_F2_WIDTH 8U 7545#define LPDDR4__NWR_F2__REG DENALI_CTL_439 7546#define LPDDR4__NWR_F2__FLD LPDDR4__DENALI_CTL_439__NWR_F2 7547 7548#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_MASK 0x00000100U 7549#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_SHIFT 8U 7550#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WIDTH 1U 7551#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOCLR 0U 7552#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOSET 0U 7553#define LPDDR4__MC_RESERVED59__REG DENALI_CTL_439 7554#define LPDDR4__MC_RESERVED59__FLD LPDDR4__DENALI_CTL_439__MC_RESERVED59 7555 7556#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_MASK 0x001F0000U 7557#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_SHIFT 16U 7558#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_WIDTH 5U 7559#define LPDDR4__REGPORT_PARAM_PARITY_PROTECTION_STATUS__REG DENALI_CTL_439 7560#define LPDDR4__REGPORT_PARAM_PARITY_PROTECTION_STATUS__FLD LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS 7561 7562#define LPDDR4__DENALI_CTL_440_READ_MASK 0xFFFFFFFFU 7563#define LPDDR4__DENALI_CTL_440_WRITE_MASK 0xFFFFFFFFU 7564#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_MASK 0xFFFFFFFFU 7565#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_SHIFT 0U 7566#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_WIDTH 32U 7567#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_0__REG DENALI_CTL_440 7568#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_0__FLD LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0 7569 7570#define LPDDR4__DENALI_CTL_441_READ_MASK 0xFFFFFFFFU 7571#define LPDDR4__DENALI_CTL_441_WRITE_MASK 0xFFFFFFFFU 7572#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_MASK 0xFFFFFFFFU 7573#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_SHIFT 0U 7574#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_WIDTH 32U 7575#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_1__REG DENALI_CTL_441 7576#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_1__FLD LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1 7577 7578#define LPDDR4__DENALI_CTL_442_READ_MASK 0x01010101U 7579#define LPDDR4__DENALI_CTL_442_WRITE_MASK 0x01010101U 7580#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_MASK 0x00000001U 7581#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_SHIFT 0U 7582#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WIDTH 1U 7583#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOCLR 0U 7584#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOSET 0U 7585#define LPDDR4__MC_PARITY_ERROR_TYPE__REG DENALI_CTL_442 7586#define LPDDR4__MC_PARITY_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE 7587 7588#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_MASK 0x00000100U 7589#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_SHIFT 8U 7590#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WIDTH 1U 7591#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WOCLR 0U 7592#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WOSET 0U 7593#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_EN__REG DENALI_CTL_442 7594#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN 7595 7596#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_MASK 0x00010000U 7597#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_SHIFT 16U 7598#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WIDTH 1U 7599#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WOCLR 0U 7600#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WOSET 0U 7601#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_EN__REG DENALI_CTL_442 7602#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN 7603 7604#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_MASK 0x01000000U 7605#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_SHIFT 24U 7606#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WIDTH 1U 7607#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WOCLR 0U 7608#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WOSET 0U 7609#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_EN__REG DENALI_CTL_442 7610#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN 7611 7612#define LPDDR4__DENALI_CTL_443_READ_MASK 0x01010101U 7613#define LPDDR4__DENALI_CTL_443_WRITE_MASK 0x01010101U 7614#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_MASK 0x00000001U 7615#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_SHIFT 0U 7616#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WIDTH 1U 7617#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WOCLR 0U 7618#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WOSET 0U 7619#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_EN__REG DENALI_CTL_443 7620#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN 7621 7622#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_MASK 0x00000100U 7623#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_SHIFT 8U 7624#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WIDTH 1U 7625#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WOCLR 0U 7626#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WOSET 0U 7627#define LPDDR4__PARAMREG_PARITY_PROTECTION_EN__REG DENALI_CTL_443 7628#define LPDDR4__PARAMREG_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN 7629 7630#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_MASK 0x00010000U 7631#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_SHIFT 16U 7632#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U 7633#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U 7634#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WOSET 0U 7635#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_443 7636#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN 7637 7638#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_MASK 0x01000000U 7639#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_SHIFT 24U 7640#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U 7641#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U 7642#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WOSET 0U 7643#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_443 7644#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN 7645 7646#define LPDDR4__DENALI_CTL_444_READ_MASK 0x00010101U 7647#define LPDDR4__DENALI_CTL_444_WRITE_MASK 0x00010101U 7648#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_MASK 0x00000001U 7649#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_SHIFT 0U 7650#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U 7651#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U 7652#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WOSET 0U 7653#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444 7654#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN 7655 7656#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_MASK 0x00000100U 7657#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_SHIFT 8U 7658#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U 7659#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U 7660#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WOSET 0U 7661#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444 7662#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN 7663 7664#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_MASK 0x00010000U 7665#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_SHIFT 16U 7666#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U 7667#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U 7668#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WOSET 0U 7669#define LPDDR4__PARAMREG_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444 7670#define LPDDR4__PARAMREG_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN 7671 7672#define LPDDR4__DENALI_CTL_445_READ_MASK 0xFFFFFFFFU 7673#define LPDDR4__DENALI_CTL_445_WRITE_MASK 0xFFFFFFFFU 7674#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_MASK 0xFFFFFFFFU 7675#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_SHIFT 0U 7676#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_WIDTH 32U 7677#define LPDDR4__MC_RESERVED60_0__REG DENALI_CTL_445 7678#define LPDDR4__MC_RESERVED60_0__FLD LPDDR4__DENALI_CTL_445__MC_RESERVED60_0 7679 7680#define LPDDR4__DENALI_CTL_446_READ_MASK 0xFFFFFFFFU 7681#define LPDDR4__DENALI_CTL_446_WRITE_MASK 0xFFFFFFFFU 7682#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_MASK 0xFFFFFFFFU 7683#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_SHIFT 0U 7684#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_WIDTH 32U 7685#define LPDDR4__MC_RESERVED60_1__REG DENALI_CTL_446 7686#define LPDDR4__MC_RESERVED60_1__FLD LPDDR4__DENALI_CTL_446__MC_RESERVED60_1 7687 7688#define LPDDR4__DENALI_CTL_447_READ_MASK 0x00000107U 7689#define LPDDR4__DENALI_CTL_447_WRITE_MASK 0x00000107U 7690#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_MASK 0x00000007U 7691#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_SHIFT 0U 7692#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_WIDTH 3U 7693#define LPDDR4__MC_RESERVED60_2__REG DENALI_CTL_447 7694#define LPDDR4__MC_RESERVED60_2__FLD LPDDR4__DENALI_CTL_447__MC_RESERVED60_2 7695 7696#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_MASK 0x00000100U 7697#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_SHIFT 8U 7698#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WIDTH 1U 7699#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WOCLR 0U 7700#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WOSET 0U 7701#define LPDDR4__PORT_TO_CORE_PROTECTION_EN__REG DENALI_CTL_447 7702#define LPDDR4__PORT_TO_CORE_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN 7703 7704#define LPDDR4__DENALI_CTL_448_READ_MASK 0xFFFFFFFFU 7705#define LPDDR4__DENALI_CTL_448_WRITE_MASK 0xFFFFFFFFU 7706#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_MASK 0xFFFFFFFFU 7707#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_SHIFT 0U 7708#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_WIDTH 32U 7709#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_0__REG DENALI_CTL_448 7710#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_0__FLD LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0 7711 7712#define LPDDR4__DENALI_CTL_449_READ_MASK 0xFFFFFFFFU 7713#define LPDDR4__DENALI_CTL_449_WRITE_MASK 0xFFFFFFFFU 7714#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_MASK 0xFFFFFFFFU 7715#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_SHIFT 0U 7716#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_WIDTH 32U 7717#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_1__REG DENALI_CTL_449 7718#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_1__FLD LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1 7719 7720#define LPDDR4__DENALI_CTL_450_READ_MASK 0x00000007U 7721#define LPDDR4__DENALI_CTL_450_WRITE_MASK 0x00000007U 7722#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_MASK 0x00000007U 7723#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_SHIFT 0U 7724#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_WIDTH 3U 7725#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_2__REG DENALI_CTL_450 7726#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_2__FLD LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2 7727 7728#define LPDDR4__DENALI_CTL_451_READ_MASK 0xFFFFFFFFU 7729#define LPDDR4__DENALI_CTL_451_WRITE_MASK 0xFFFFFFFFU 7730#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_MASK 0xFFFFFFFFU 7731#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_SHIFT 0U 7732#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_WIDTH 32U 7733#define LPDDR4__MC_RESERVED61_0__REG DENALI_CTL_451 7734#define LPDDR4__MC_RESERVED61_0__FLD LPDDR4__DENALI_CTL_451__MC_RESERVED61_0 7735 7736#define LPDDR4__DENALI_CTL_452_READ_MASK 0xFFFFFFFFU 7737#define LPDDR4__DENALI_CTL_452_WRITE_MASK 0xFFFFFFFFU 7738#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_MASK 0xFFFFFFFFU 7739#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_SHIFT 0U 7740#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_WIDTH 32U 7741#define LPDDR4__MC_RESERVED61_1__REG DENALI_CTL_452 7742#define LPDDR4__MC_RESERVED61_1__FLD LPDDR4__DENALI_CTL_452__MC_RESERVED61_1 7743 7744#define LPDDR4__DENALI_CTL_453_READ_MASK 0xFFFFFFFFU 7745#define LPDDR4__DENALI_CTL_453_WRITE_MASK 0xFFFFFFFFU 7746#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_MASK 0xFFFFFFFFU 7747#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_SHIFT 0U 7748#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_WIDTH 32U 7749#define LPDDR4__MC_RESERVED61_2__REG DENALI_CTL_453 7750#define LPDDR4__MC_RESERVED61_2__FLD LPDDR4__DENALI_CTL_453__MC_RESERVED61_2 7751 7752#define LPDDR4__DENALI_CTL_454_READ_MASK 0x0000000FU 7753#define LPDDR4__DENALI_CTL_454_WRITE_MASK 0x0000000FU 7754#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_MASK 0x0000000FU 7755#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_SHIFT 0U 7756#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_WIDTH 4U 7757#define LPDDR4__MC_RESERVED61_3__REG DENALI_CTL_454 7758#define LPDDR4__MC_RESERVED61_3__FLD LPDDR4__DENALI_CTL_454__MC_RESERVED61_3 7759 7760#define LPDDR4__DENALI_CTL_455_READ_MASK 0xFFFFFFFFU 7761#define LPDDR4__DENALI_CTL_455_WRITE_MASK 0xFFFFFFFFU 7762#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_MASK 0xFFFFFFFFU 7763#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_SHIFT 0U 7764#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_WIDTH 32U 7765#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_0__REG DENALI_CTL_455 7766#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_0__FLD LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0 7767 7768#define LPDDR4__DENALI_CTL_456_READ_MASK 0xFFFFFFFFU 7769#define LPDDR4__DENALI_CTL_456_WRITE_MASK 0xFFFFFFFFU 7770#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_MASK 0xFFFFFFFFU 7771#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_SHIFT 0U 7772#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_WIDTH 32U 7773#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_1__REG DENALI_CTL_456 7774#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_1__FLD LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1 7775 7776#define LPDDR4__DENALI_CTL_457_READ_MASK 0xFFFFFFFFU 7777#define LPDDR4__DENALI_CTL_457_WRITE_MASK 0xFFFFFFFFU 7778#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_MASK 0xFFFFFFFFU 7779#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_SHIFT 0U 7780#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_WIDTH 32U 7781#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_2__REG DENALI_CTL_457 7782#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_2__FLD LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2 7783 7784#define LPDDR4__DENALI_CTL_458_READ_MASK 0x0000000FU 7785#define LPDDR4__DENALI_CTL_458_WRITE_MASK 0x0000000FU 7786#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_MASK 0x0000000FU 7787#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_SHIFT 0U 7788#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_WIDTH 4U 7789#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_3__REG DENALI_CTL_458 7790#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_3__FLD LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3 7791 7792#endif /* REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ */ 7793