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9#include <errno.h>
10
11#include "cps_drv_lpddr4.h"
12#include "lpddr4_if.h"
13#include "lpddr4.h"
14#include "lpddr4_structs_if.h"
15
16#ifndef LPDDR4_CUSTOM_TIMEOUT_DELAY
17#define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U
18#endif
19
20#ifndef LPDDR4_CPS_NS_DELAY_TIME
21#define LPDDR4_CPS_NS_DELAY_TIME 10000000U
22#endif
23
24static u32 lpddr4_pollphyindepirq(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt irqbit, u32 delay);
25static u32 lpddr4_pollandackirq(const lpddr4_privatedata *pd);
26static u32 lpddr4_startsequencecontroller(const lpddr4_privatedata *pd);
27static u32 lpddr4_writemmrregister(const lpddr4_privatedata *pd, u32 writemoderegval);
28static void lpddr4_checkcatrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
29static void lpddr4_checkgatelvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
30static void lpddr4_checkreadlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
31static void lpddr4_checkdqtrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
32static u8 lpddr4_seterror(volatile u32 *reg, u32 errbitmask, u8 *errfoundptr, const u32 errorinfobits);
33static void lpddr4_setphysnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
34static void lpddr4_setphyadrsnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
35static void readpdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
36static void readsrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
37static void readsrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
38static void readsrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
39static void readsrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
40static void readsrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
41static void readsrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
42static void lpddr4_readlpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles);
43static void writepdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
44static void writesrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
45static void writesrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
46static void writesrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
47static void writesrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
48static void writesrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
49static void writesrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
50static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
51static void lpddr4_updatefsp2refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
52static void lpddr4_updatefsp1refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
53static void lpddr4_updatefsp0refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
54#ifdef REG_WRITE_VERIF
55static u32 lpddr4_getphyrwmask(u32 regoffset);
56static u32 lpddr4_verifyregwrite(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
57#endif
58
59u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay)
60{
61 u32 result = 0U;
62 u32 timeout = 0U;
63 bool irqstatus = false;
64
65 do {
66 if (++timeout == delay) {
67 result = (u32)EIO;
68 break;
69 }
70 result = lpddr4_checkctlinterrupt(pd, irqbit, &irqstatus);
71 } while ((irqstatus == (bool)false) && (result == (u32)0));
72
73 return result;
74}
75
76static u32 lpddr4_pollphyindepirq(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt irqbit, u32 delay)
77{
78 u32 result = 0U;
79 u32 timeout = 0U;
80 bool irqstatus = false;
81
82 do {
83 if (++timeout == delay) {
84 result = (u32)EIO;
85 break;
86 }
87 result = lpddr4_checkphyindepinterrupt(pd, irqbit, &irqstatus);
88 } while ((irqstatus == (bool)false) && (result == (u32)0));
89
90 return result;
91}
92
93static u32 lpddr4_pollandackirq(const lpddr4_privatedata *pd)
94{
95 u32 result = 0U;
96
97 result = lpddr4_pollphyindepirq(pd, LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT, LPDDR4_CUSTOM_TIMEOUT_DELAY);
98
99 if (result == (u32)0)
100 result = lpddr4_ackphyindepinterrupt(pd, LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT);
101 if (result == (u32)0)
102 result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MC_INIT_DONE, LPDDR4_CUSTOM_TIMEOUT_DELAY);
103 if (result == (u32)0)
104 result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MC_INIT_DONE);
105 return result;
106}
107
108static u32 lpddr4_startsequencecontroller(const lpddr4_privatedata *pd)
109{
110 u32 result = 0U;
111 u32 regval = 0U;
112 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
113 lpddr4_infotype infotype;
114
115 regval = CPS_FLD_SET(LPDDR4__PI_START__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_START__REG)));
116 CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_START__REG)), regval);
117
118 regval = CPS_FLD_SET(LPDDR4__START__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__START__REG)));
119 CPS_REG_WRITE(&(ctlregbase->LPDDR4__START__REG), regval);
120
121 if (pd->infohandler != (lpddr4_infocallback)NULL) {
122 infotype = LPDDR4_DRV_SOC_PLL_UPDATE;
123 pd->infohandler(pd, infotype);
124 }
125
126 result = lpddr4_pollandackirq(pd);
127
128 return result;
129}
130
131volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset)
132{
133 volatile u32 *local_addr = addr;
134 volatile u32 *regaddr = &local_addr[regoffset];
135
136 return regaddr;
137}
138
139u32 lpddr4_probe(const lpddr4_config *config, u16 *configsize)
140{
141 u32 result;
142
143 result = (u32)(lpddr4_probesf(config, configsize));
144 if (result == (u32)0)
145 *configsize = (u16)(sizeof(lpddr4_privatedata));
146 return result;
147}
148
149u32 lpddr4_init(lpddr4_privatedata *pd, const lpddr4_config *cfg)
150{
151 u32 result = 0U;
152
153 result = lpddr4_initsf(pd, cfg);
154 if (result == (u32)0) {
155 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)cfg->ctlbase;
156 pd->ctlbase = ctlregbase;
157 pd->infohandler = (lpddr4_infocallback)cfg->infohandler;
158 pd->ctlinterrupthandler = (lpddr4_ctlcallback)cfg->ctlinterrupthandler;
159 pd->phyindepinterrupthandler = (lpddr4_phyindepcallback)cfg->phyindepinterrupthandler;
160 }
161 return result;
162}
163
164u32 lpddr4_start(const lpddr4_privatedata *pd)
165{
166 u32 result = 0U;
167
168 result = lpddr4_startsf(pd);
169 if (result == (u32)0) {
170 result = lpddr4_enablepiinitiator(pd);
171 result = lpddr4_startsequencecontroller(pd);
172 }
173 return result;
174}
175
176u32 lpddr4_readreg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue)
177{
178 u32 result = 0U;
179
180 result = lpddr4_readregsf(pd, cpp, regvalue);
181 if (result == (u32)0) {
182 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
183
184 if (cpp == LPDDR4_CTL_REGS) {
185 if (regoffset >= LPDDR4_INTR_CTL_REG_COUNT)
186 result = (u32)EINVAL;
187 else
188 *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_CTL_0), regoffset));
189 } else if (cpp == LPDDR4_PHY_REGS) {
190 if (regoffset >= LPDDR4_INTR_PHY_REG_COUNT)
191 result = (u32)EINVAL;
192 else
193 *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_PHY_0), regoffset));
194
195 } else {
196 if (regoffset >= LPDDR4_INTR_PHY_INDEP_REG_COUNT)
197 result = (u32)EINVAL;
198 else
199 *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset));
200 }
201 }
202 return result;
203}
204
205#ifdef REG_WRITE_VERIF
206
207static u32 lpddr4_getphyrwmask(u32 regoffset)
208{
209 u32 rwmask = 0U;
210 u32 arrayoffset = 0U;
211 u32 slicenum, sliceoffset = 0U;
212
213 for (slicenum = (u32)0U; slicenum <= (DSLICE_NUM + ASLICE_NUM); slicenum++) {
214 sliceoffset = sliceoffset + (u32)SLICE_WIDTH;
215 if (regoffset < sliceoffset)
216 break;
217 }
218 arrayoffset = regoffset - (sliceoffset - (u32)SLICE_WIDTH);
219
220 if (slicenum < DSLICE_NUM) {
221 rwmask = lpddr4_getdslicemask(slicenum, arrayoffset);
222 } else {
223 if (slicenum == DSLICE_NUM) {
224 if (arrayoffset < ASLICE0_REG_COUNT)
225 rwmask = g_lpddr4_address_slice_0_rw_mask[arrayoffset];
226 } else {
227 if (arrayoffset < PHY_CORE_REG_COUNT)
228 rwmask = g_lpddr4_phy_core_rw_mask[arrayoffset];
229 }
230 }
231 return rwmask;
232}
233
234static u32 lpddr4_verifyregwrite(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue)
235{
236 u32 result = (u32)0;
237 u32 regreadval = 0U;
238 u32 rwmask = 0U;
239
240 result = lpddr4_readreg(pd, cpp, regoffset, ®readval);
241
242 if (result == (u32)0) {
243 switch (cpp) {
244 case LPDDR4_PHY_INDEP_REGS:
245 rwmask = g_lpddr4_pi_rw_mask[regoffset];
246 break;
247 case LPDDR4_PHY_REGS:
248 rwmask = lpddr4_getphyrwmask(regoffset);
249 break;
250 default:
251 rwmask = g_lpddr4_ddr_controller_rw_mask[regoffset];
252 break;
253 }
254
255 if ((rwmask & regreadval) != (regvalue & rwmask))
256 result = EIO;
257 }
258 return result;
259}
260#endif
261
262u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue)
263{
264 u32 result = 0U;
265
266 result = lpddr4_writeregsf(pd, cpp);
267 if (result == (u32)0) {
268 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
269
270 if (cpp == LPDDR4_CTL_REGS) {
271 if (regoffset >= LPDDR4_INTR_CTL_REG_COUNT)
272 result = (u32)EINVAL;
273 else
274 CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_CTL_0), regoffset), regvalue);
275 } else if (cpp == LPDDR4_PHY_REGS) {
276 if (regoffset >= LPDDR4_INTR_PHY_REG_COUNT)
277 result = (u32)EINVAL;
278 else
279 CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_PHY_0), regoffset), regvalue);
280 } else {
281 if (regoffset >= LPDDR4_INTR_PHY_INDEP_REG_COUNT)
282 result = (u32)EINVAL;
283 else
284 CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset), regvalue);
285 }
286 }
287#ifdef REG_WRITE_VERIF
288 if (result == (u32)0)
289 result = lpddr4_verifyregwrite(pd, cpp, regoffset, regvalue);
290
291#endif
292
293 return result;
294}
295
296u32 lpddr4_getmmrregister(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus)
297{
298 u32 result = 0U;
299 u32 tdelay = 1000U;
300 u32 regval = 0U;
301
302 result = lpddr4_getmmrregistersf(pd, mmrvalue, mmrstatus);
303 if (result == (u32)0) {
304 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
305
306 regval = CPS_FLD_WRITE(LPDDR4__READ_MODEREG__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__READ_MODEREG__REG)), readmoderegval);
307 CPS_REG_WRITE(&(ctlregbase->LPDDR4__READ_MODEREG__REG), regval);
308
309 result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MR_READ_DONE, tdelay);
310 }
311 if (result == (u32)0)
312 result = lpddr4_checkmmrreaderror(pd, mmrvalue, mmrstatus);
313 return result;
314}
315
316static u32 lpddr4_writemmrregister(const lpddr4_privatedata *pd, u32 writemoderegval)
317{
318 u32 result = (u32)0;
319 u32 tdelay = 1000U;
320 u32 regval = 0U;
321 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
322
323 regval = CPS_FLD_WRITE(LPDDR4__WRITE_MODEREG__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WRITE_MODEREG__REG)), writemoderegval);
324 CPS_REG_WRITE(&(ctlregbase->LPDDR4__WRITE_MODEREG__REG), regval);
325
326 result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MR_WRITE_DONE, tdelay);
327
328 return result;
329}
330
331u32 lpddr4_setmmrregister(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus)
332{
333 u32 result = 0U;
334
335 result = lpddr4_setmmrregistersf(pd, mrwstatus);
336 if (result == (u32)0) {
337 result = lpddr4_writemmrregister(pd, writemoderegval);
338
339 if (result == (u32)0)
340 result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_WRITE_DONE);
341 if (result == (u32)0) {
342 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
343 *mrwstatus = (u8)CPS_FLD_READ(LPDDR4__MRW_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRW_STATUS__REG)));
344 if ((*mrwstatus) != 0U)
345 result = (u32)EIO;
346 }
347 }
348
349#ifdef ASILC
350#endif
351
352 return result;
353}
354
355u32 lpddr4_writectlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
356{
357 u32 result;
358 u32 aindex;
359
360 result = lpddr4_writectlconfigsf(pd);
361 if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
362 result = EINVAL;
363
364 if (result == (u32)0) {
365 for (aindex = 0; aindex < regcount; aindex++)
366 result = (u32)lpddr4_writereg(pd, LPDDR4_CTL_REGS, (u32)regnum[aindex],
367 (u32)regvalues[aindex]);
368 }
369 return result;
370}
371
372u32 lpddr4_writephyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
373{
374 u32 result;
375 u32 aindex;
376
377 result = lpddr4_writephyindepconfigsf(pd);
378 if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
379 result = EINVAL;
380 if (result == (u32)0) {
381 for (aindex = 0; aindex < regcount; aindex++)
382 result = (u32)lpddr4_writereg(pd, LPDDR4_PHY_INDEP_REGS, (u32)regnum[aindex],
383 (u32)regvalues[aindex]);
384 }
385 return result;
386}
387
388u32 lpddr4_writephyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
389{
390 u32 result;
391 u32 aindex;
392
393 result = lpddr4_writephyconfigsf(pd);
394 if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
395 result = EINVAL;
396 if (result == (u32)0) {
397 for (aindex = 0; aindex < regcount; aindex++)
398 result = (u32)lpddr4_writereg(pd, LPDDR4_PHY_REGS, (u32)regnum[aindex],
399 (u32)regvalues[aindex]);
400 }
401 return result;
402}
403
404u32 lpddr4_readctlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
405{
406 u32 result;
407 u32 aindex;
408
409 result = lpddr4_readctlconfigsf(pd);
410 if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
411 result = EINVAL;
412 if (result == (u32)0) {
413 for (aindex = 0; aindex < regcount; aindex++)
414 result = (u32)lpddr4_readreg(pd, LPDDR4_CTL_REGS, (u32)regnum[aindex],
415 (u32 *)(®values[aindex]));
416 }
417 return result;
418}
419
420u32 lpddr4_readphyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
421{
422 u32 result;
423 u32 aindex;
424
425 result = lpddr4_readphyindepconfigsf(pd);
426 if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
427 result = EINVAL;
428 if (result == (u32)0) {
429 for (aindex = 0; aindex < regcount; aindex++)
430 result = (u32)lpddr4_readreg(pd, LPDDR4_PHY_INDEP_REGS, (u32)regnum[aindex],
431 (u32 *)(®values[aindex]));
432 }
433 return result;
434}
435
436u32 lpddr4_readphyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
437{
438 u32 result;
439 u32 aindex;
440
441 result = lpddr4_readphyconfigsf(pd);
442 if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
443 result = EINVAL;
444 if (result == (u32)0) {
445 for (aindex = 0; aindex < regcount; aindex++)
446 result = (u32)lpddr4_readreg(pd, LPDDR4_PHY_REGS, (u32)regnum[aindex],
447 (u32 *)(®values[aindex]));
448 }
449 return result;
450}
451
452u32 lpddr4_getphyindepinterruptmask(const lpddr4_privatedata *pd, u32 *mask)
453{
454 u32 result;
455
456 result = lpddr4_getphyindepinterruptmsf(pd, mask);
457 if (result == (u32)0) {
458 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
459 *mask = CPS_FLD_READ(LPDDR4__PI_INT_MASK__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_MASK__REG)));
460 }
461 return result;
462}
463
464u32 lpddr4_setphyindepinterruptmask(const lpddr4_privatedata *pd, const u32 *mask)
465{
466 u32 result;
467 u32 regval = 0;
468 const u32 ui32irqcount = (u32)LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT + 1U;
469
470 result = lpddr4_setphyindepinterruptmsf(pd, mask);
471 if ((result == (u32)0) && (ui32irqcount < WORD_SHIFT)) {
472 if (*mask >= (1U << ui32irqcount))
473 result = (u32)EINVAL;
474 }
475 if (result == (u32)0) {
476 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
477
478 regval = CPS_FLD_WRITE(LPDDR4__PI_INT_MASK__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_MASK__REG)), *mask);
479 CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_MASK__REG), regval);
480 }
481 return result;
482}
483
484u32 lpddr4_checkphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus)
485{
486 u32 result = 0;
487 u32 phyindepirqstatus = 0;
488
489 result = LPDDR4_INTR_CheckPhyIndepIntSF(pd, intr, irqstatus);
490 if ((result == (u32)0) && ((u32)intr < WORD_SHIFT)) {
491 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
492
493 phyindepirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_STATUS__REG));
494 *irqstatus = (bool)(((phyindepirqstatus >> (u32)intr) & LPDDR4_BIT_MASK) > 0U);
495 }
496 return result;
497}
498
499u32 lpddr4_ackphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr)
500{
501 u32 result = 0U;
502 u32 regval = 0U;
503
504 result = LPDDR4_INTR_AckPhyIndepIntSF(pd, intr);
505 if ((result == (u32)0) && ((u32)intr < WORD_SHIFT)) {
506 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
507
508 regval = ((u32)LPDDR4_BIT_MASK << (u32)intr);
509 CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_ACK__REG), regval);
510 }
511
512 return result;
513}
514
515static void lpddr4_checkcatrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
516{
517 u32 regval;
518 u32 errbitmask = 0U;
519 u32 snum;
520 volatile u32 *regaddress;
521
522 regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_ADR_CALVL_OBS1_0__REG));
523 errbitmask = (CA_TRAIN_RL) | (NIBBLE_MASK);
524 for (snum = 0U; snum < ASLICE_NUM; snum++) {
525 regval = CPS_REG_READ(regaddress);
526 if ((regval & errbitmask) != CA_TRAIN_RL) {
527 debuginfo->catraingerror = CDN_TRUE;
528 *errfoundptr = true;
529 }
530 regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
531 }
532}
533
534static void lpddr4_checkgatelvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
535{
536 u32 regval;
537 u32 errbitmask = 0U;
538 u32 snum;
539 volatile u32 *regaddress;
540
541 regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG));
542 errbitmask = GATE_LVL_ERROR_FIELDS;
543 for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
544 regval = CPS_REG_READ(regaddress);
545 if ((regval & errbitmask) != 0U) {
546 debuginfo->gatelvlerror = CDN_TRUE;
547 *errfoundptr = true;
548 }
549 regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
550 }
551}
552
553static void lpddr4_checkreadlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
554{
555 u32 regval;
556 u32 errbitmask = 0U;
557 u32 snum;
558 volatile u32 *regaddress;
559
560 regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG));
561 errbitmask = READ_LVL_ERROR_FIELDS;
562 for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
563 regval = CPS_REG_READ(regaddress);
564 if ((regval & errbitmask) != 0U) {
565 debuginfo->readlvlerror = CDN_TRUE;
566 *errfoundptr = true;
567 }
568 regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
569 }
570}
571
572static void lpddr4_checkdqtrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
573{
574 u32 regval;
575 u32 errbitmask = 0U;
576 u32 snum;
577 volatile u32 *regaddress;
578
579 regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG));
580 errbitmask = DQ_LVL_STATUS;
581 for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
582 regval = CPS_REG_READ(regaddress);
583 if ((regval & errbitmask) != 0U) {
584 debuginfo->dqtrainingerror = CDN_TRUE;
585 *errfoundptr = true;
586 }
587 regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
588 }
589}
590
591bool lpddr4_checklvlerrors(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo, bool errfound)
592{
593 bool localerrfound = errfound;
594
595 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
596
597 if (localerrfound == (bool)false)
598 lpddr4_checkcatrainingerror(ctlregbase, debuginfo, &localerrfound);
599
600 if (localerrfound == (bool)false)
601 lpddr4_checkwrlvlerror(ctlregbase, debuginfo, &localerrfound);
602
603 if (localerrfound == (bool)false)
604 lpddr4_checkgatelvlerror(ctlregbase, debuginfo, &localerrfound);
605
606 if (localerrfound == (bool)false)
607 lpddr4_checkreadlvlerror(ctlregbase, debuginfo, &localerrfound);
608
609 if (localerrfound == (bool)false)
610 lpddr4_checkdqtrainingerror(ctlregbase, debuginfo, &localerrfound);
611 return localerrfound;
612}
613
614static u8 lpddr4_seterror(volatile u32 *reg, u32 errbitmask, u8 *errfoundptr, const u32 errorinfobits)
615{
616 u32 regval = 0U;
617
618 regval = CPS_REG_READ(reg);
619 if ((regval & errbitmask) != errorinfobits)
620 *errfoundptr = CDN_TRUE;
621 return *errfoundptr;
622}
623
624void lpddr4_seterrors(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, u8 *errfoundptr)
625{
626 u32 errbitmask = (LPDDR4_BIT_MASK << 0x1U) | (LPDDR4_BIT_MASK);
627
628 debuginfo->pllerror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_0__REG),
629 errbitmask, errfoundptr, PLL_READY);
630 if (*errfoundptr == CDN_FALSE)
631 debuginfo->pllerror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_1__REG),
632 errbitmask, errfoundptr, PLL_READY);
633
634 if (*errfoundptr == CDN_FALSE)
635 debuginfo->iocaliberror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_CAL_RESULT_OBS_0__REG),
636 IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
637 if (*errfoundptr == CDN_FALSE)
638 debuginfo->iocaliberror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_CAL_RESULT2_OBS_0__REG),
639 IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
640 if (*errfoundptr == CDN_FALSE)
641 debuginfo->iocaliberror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_CAL_RESULT3_OBS_0__REG),
642 IO_CALIB_FIELD, errfoundptr, IO_CALIB_STATE);
643}
644
645static void lpddr4_setphysnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound)
646{
647 u32 snum = 0U;
648 volatile u32 *regaddress;
649 u32 regval = 0U;
650
651 if (errorfound == (bool)false) {
652 regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG));
653 for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
654 regval = CPS_FLD_SET(LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD, CPS_REG_READ(regaddress));
655 CPS_REG_WRITE(regaddress, regval);
656 regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
657 }
658 }
659}
660
661static void lpddr4_setphyadrsnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound)
662{
663 u32 snum = 0U;
664 volatile u32 *regaddress;
665 u32 regval = 0U;
666
667 if (errorfound == (bool)false) {
668 regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG));
669 for (snum = (u32)0U; snum < ASLICE_NUM; snum++) {
670 regval = CPS_FLD_SET(LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD, CPS_REG_READ(regaddress));
671 CPS_REG_WRITE(regaddress, regval);
672 regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
673 }
674 }
675}
676
677void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound)
678{
679 lpddr4_setphysnapsettings(ctlregbase, errorfound);
680 lpddr4_setphyadrsnapsettings(ctlregbase, errorfound);
681}
682
683static void readpdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
684{
685 if (*fspnum == LPDDR4_FSP_0)
686 *cycles = CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG)));
687 else if (*fspnum == LPDDR4_FSP_1)
688 *cycles = CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG)));
689 else
690 *cycles = CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG)));
691}
692
693static void readsrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
694{
695 if (*fspnum == LPDDR4_FSP_0)
696 *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)));
697 else if (*fspnum == LPDDR4_FSP_1)
698 *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)));
699 else
700 *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)));
701}
702
703static void readsrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
704{
705 if (*fspnum == LPDDR4_FSP_0)
706 *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)));
707 else if (*fspnum == LPDDR4_FSP_1)
708 *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)));
709 else
710 *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)));
711}
712
713static void readsrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
714{
715 if (*fspnum == LPDDR4_FSP_0)
716 *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
717 else if (*fspnum == LPDDR4_FSP_1)
718 *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
719 else
720 *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
721}
722
723static void readsrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
724{
725 if (*fspnum == LPDDR4_FSP_0)
726 *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)));
727 else if (*fspnum == LPDDR4_FSP_1)
728 *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)));
729 else
730 *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)));
731}
732
733static void readsrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
734{
735 if (*fspnum == LPDDR4_FSP_0)
736 *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)));
737 else if (*fspnum == LPDDR4_FSP_1)
738 *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)));
739 else
740 *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)));
741}
742
743static void readsrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
744{
745 if (*fspnum == LPDDR4_FSP_0)
746 *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
747 else if (*fspnum == LPDDR4_FSP_1)
748 *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
749 else
750 *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
751
752}
753
754static void lpddr4_readlpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles)
755{
756 if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN)
757 readpdwakeup(fspnum, ctlregbase, cycles);
758 else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN)
759 readsrshortwakeup(fspnum, ctlregbase, cycles);
760 else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN)
761 readsrlongwakeup(fspnum, ctlregbase, cycles);
762 else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN)
763 readsrlonggatewakeup(fspnum, ctlregbase, cycles);
764 else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN)
765 readsrdpshortwakeup(fspnum, ctlregbase, cycles);
766 else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN)
767 readsrdplongwakeup(fspnum, ctlregbase, cycles);
768 else
769 readsrdplonggatewakeup(fspnum, ctlregbase, cycles);
770}
771
772u32 lpddr4_getlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles)
773{
774 u32 result = 0U;
775
776 result = lpddr4_getlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles);
777 if (result == (u32)0) {
778 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
779 lpddr4_readlpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum, cycles);
780 }
781 return result;
782}
783
784static void writepdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
785{
786 u32 regval = 0U;
787
788 if (*fspnum == LPDDR4_FSP_0) {
789 regval = CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG)), *cycles);
790 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG), regval);
791 } else if (*fspnum == LPDDR4_FSP_1) {
792 regval = CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG)), *cycles);
793 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG), regval);
794 } else {
795 regval = CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG)), *cycles);
796 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG), regval);
797 }
798}
799
800static void writesrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
801{
802 u32 regval = 0U;
803
804 if (*fspnum == LPDDR4_FSP_0) {
805 regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)), *cycles);
806 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG), regval);
807 } else if (*fspnum == LPDDR4_FSP_1) {
808 regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)), *cycles);
809 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG), regval);
810 } else {
811 regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)), *cycles);
812 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG), regval);
813 }
814}
815
816static void writesrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
817{
818 u32 regval = 0U;
819
820 if (*fspnum == LPDDR4_FSP_0) {
821 regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)), *cycles);
822 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG), regval);
823 } else if (*fspnum == LPDDR4_FSP_1) {
824 regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)), *cycles);
825 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG), regval);
826 } else {
827 regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)), *cycles);
828 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG), regval);
829 }
830}
831
832static void writesrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
833{
834 u32 regval = 0U;
835
836 if (*fspnum == LPDDR4_FSP_0) {
837 regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)), *cycles);
838 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG), regval);
839 } else if (*fspnum == LPDDR4_FSP_1) {
840 regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)), *cycles);
841 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG), regval);
842 } else {
843 regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)), *cycles);
844 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG), regval);
845 }
846}
847
848static void writesrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
849{
850 u32 regval = 0U;
851
852 if (*fspnum == LPDDR4_FSP_0) {
853 regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)), *cycles);
854 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG), regval);
855 } else if (*fspnum == LPDDR4_FSP_1) {
856 regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)), *cycles);
857 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG), regval);
858 } else {
859 regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)), *cycles);
860 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG), regval);
861 }
862}
863
864static void writesrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
865{
866 u32 regval = 0U;
867
868 if (*fspnum == LPDDR4_FSP_0) {
869 regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)), *cycles);
870 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG), regval);
871 } else if (*fspnum == LPDDR4_FSP_1) {
872 regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)), *cycles);
873 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG), regval);
874 } else {
875 regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)), *cycles);
876 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG), regval);
877 }
878}
879static void writesrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
880{
881 u32 regval = 0U;
882
883 if (*fspnum == LPDDR4_FSP_0) {
884 regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)), *cycles);
885 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG), regval);
886 } else if (*fspnum == LPDDR4_FSP_1) {
887 regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)), *cycles);
888 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG), regval);
889 } else {
890 regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)), *cycles);
891 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG), regval);
892 }
893}
894
895static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles)
896{
897 if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN)
898 writepdwakeup(fspnum, ctlregbase, cycles);
899 else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN)
900 writesrshortwakeup(fspnum, ctlregbase, cycles);
901 else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN)
902 writesrlongwakeup(fspnum, ctlregbase, cycles);
903 else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN)
904 writesrlonggatewakeup(fspnum, ctlregbase, cycles);
905 else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN)
906 writesrdpshortwakeup(fspnum, ctlregbase, cycles);
907 else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN)
908 writesrdplongwakeup(fspnum, ctlregbase, cycles);
909 else
910 writesrdplonggatewakeup(fspnum, ctlregbase, cycles);
911}
912
913u32 lpddr4_setlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles)
914{
915 u32 result = 0U;
916
917 result = lpddr4_setlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles);
918 if (result == (u32)0) {
919 if (*cycles > NIBBLE_MASK)
920 result = (u32)EINVAL;
921 }
922 if (result == (u32)0) {
923 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
924 lpddr4_writelpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum, cycles);
925 }
926 return result;
927}
928
929u32 lpddr4_getdbireadmode(const lpddr4_privatedata *pd, bool *on_off)
930{
931 u32 result = 0U;
932
933 result = lpddr4_getdbireadmodesf(pd, on_off);
934
935 if (result == (u32)0) {
936 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
937 if (CPS_FLD_READ(LPDDR4__RD_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG))) == 0U)
938 *on_off = false;
939 else
940 *on_off = true;
941 }
942 return result;
943}
944
945u32 lpddr4_getdbiwritemode(const lpddr4_privatedata *pd, bool *on_off)
946{
947 u32 result = 0U;
948
949 result = lpddr4_getdbireadmodesf(pd, on_off);
950
951 if (result == (u32)0) {
952 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
953 if (CPS_FLD_READ(LPDDR4__WR_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG))) == 0U)
954 *on_off = false;
955 else
956 *on_off = true;
957 }
958 return result;
959}
960
961u32 lpddr4_setdbimode(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode)
962{
963 u32 result = 0U;
964 u32 regval = 0U;
965
966 result = lpddr4_setdbimodesf(pd, mode);
967
968 if (result == (u32)0) {
969 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
970
971 if (*mode == LPDDR4_DBI_RD_ON)
972 regval = CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG)), 1U);
973 else if (*mode == LPDDR4_DBI_RD_OFF)
974 regval = CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG)), 0U);
975 else if (*mode == LPDDR4_DBI_WR_ON)
976 regval = CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG)), 1U);
977 else
978 regval = CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG)), 0U);
979 CPS_REG_WRITE(&(ctlregbase->LPDDR4__RD_DBI_EN__REG), regval);
980 }
981 return result;
982}
983
984u32 lpddr4_getrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max)
985{
986 u32 result = 0U;
987
988 result = lpddr4_getrefreshratesf(pd, fspnum, tref, tras_max);
989
990 if (result == (u32)0) {
991 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
992
993 switch (*fspnum) {
994 case LPDDR4_FSP_2:
995 *tref = CPS_FLD_READ(LPDDR4__TREF_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F2__REG)));
996 *tras_max = CPS_FLD_READ(LPDDR4__TRAS_MAX_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F2__REG)));
997 break;
998 case LPDDR4_FSP_1:
999 *tref = CPS_FLD_READ(LPDDR4__TREF_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F1__REG)));
1000 *tras_max = CPS_FLD_READ(LPDDR4__TRAS_MAX_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F1__REG)));
1001 break;
1002 default:
1003 *tref = CPS_FLD_READ(LPDDR4__TREF_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F0__REG)));
1004 *tras_max = CPS_FLD_READ(LPDDR4__TRAS_MAX_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F0__REG)));
1005 break;
1006 }
1007 }
1008 return result;
1009}
1010
1011static void lpddr4_updatefsp2refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max)
1012{
1013 u32 regval = 0U;
1014 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
1015
1016 regval = CPS_FLD_WRITE(LPDDR4__TREF_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F2__REG)), *tref);
1017 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F2__REG), regval);
1018 regval = CPS_FLD_WRITE(LPDDR4__TRAS_MAX_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F2__REG)), *tras_max);
1019 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TRAS_MAX_F2__REG), regval);
1020}
1021
1022static void lpddr4_updatefsp1refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max)
1023{
1024 u32 regval = 0U;
1025 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
1026
1027 regval = CPS_FLD_WRITE(LPDDR4__TREF_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F1__REG)), *tref);
1028 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F1__REG), regval);
1029 regval = CPS_FLD_WRITE(LPDDR4__TRAS_MAX_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F1__REG)), *tras_max);
1030 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TRAS_MAX_F1__REG), regval);;
1031}
1032
1033static void lpddr4_updatefsp0refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max)
1034{
1035 u32 regval = 0U;
1036 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
1037
1038 regval = CPS_FLD_WRITE(LPDDR4__TREF_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F0__REG)), *tref);
1039 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F0__REG), regval);
1040 regval = CPS_FLD_WRITE(LPDDR4__TRAS_MAX_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F0__REG)), *tras_max);
1041 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TRAS_MAX_F0__REG), regval);
1042}
1043
1044u32 lpddr4_setrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
1045{
1046 u32 result = 0U;
1047
1048 result = lpddr4_setrefreshratesf(pd, fspnum, tref, tras_max);
1049
1050 if (result == (u32)0) {
1051 switch (*fspnum) {
1052 case LPDDR4_FSP_2:
1053 lpddr4_updatefsp2refrateparams(pd, tref, tras_max);
1054 break;
1055 case LPDDR4_FSP_1:
1056 lpddr4_updatefsp1refrateparams(pd, tref, tras_max);
1057 break;
1058 default:
1059 lpddr4_updatefsp0refrateparams(pd, tref, tras_max);
1060 break;
1061 }
1062 }
1063 return result;
1064}
1065
1066u32 lpddr4_refreshperchipselect(const lpddr4_privatedata *pd, const u32 trefinterval)
1067{
1068 u32 result = 0U;
1069 u32 regval = 0U;
1070
1071 result = lpddr4_refreshperchipselectsf(pd);
1072
1073 if (result == (u32)0) {
1074 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
1075 regval = CPS_FLD_WRITE(LPDDR4__TREF_INTERVAL__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG)), trefinterval);
1076 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG), regval);
1077 }
1078 return result;
1079}
1080
