LXR uboot/drivers/serial/lpc32xx

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
   4 */
   5
   6#include <common.h>
   7#include <clock_legacy.h>
   8#include <dm.h>
   9#include <serial.h>
  10#include <dm/platform_data/lpc32xx_hsuart.h>
  11
  12#include <asm/arch/uart.h>
  13#include <linux/compiler.h>
  14
  15struct lpc32xx_hsuart_priv {
  16        struct hsuart_regs *hsuart;
  17};
  18
  19static int lpc32xx_serial_setbrg(struct udevice *dev, int baudrate)
  20{
  21        struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
  22        struct hsuart_regs *hsuart = priv->hsuart;
  23        u32 div;
  24
  25        /* UART rate = PERIPH_CLK / ((HSU_RATE + 1) x 14) */
  26        div = (get_serial_clock() / 14 + baudrate / 2) / baudrate - 1;
  27        if (div > 255)
  28                div = 255;
  29
  30        writel(div, &hsuart->rate);
  31
  32        return 0;
  33}
  34
  35static int lpc32xx_serial_getc(struct udevice *dev)
  36{
  37        struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
  38        struct hsuart_regs *hsuart = priv->hsuart;
  39
  40        if (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
  41                return -EAGAIN;
  42
  43        return readl(&hsuart->rx) & HSUART_RX_DATA;
  44}
  45
  46static int lpc32xx_serial_putc(struct udevice *dev, const char c)
  47{
  48        struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
  49        struct hsuart_regs *hsuart = priv->hsuart;
  50
  51        /* Wait for empty FIFO */
  52        if (readl(&hsuart->level) & HSUART_LEVEL_TX)
  53                return -EAGAIN;
  54
  55        writel(c, &hsuart->tx);
  56
  57        return 0;
  58}
  59
  60static int lpc32xx_serial_pending(struct udevice *dev, bool input)
  61{
  62        struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
  63        struct hsuart_regs *hsuart = priv->hsuart;
  64
  65        if (input) {
  66                if (readl(&hsuart->level) & HSUART_LEVEL_RX)
  67                        return 1;
  68        } else {
  69                if (readl(&hsuart->level) & HSUART_LEVEL_TX)
  70                        return 1;
  71        }
  72
  73        return 0;
  74}
  75
  76static int lpc32xx_serial_init(struct hsuart_regs *hsuart)
  77{
  78        /* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */
  79        writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) |
  80               HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0,
  81               &hsuart->ctrl);
  82
  83        return 0;
  84}
  85
  86static int lpc32xx_hsuart_probe(struct udevice *dev)
  87{
  88        struct lpc32xx_hsuart_plat *plat = dev_get_plat(dev);
  89        struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev);
  90
  91        priv->hsuart = (struct hsuart_regs *)plat->base;
  92
  93        lpc32xx_serial_init(priv->hsuart);
  94
  95        return 0;
  96}
  97
  98static const struct dm_serial_ops lpc32xx_hsuart_ops = {
  99        .setbrg = lpc32xx_serial_setbrg,
 100        .getc   = lpc32xx_serial_getc,
 101        .putc   = lpc32xx_serial_putc,
 102        .pending = lpc32xx_serial_pending,
 103};
 104
 105U_BOOT_DRIVER(lpc32xx_hsuart) = {
 106        .name   = "lpc32xx_hsuart",
 107        .id     = UCLASS_SERIAL,
 108        .probe  = lpc32xx_hsuart_probe,
 109        .ops    = &lpc32xx_hsuart_ops,
 110        .priv_auto      = sizeof(struct lpc32xx_hsuart_priv),
 111        .flags  = DM_FLAG_PRE_RELOC,
 112};
 113