LXR uboot/drivers/serial/serial

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
   4 * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
   5 */
   6
   7#include <clk.h>
   8#include <common.h>
   9#include <debug_uart.h>
  10#include <dm.h>
  11#include <errno.h>
  12#include <fdtdec.h>
  13#include <log.h>
  14#include <watchdog.h>
  15#include <asm/io.h>
  16#include <dm/device_compat.h>
  17#include <linux/bitops.h>
  18#include <linux/compiler.h>
  19#include <serial.h>
  20#include <linux/err.h>
  21
  22#define ZYNQ_UART_SR_TXACTIVE   BIT(11) /* TX active */
  23#define ZYNQ_UART_SR_TXFULL     BIT(4) /* TX FIFO full */
  24#define ZYNQ_UART_SR_RXEMPTY    BIT(1) /* RX FIFO empty */
  25
  26#define ZYNQ_UART_CR_TX_EN      BIT(4) /* TX enabled */
  27#define ZYNQ_UART_CR_RX_EN      BIT(2) /* RX enabled */
  28#define ZYNQ_UART_CR_TXRST      BIT(1) /* TX logic reset */
  29#define ZYNQ_UART_CR_RXRST      BIT(0) /* RX logic reset */
  30
  31#define ZYNQ_UART_MR_STOPMODE_2_BIT     0x00000080  /* 2 stop bits */
  32#define ZYNQ_UART_MR_STOPMODE_1_5_BIT   0x00000040  /* 1.5 stop bits */
  33#define ZYNQ_UART_MR_STOPMODE_1_BIT     0x00000000  /* 1 stop bit */
  34
  35#define ZYNQ_UART_MR_PARITY_NONE        0x00000020  /* No parity mode */
  36#define ZYNQ_UART_MR_PARITY_ODD         0x00000008  /* Odd parity mode */
  37#define ZYNQ_UART_MR_PARITY_EVEN        0x00000000  /* Even parity mode */
  38
  39#define ZYNQ_UART_MR_CHARLEN_6_BIT      0x00000006  /* 6 bits data */
  40#define ZYNQ_UART_MR_CHARLEN_7_BIT      0x00000004  /* 7 bits data */
  41#define ZYNQ_UART_MR_CHARLEN_8_BIT      0x00000000  /* 8 bits data */
  42
  43struct uart_zynq {
  44        u32 control; /* 0x0 - Control Register [8:0] */
  45        u32 mode; /* 0x4 - Mode Register [10:0] */
  46        u32 reserved1[4];
  47        u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
  48        u32 reserved2[4];
  49        u32 channel_sts; /* 0x2c - Channel Status [11:0] */
  50        u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
  51        u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
  52};
  53
  54struct zynq_uart_plat {
  55        struct uart_zynq *regs;
  56};
  57
  58/* Set up the baud rate */
  59static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
  60                                     unsigned long clock, unsigned long baud)
  61{
  62        /* Calculation results. */
  63        unsigned int calc_bauderror, bdiv, bgen;
  64        unsigned long calc_baud = 0;
  65
  66        /* Covering case where input clock is so slow */
  67        if (clock < 1000000 && baud > 4800)
  68                baud = 4800;
  69
  70        /*                master clock
  71         * Baud rate = ------------------
  72         *              bgen * (bdiv + 1)
  73         *
  74         * Find acceptable values for baud generation.
  75         */
  76        for (bdiv = 4; bdiv < 255; bdiv++) {
  77                bgen = clock / (baud * (bdiv + 1));
  78                if (bgen < 2 || bgen > 65535)
  79                        continue;
  80
  81                calc_baud = clock / (bgen * (bdiv + 1));
  82
  83                /*
  84                 * Use first calculated baudrate with
  85                 * an acceptable (<3%) error
  86                 */
  87                if (baud > calc_baud)
  88                        calc_bauderror = baud - calc_baud;
  89                else
  90                        calc_bauderror = calc_baud - baud;
  91                if (((calc_bauderror * 100) / baud) < 3)
  92                        break;
  93        }
  94
  95        writel(bdiv, &regs->baud_rate_divider);
  96        writel(bgen, &regs->baud_rate_gen);
  97}
  98
  99/* Initialize the UART, with...some settings. */
 100static void _uart_zynq_serial_init(struct uart_zynq *regs)
 101{
 102        /* RX/TX enabled & reset */
 103        writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
 104                                        ZYNQ_UART_CR_RXRST, &regs->control);
 105        writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */
 106}
 107
 108static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
 109{
 110        if (readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL)
 111                return -EAGAIN;
 112
 113        writel(c, &regs->tx_rx_fifo);
 114
 115        return 0;
 116}
 117
 118static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
 119{
 120        struct zynq_uart_plat *plat = dev_get_plat(dev);
 121        unsigned long clock;
 122
 123        int ret;
 124        struct clk clk;
 125
 126        ret = clk_get_by_index(dev, 0, &clk);
 127        if (ret < 0) {
 128                dev_err(dev, "failed to get clock\n");
 129                return ret;
 130        }
 131
 132        clock = clk_get_rate(&clk);
 133        if (IS_ERR_VALUE(clock)) {
 134                dev_err(dev, "failed to get rate\n");
 135                return clock;
 136        }
 137        debug("%s: CLK %ld\n", __func__, clock);
 138
 139        ret = clk_enable(&clk);
 140        if (ret) {
 141                dev_err(dev, "failed to enable clock\n");
 142                return ret;
 143        }
 144
 145        _uart_zynq_serial_setbrg(plat->regs, clock, baudrate);
 146
 147        return 0;
 148}
 149
 150#if !defined(CONFIG_SPL_BUILD)
 151static int zynq_serial_setconfig(struct udevice *dev, uint serial_config)
 152{
 153        struct zynq_uart_plat *plat = dev_get_plat(dev);
 154        struct uart_zynq *regs = plat->regs;
 155        u32 val = 0;
 156
 157        switch (SERIAL_GET_BITS(serial_config)) {
 158        case SERIAL_6_BITS:
 159                val |= ZYNQ_UART_MR_CHARLEN_6_BIT;
 160                break;
 161        case SERIAL_7_BITS:
 162                val |= ZYNQ_UART_MR_CHARLEN_7_BIT;
 163                break;
 164        case SERIAL_8_BITS:
 165                val |= ZYNQ_UART_MR_CHARLEN_8_BIT;
 166                break;
 167        default:
 168                return -ENOTSUPP; /* not supported in driver */
 169        }
 170
 171        switch (SERIAL_GET_STOP(serial_config)) {
 172        case SERIAL_ONE_STOP:
 173                val |= ZYNQ_UART_MR_STOPMODE_1_BIT;
 174                break;
 175        case SERIAL_ONE_HALF_STOP:
 176                val |= ZYNQ_UART_MR_STOPMODE_1_5_BIT;
 177                break;
 178        case SERIAL_TWO_STOP:
 179                val |= ZYNQ_UART_MR_STOPMODE_2_BIT;
 180                break;
 181        default:
 182                return -ENOTSUPP; /* not supported in driver */
 183        }
 184
 185        switch (SERIAL_GET_PARITY(serial_config)) {
 186        case SERIAL_PAR_NONE:
 187                val |= ZYNQ_UART_MR_PARITY_NONE;
 188                break;
 189        case SERIAL_PAR_ODD:
 190                val |= ZYNQ_UART_MR_PARITY_ODD;
 191                break;
 192        case SERIAL_PAR_EVEN:
 193                val |= ZYNQ_UART_MR_PARITY_EVEN;
 194                break;
 195        default:
 196                return -ENOTSUPP; /* not supported in driver */
 197        }
 198
 199        writel(val, &regs->mode);
 200
 201        return 0;
 202}
 203#else
 204#define zynq_serial_setconfig NULL
 205#endif
 206
 207static int zynq_serial_probe(struct udevice *dev)
 208{
 209        struct zynq_uart_plat *plat = dev_get_plat(dev);
 210        struct uart_zynq *regs = plat->regs;
 211        u32 val;
 212
 213        /* No need to reinitialize the UART if TX already enabled */
 214        val = readl(&regs->control);
 215        if (val & ZYNQ_UART_CR_TX_EN)
 216                return 0;
 217
 218        _uart_zynq_serial_init(plat->regs);
 219
 220        return 0;
 221}
 222
 223static int zynq_serial_getc(struct udevice *dev)
 224{
 225        struct zynq_uart_plat *plat = dev_get_plat(dev);
 226        struct uart_zynq *regs = plat->regs;
 227
 228        if (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
 229                return -EAGAIN;
 230
 231        return readl(&regs->tx_rx_fifo);
 232}
 233
 234static int zynq_serial_putc(struct udevice *dev, const char ch)
 235{
 236        struct zynq_uart_plat *plat = dev_get_plat(dev);
 237
 238        return _uart_zynq_serial_putc(plat->regs, ch);
 239}
 240
 241static int zynq_serial_pending(struct udevice *dev, bool input)
 242{
 243        struct zynq_uart_plat *plat = dev_get_plat(dev);
 244        struct uart_zynq *regs = plat->regs;
 245
 246        if (input)
 247                return !(readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY);
 248        else
 249                return !!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXACTIVE);
 250}
 251
 252static int zynq_serial_of_to_plat(struct udevice *dev)
 253{
 254        struct zynq_uart_plat *plat = dev_get_plat(dev);
 255
 256        plat->regs = (struct uart_zynq *)dev_read_addr(dev);
 257        if (IS_ERR(plat->regs))
 258                return PTR_ERR(plat->regs);
 259
 260        return 0;
 261}
 262
 263static const struct dm_serial_ops zynq_serial_ops = {
 264        .putc = zynq_serial_putc,
 265        .pending = zynq_serial_pending,
 266        .getc = zynq_serial_getc,
 267        .setbrg = zynq_serial_setbrg,
 268        .setconfig = zynq_serial_setconfig,
 269};
 270
 271static const struct udevice_id zynq_serial_ids[] = {
 272        { .compatible = "xlnx,xuartps" },
 273        { .compatible = "cdns,uart-r1p8" },
 274        { .compatible = "cdns,uart-r1p12" },
 275        { }
 276};
 277
 278U_BOOT_DRIVER(serial_zynq) = {
 279        .name   = "serial_zynq",
 280        .id     = UCLASS_SERIAL,
 281        .of_match = zynq_serial_ids,
 282        .of_to_plat = zynq_serial_of_to_plat,
 283        .plat_auto      = sizeof(struct zynq_uart_plat),
 284        .probe = zynq_serial_probe,
 285        .ops    = &zynq_serial_ops,
 286};
 287
 288#ifdef CONFIG_DEBUG_UART_ZYNQ
 289static inline void _debug_uart_init(void)
 290{
 291        struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
 292
 293        _uart_zynq_serial_init(regs);
 294        _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
 295                                 CONFIG_BAUDRATE);
 296}
 297
 298static inline void _debug_uart_putc(int ch)
 299{
 300        struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
 301
 302        while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
 303                WATCHDOG_RESET();
 304}
 305
 306DEBUG_UART_FUNCS
 307
 308#endif
 309