1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright 2008-2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP Semiconductor 5 */ 6 7#ifndef DDR2_DIMM_PARAMS_H 8#define DDR2_DIMM_PARAMS_H 9 10#define EDC_DATA_PARITY 1 11#define EDC_ECC 2 12#define EDC_AC_PARITY 4 13 14/* Parameters for a DDR dimm computed from the SPD */ 15typedef struct dimm_params_s { 16 17 /* DIMM organization parameters */ 18 char mpart[19]; /* guaranteed null terminated */ 19 20 unsigned int n_ranks; 21 unsigned int die_density; 22 unsigned long long rank_density; 23 unsigned long long capacity; 24 unsigned int data_width; 25 unsigned int primary_sdram_width; 26 unsigned int ec_sdram_width; 27 unsigned int registered_dimm; 28 unsigned int package_3ds; /* number of dies in 3DS DIMM */ 29 unsigned int device_width; /* x4, x8, x16 components */ 30 31 /* SDRAM device parameters */ 32 unsigned int n_row_addr; 33 unsigned int n_col_addr; 34 unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ 35#ifdef CONFIG_SYS_FSL_DDR4 36 unsigned int bank_addr_bits; 37 unsigned int bank_group_bits; 38#else 39 unsigned int n_banks_per_sdram_device; 40#endif 41 unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ 42 43 /* used in computing base address of DIMMs */ 44 unsigned long long base_address; 45 /* mirrored DIMMs */ 46 unsigned int mirrored_dimm; /* only for ddr3 */ 47 48 /* DIMM timing parameters */ 49 50 int mtb_ps; /* medium timebase ps */ 51 int ftb_10th_ps; /* fine timebase, in 1/10 ps */ 52 int taa_ps; /* minimum CAS latency time */ 53 int tfaw_ps; /* four active window delay */ 54 55 /* 56 * SDRAM clock periods 57 * The range for these are 1000-10000 so a short should be sufficient 58 */ 59 int tckmin_x_ps; 60 int tckmin_x_minus_1_ps; 61 int tckmin_x_minus_2_ps; 62 int tckmax_ps; 63 64 /* SPD-defined CAS latencies */ 65 unsigned int caslat_x; 66 unsigned int caslat_x_minus_1; 67 unsigned int caslat_x_minus_2; 68 69 unsigned int caslat_lowest_derated; /* Derated CAS latency */ 70 71 /* basic timing parameters */ 72 int trcd_ps; 73 int trp_ps; 74 int tras_ps; 75 76#ifdef CONFIG_SYS_FSL_DDR4 77 int trfc1_ps; 78 int trfc2_ps; 79 int trfc4_ps; 80 int trrds_ps; 81 int trrdl_ps; 82 int tccdl_ps; 83 int trfc_slr_ps; 84#else 85 int twr_ps; /* maximum = 63750 ps */ 86 int trfc_ps; /* max = 255 ns + 256 ns + .75 ns 87 = 511750 ps */ 88 int trrd_ps; /* maximum = 63750 ps */ 89 int twtr_ps; /* maximum = 63750 ps */ 90 int trtp_ps; /* byte 38, spd->trtp */ 91#endif 92 93 int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ 94 95 int refresh_rate_ps; 96 int extended_op_srt; 97 98#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) 99 int tis_ps; /* byte 32, spd->ca_setup */ 100 int tih_ps; /* byte 33, spd->ca_hold */ 101 int tds_ps; /* byte 34, spd->data_setup */ 102 int tdh_ps; /* byte 35, spd->data_hold */ 103 int tdqsq_max_ps; /* byte 44, spd->tdqsq */ 104 int tqhs_ps; /* byte 45, spd->tqhs */ 105#endif 106 107 /* DDR3 & DDR4 RDIMM */ 108 unsigned char rcw[16]; /* Register Control Word 0-15 */ 109#ifdef CONFIG_SYS_FSL_DDR4 110 unsigned int dq_mapping[18]; 111 unsigned int dq_mapping_ors; 112#endif 113} dimm_params_t; 114 115unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, 116 const generic_spd_eeprom_t *spd, 117 dimm_params_t *pdimm, 118 unsigned int dimm_number); 119 120#endif 121