LXR uboot/include/fsl

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2016 Freescale Semiconductor, Inc.
   4 */
   5
   6#ifndef FSL_MMDC_H
   7#define FSL_MMDC_H
   8
   9/* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */
  10#define MPWLGCR_HW_WL_EN                (1 << 0)
  11
  12/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
  13#define MPPDCMPR2_MPR_COMPARE_EN        (1 << 0)
  14
  15
  16/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
  17#define AUTO_RD_DQS_GATING_CALIBRATION_EN       (1 << 28)
  18
  19/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
  20#define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN      (1 << 4)
  21
  22/* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */
  23#define MMDC_MAPSR_PWR_SAV_CTRL_STAT    0x00001067
  24
  25/* MMDC Core Refresh Control Register (MMDC_MDREF) */
  26#define MDREF_START_REFRESH     (1 << 0)
  27
  28/* MMDC Core Special Command Register (MDSCR) */
  29#define CMD_ADDR_MSB_MR_OP(x)   (x << 24)
  30#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
  31#define MDSCR_DISABLE_CFG_REQ   (0 << 15)
  32#define MDSCR_ENABLE_CON_REQ    (1 << 15)
  33#define MDSCR_CON_ACK           (1 << 14)
  34#define MDSCR_WL_EN             (1 << 9)
  35#define CMD_NORMAL              (0 << 4)
  36#define CMD_PRECHARGE           (1 << 4)
  37#define CMD_AUTO_REFRESH        (2 << 4)
  38#define CMD_LOAD_MODE_REG       (3 << 4)
  39#define CMD_ZQ_CALIBRATION      (4 << 4)
  40#define CMD_PRECHARGE_BANK_OPEN (5 << 4)
  41#define CMD_MRR                 (6 << 4)
  42#define CMD_BANK_ADDR_0         0x0
  43#define CMD_BANK_ADDR_1         0x1
  44#define CMD_BANK_ADDR_2         0x2
  45#define CMD_BANK_ADDR_3         0x3
  46#define CMD_BANK_ADDR_4         0x4
  47#define CMD_BANK_ADDR_5         0x5
  48#define CMD_BANK_ADDR_6         0x6
  49#define CMD_BANK_ADDR_7         0x7
  50
  51/* MMDC Core Control Register (MDCTL) */
  52#define MDCTL_SDE0              (1 << 31)
  53#define MDCTL_SDE1              (1 << 30)
  54
  55/* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */
  56#define MPZQHWCTRL_ZQ_HW_FORCE  (1 << 16)
  57
  58/* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */
  59#define MMDC_MPMUR0_FRC_MSR     (1 << 11)
  60
  61/* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */
  62/* default 64 for a quarter cycle delay */
  63#define MMDC_MPRDDLCTL_DEFAULT_DELAY    0x40404040
  64
  65/* MMDC Registers */
  66struct mmdc_regs {
  67        u32 mdctl;
  68        u32 mdpdc;
  69        u32 mdotc;
  70        u32 mdcfg0;
  71        u32 mdcfg1;
  72        u32 mdcfg2;
  73        u32 mdmisc;
  74        u32 mdscr;
  75        u32 mdref;
  76        u32 res1[2];
  77        u32 mdrwd;
  78        u32 mdor;
  79        u32 mdmrr;
  80        u32 mdcfg3lp;
  81        u32 mdmr4;
  82        u32 mdasp;
  83        u32 res2[239];
  84        u32 maarcr;
  85        u32 mapsr;
  86        u32 maexidr0;
  87        u32 maexidr1;
  88        u32 madpcr0;
  89        u32 madpcr1;
  90        u32 madpsr0;
  91        u32 madpsr1;
  92        u32 madpsr2;
  93        u32 madpsr3;
  94        u32 madpsr4;
  95        u32 madpsr5;
  96        u32 masbs0;
  97        u32 masbs1;
  98        u32 res3[2];
  99        u32 magenp;
 100        u32 res4[239];
 101        u32 mpzqhwctrl;
 102        u32 mpzqswctrl;
 103        u32 mpwlgcr;
 104        u32 mpwldectrl0;
 105        u32 mpwldectrl1;
 106        u32 mpwldlst;
 107        u32 mpodtctrl;
 108        u32 mprddqby0dl;
 109        u32 mprddqby1dl;
 110        u32 mprddqby2dl;
 111        u32 mprddqby3dl;
 112        u32 mpwrdqby0dl;
 113        u32 mpwrdqby1dl;
 114        u32 mpwrdqby2dl;
 115        u32 mpwrdqby3dl;
 116        u32 mpdgctrl0;
 117        u32 mpdgctrl1;
 118        u32 mpdgdlst0;
 119        u32 mprddlctl;
 120        u32 mprddlst;
 121        u32 mpwrdlctl;
 122        u32 mpwrdlst;
 123        u32 mpsdctrl;
 124        u32 mpzqlp2ctl;
 125        u32 mprddlhwctl;
 126        u32 mpwrdlhwctl;
 127        u32 mprddlhwst0;
 128        u32 mprddlhwst1;
 129        u32 mpwrdlhwst0;
 130        u32 mpwrdlhwst1;
 131        u32 mpwlhwerr;
 132        u32 mpdghwst0;
 133        u32 mpdghwst1;
 134        u32 mpdghwst2;
 135        u32 mpdghwst3;
 136        u32 mppdcmpr1;
 137        u32 mppdcmpr2;
 138        u32 mpswdar0;
 139        u32 mpswdrdr0;
 140        u32 mpswdrdr1;
 141        u32 mpswdrdr2;
 142        u32 mpswdrdr3;
 143        u32 mpswdrdr4;
 144        u32 mpswdrdr5;
 145        u32 mpswdrdr6;
 146        u32 mpswdrdr7;
 147        u32 mpmur0;
 148        u32 mpwrcadl;
 149        u32 mpdccr;
 150};
 151
 152struct fsl_mmdc_info {
 153        u32 mdctl;
 154        u32 mdpdc;
 155        u32 mdotc;
 156        u32 mdcfg0;
 157        u32 mdcfg1;
 158        u32 mdcfg2;
 159        u32 mdmisc;
 160        u32 mdref;
 161        u32 mdrwd;
 162        u32 mdor;
 163        u32 mdasp;
 164        u32 mpodtctrl;
 165        u32 mpzqhwctrl;
 166        u32 mprddlctl;
 167};
 168
 169void mmdc_init(const struct fsl_mmdc_info *);
 170
 171#endif /* FSL_MMDC_H */
 172