LXR uboot/post/lib_powerpc/rlwimi.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2002
   4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5 */
   6
   7#include <common.h>
   8#include <irq_func.h>
   9
  10/*
  11 * CPU test
  12 * Shift instructions:          rlwimi
  13 *
  14 * The test contains a pre-built table of instructions, operands and
  15 * expected results. For each table entry, the test will cyclically use
  16 * different sets of operand registers and result registers.
  17 */
  18
  19#include <post.h>
  20#include "cpu_asm.h"
  21
  22#if CONFIG_POST & CONFIG_SYS_POST_CPU
  23
  24extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
  25    ulong op2);
  26extern ulong cpu_post_makecr (long v);
  27
  28static struct cpu_post_rlwimi_s
  29{
  30    ulong cmd;
  31    ulong op0;
  32    ulong op1;
  33    uchar op2;
  34    uchar mb;
  35    uchar me;
  36    ulong res;
  37} cpu_post_rlwimi_table[] =
  38{
  39    {
  40        OP_RLWIMI,
  41        0xff00ffff,
  42        0x0000aa00,
  43        8,
  44        8,
  45        15,
  46        0xffaaffff
  47    },
  48};
  49static unsigned int cpu_post_rlwimi_size = ARRAY_SIZE(cpu_post_rlwimi_table);
  50
  51int cpu_post_test_rlwimi (void)
  52{
  53    int ret = 0;
  54    unsigned int i, reg;
  55    int flag = disable_interrupts();
  56
  57    for (i = 0; i < cpu_post_rlwimi_size && ret == 0; i++)
  58    {
  59        struct cpu_post_rlwimi_s *test = cpu_post_rlwimi_table + i;
  60
  61        for (reg = 0; reg < 32 && ret == 0; reg++)
  62        {
  63            unsigned int reg0 = (reg + 0) % 32;
  64            unsigned int reg1 = (reg + 1) % 32;
  65            unsigned int stk = reg < 16 ? 31 : 15;
  66            unsigned long code[] =
  67            {
  68                ASM_STW(stk, 1, -4),
  69                ASM_ADDI(stk, 1, -20),
  70                ASM_STW(3, stk, 8),
  71                ASM_STW(4, stk, 12),
  72                ASM_STW(reg0, stk, 4),
  73                ASM_STW(reg1, stk, 0),
  74                ASM_LWZ(reg1, stk, 8),
  75                ASM_LWZ(reg0, stk, 12),
  76                ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me),
  77                ASM_STW(reg1, stk, 8),
  78                ASM_LWZ(reg1, stk, 0),
  79                ASM_LWZ(reg0, stk, 4),
  80                ASM_LWZ(3, stk, 8),
  81                ASM_ADDI(1, stk, 20),
  82                ASM_LWZ(stk, 1, -4),
  83                ASM_BLR,
  84            };
  85            unsigned long codecr[] =
  86            {
  87                ASM_STW(stk, 1, -4),
  88                ASM_ADDI(stk, 1, -20),
  89                ASM_STW(3, stk, 8),
  90                ASM_STW(4, stk, 12),
  91                ASM_STW(reg0, stk, 4),
  92                ASM_STW(reg1, stk, 0),
  93                ASM_LWZ(reg1, stk, 8),
  94                ASM_LWZ(reg0, stk, 12),
  95                ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me) |
  96                    BIT_C,
  97                ASM_STW(reg1, stk, 8),
  98                ASM_LWZ(reg1, stk, 0),
  99                ASM_LWZ(reg0, stk, 4),
 100                ASM_LWZ(3, stk, 8),
 101                ASM_ADDI(1, stk, 20),
 102                ASM_LWZ(stk, 1, -4),
 103                ASM_BLR,
 104            };
 105            ulong res;
 106            ulong cr;
 107
 108            if (ret == 0)
 109            {
 110                cr = 0;
 111                cpu_post_exec_22 (code, & cr, & res, test->op0, test->op1);
 112
 113                ret = res == test->res && cr == 0 ? 0 : -1;
 114
 115                if (ret != 0)
 116                {
 117                    post_log ("Error at rlwimi test %d !\n", i);
 118                }
 119            }
 120
 121            if (ret == 0)
 122            {
 123                cpu_post_exec_22 (codecr, & cr, & res, test->op0, test->op1);
 124
 125                ret = res == test->res &&
 126                      (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
 127
 128                if (ret != 0)
 129                {
 130                    post_log ("Error at rlwimi test %d !\n", i);
 131                }
 132            }
 133        }
 134    }
 135
 136    if (flag)
 137        enable_interrupts();
 138
 139    return ret;
 140}
 141
 142#endif
 143