LXR uboot/arch/microblaze/cpu/cache.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2007 Michal Simek
   4 *
   5 * Michal SIMEK <monstr@monstr.eu>
   6 */
   7
   8#include <common.h>
   9#include <cpu_func.h>
  10#include <asm/asm.h>
  11#include <asm/cache.h>
  12
  13int dcache_status(void)
  14{
  15        int i = 0;
  16        int mask = 0x80;
  17        __asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
  18        /* i&=0x80 */
  19        __asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
  20        return i;
  21}
  22
  23int icache_status(void)
  24{
  25        int i = 0;
  26        int mask = 0x20;
  27        __asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
  28        /* i&=0x20 */
  29        __asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
  30        return i;
  31}
  32
  33void icache_enable(void)
  34{
  35        MSRSET(0x20);
  36}
  37
  38void icache_disable(void)
  39{
  40        /* we are not generate ICACHE size -> flush whole cache */
  41        flush_cache(0, 32768);
  42        MSRCLR(0x20);
  43}
  44
  45void dcache_enable(void)
  46{
  47        MSRSET(0x80);
  48}
  49
  50void dcache_disable(void)
  51{
  52#ifdef XILINX_USE_DCACHE
  53        flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
  54#endif
  55        MSRCLR(0x80);
  56}
  57
  58void flush_cache(ulong addr, ulong size)
  59{
  60        int i;
  61        for (i = 0; i < size; i += 4)
  62                asm volatile (
  63#ifdef CONFIG_ICACHE
  64                                "wic    %0, r0;"
  65#endif
  66                                "nop;"
  67#ifdef CONFIG_DCACHE
  68                                "wdc.flush      %0, r0;"
  69#endif
  70                                "nop;"
  71                                :
  72                                : "r" (addr + i)
  73                                : "memory");
  74}
  75