1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2010 4 * Texas Instruments, <www.ti.com> 5 * 6 * Aneesh V <aneesh@ti.com> 7 * Sricharan R <r.sricharan@ti.com> 8 */ 9#ifndef _CLOCKS_OMAP5_H_ 10#define _CLOCKS_OMAP5_H_ 11#include <asm/omap_common.h> 12 13/* 14 * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per 15 * loop, allow for a minimum of 2 ms wait (in reality the wait will be 16 * much more than that) 17 */ 18#define LDELAY 1000000 19 20/* CM_DLL_CTRL */ 21#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 22#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) 23#define CM_DLL_CTRL_NO_OVERRIDE 0 24 25/* CM_CLKMODE_DPLL */ 26#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 27#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) 28#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 29#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) 30#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 31#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) 32#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 33#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 34#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 35#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) 36#define CM_CLKMODE_DPLL_EN_SHIFT 0 37#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) 38 39#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 40#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 41 42#define DPLL_EN_STOP 1 43#define DPLL_EN_MN_BYPASS 4 44#define DPLL_EN_LOW_POWER_BYPASS 5 45#define DPLL_EN_FAST_RELOCK_BYPASS 6 46#define DPLL_EN_LOCK 7 47 48/* CM_IDLEST_DPLL fields */ 49#define ST_DPLL_CLK_MASK 1 50 51/* SGX */ 52#define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) 53#define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) 54 55/* CM_CLKSEL_DPLL */ 56#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 57#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) 58#define CM_CLKSEL_DPLL_M_SHIFT 8 59#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) 60#define CM_CLKSEL_DPLL_N_SHIFT 0 61#define CM_CLKSEL_DPLL_N_MASK 0x7F 62#define CM_CLKSEL_DCC_EN_SHIFT 22 63#define CM_CLKSEL_DCC_EN_MASK (1 << 22) 64 65/* CM_SYS_CLKSEL */ 66#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 67 68/* CM_CLKSEL_CORE */ 69#define CLKSEL_CORE_SHIFT 0 70#define CLKSEL_L3_SHIFT 4 71#define CLKSEL_L4_SHIFT 8 72 73#define CLKSEL_CORE_X2_DIV_1 0 74#define CLKSEL_L3_CORE_DIV_2 1 75#define CLKSEL_L4_L3_DIV_2 1 76 77/* CM_ABE_PLL_REF_CLKSEL */ 78#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 79#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 80#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 81#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 82 83/* CM_CLKSEL_ABE_PLL_SYS */ 84#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0 85#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1 86#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0 87#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1 88 89/* CM_BYPCLK_DPLL_IVA */ 90#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 91#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 92 93#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 94 95/* CM_SHADOW_FREQ_CONFIG1 */ 96#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 97#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 98#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 99 100#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 101#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) 102 103#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 104#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) 105 106/*CM_<clock_domain>__CLKCTRL */ 107#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 108#define CD_CLKCTRL_CLKTRCTRL_MASK 3 109 110#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 111#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 112#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 113#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 114 115 116/* CM_<clock_domain>_<module>_CLKCTRL */ 117#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 118#define MODULE_CLKCTRL_MODULEMODE_MASK 3 119#define MODULE_CLKCTRL_IDLEST_SHIFT 16 120#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) 121 122#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 123#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 124#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 125 126#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 127#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 128#define MODULE_CLKCTRL_IDLEST_IDLE 2 129#define MODULE_CLKCTRL_IDLEST_DISABLED 3 130 131/* CM_L4PER_GPIO4_CLKCTRL */ 132#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) 133 134/* CM_L3INIT_HSMMCn_CLKCTRL */ 135#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) 136#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25) 137 138/* CM_IPU1_IPU1_CLKCTRL CLKSEL MASK */ 139#define IPU1_CLKCTRL_CLKSEL_MASK BIT(24) 140 141/* CM_L3INIT_SATA_CLKCTRL */ 142#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8) 143 144/* CM_WKUP_GPTIMER1_CLKCTRL */ 145#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) 146 147/* CM_CAM_ISS_CLKCTRL */ 148#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) 149 150/* CM_DSS_DSS_CLKCTRL */ 151#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 152 153/* CM_L3INIT_USBPHY_CLKCTRL */ 154#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 155 156/* CM_L3INIT_USB_HOST_HS_CLKCTRL */ 157#define OPTFCLKEN_FUNC48M_CLK (1 << 15) 158#define OPTFCLKEN_HSIC480M_P2_CLK (1 << 14) 159#define OPTFCLKEN_HSIC480M_P1_CLK (1 << 13) 160#define OPTFCLKEN_HSIC60M_P2_CLK (1 << 12) 161#define OPTFCLKEN_HSIC60M_P1_CLK (1 << 11) 162#define OPTFCLKEN_UTMI_P3_CLK (1 << 10) 163#define OPTFCLKEN_UTMI_P2_CLK (1 << 9) 164#define OPTFCLKEN_UTMI_P1_CLK (1 << 8) 165#define OPTFCLKEN_HSIC480M_P3_CLK (1 << 7) 166#define OPTFCLKEN_HSIC60M_P3_CLK (1 << 6) 167 168/* CM_L3INIT_USB_TLL_HS_CLKCTRL */ 169#define OPTFCLKEN_USB_CH0_CLK_ENABLE (1 << 8) 170#define OPTFCLKEN_USB_CH1_CLK_ENABLE (1 << 9) 171#define OPTFCLKEN_USB_CH2_CLK_ENABLE (1 << 10) 172 173/* CM_COREAON_USB_PHY_CORE_CLKCTRL */ 174#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) 175 176/* CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL */ 177#define L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK (1 << 8) 178 179/* CM_L3INIT_USB_OTG_SS_CLKCTRL */ 180#define OTG_SS_CLKCTRL_MODULEMODE_HW (1 << 0) 181#define OPTFCLKEN_REFCLK960M (1 << 8) 182 183/* CM_L3INIT_OCP2SCP1_CLKCTRL */ 184#define OCP2SCP1_CLKCTRL_MODULEMODE_HW (1 << 0) 185 186/* CM_MPU_MPU_CLKCTRL */ 187#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 188#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24) 189#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26 190#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) 191 192/* CM_WKUPAON_SCRM_CLKCTRL */ 193#define OPTFCLKEN_SCRM_PER_SHIFT 9 194#define OPTFCLKEN_SCRM_PER_MASK (1 << 9) 195#define OPTFCLKEN_SCRM_CORE_SHIFT 8 196#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8) 197 198/* CM_COREAON_IO_SRCOMP_CLKCTRL */ 199#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8 200#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8) 201 202/* PRM_RSTTIME */ 203#define RSTTIME1_SHIFT 0 204#define RSTTIME1_MASK (0x3ff << 0) 205 206/* Clock frequencies */ 207#define OMAP_SYS_CLK_IND_38_4_MHZ 6 208 209/* PRM_VC_VAL_BYPASS */ 210#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 211 212/* CTRL_CORE_SRCOMP_NORTH_SIDE */ 213#define USB2PHY_DISCHGDET (1 << 29) 214#define USB2PHY_AUTORESUME_EN (1 << 30) 215 216/* SMPS */ 217#define SMPS_I2C_SLAVE_ADDR 0x12 218#define SMPS_REG_ADDR_12_MPU 0x23 219#define SMPS_REG_ADDR_45_IVA 0x2B 220#define SMPS_REG_ADDR_8_CORE 0x37 221 222/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */ 223/* ES1.0 settings */ 224#define VDD_MPU 1040 225#define VDD_MM 1040 226#define VDD_CORE 1040 227 228#define VDD_MPU_LOW 890 229#define VDD_MM_LOW 890 230#define VDD_CORE_LOW 890 231 232/* ES2.0 settings */ 233#define VDD_MPU_ES2 1060 234#define VDD_MM_ES2 1025 235#define VDD_CORE_ES2 1040 236 237#define VDD_MPU_ES2_HIGH 1250 238#define VDD_MM_ES2_OD 1120 239 240/* Efuse register offsets for OMAP5 platform */ 241#define OMAP5_ES2_EFUSE_BASE 0x4A002000 242#define OMAP5_ES2_PROD_REGBITS 16 243 244/* CONTROL_STD_FUSE_OPP_VDD_CORE_3 */ 245#define OMAP5_ES2_PROD_CORE_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1D8) 246 247/* CONTROL_STD_FUSE_OPP_VDD_MM_4 */ 248#define OMAP5_ES2_PROD_MM_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1A4) 249/* CONTROL_STD_FUSE_OPP_VDD_MM_5 */ 250#define OMAP5_ES2_PROD_MM_OPOD_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1A8) 251/* CONTROL_STD_FUSE_OPP_VDD_MPU_6 */ 252#define OMAP5_ES2_PROD_MPU_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1C4) 253/* CONTROL_STD_FUSE_OPP_VDD_MPU_7 */ 254#define OMAP5_ES2_PROD_MPU_OPHI_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1C8) 255 256/* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */ 257#define VDD_MPU_DRA7_NOM 1150 258#define VDD_CORE_DRA7_NOM 1150 259#define VDD_EVE_DRA7_NOM 1060 260#define VDD_GPU_DRA7_NOM 1060 261#define VDD_IVA_DRA7_NOM 1060 262 263/* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */ 264#define VDD_EVE_DRA7_OD 1150 265#define VDD_GPU_DRA7_OD 1150 266#define VDD_IVA_DRA7_OD 1150 267 268/* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */ 269#define VDD_EVE_DRA7_HIGH 1250 270#define VDD_GPU_DRA7_HIGH 1250 271#define VDD_IVA_DRA7_HIGH 1250 272 273/* Efuse register offsets for DRA7xx platform */ 274#define DRA752_EFUSE_BASE 0x4A002000 275#define DRA752_EFUSE_REGBITS 16 276/* STD_FUSE_OPP_VMIN_IVA_2 */ 277#define STD_FUSE_OPP_VMIN_IVA_NOM (DRA752_EFUSE_BASE + 0x05CC) 278/* STD_FUSE_OPP_VMIN_IVA_3 */ 279#define STD_FUSE_OPP_VMIN_IVA_OD (DRA752_EFUSE_BASE + 0x05D0) 280/* STD_FUSE_OPP_VMIN_IVA_4 */ 281#define STD_FUSE_OPP_VMIN_IVA_HIGH (DRA752_EFUSE_BASE + 0x05D4) 282/* STD_FUSE_OPP_VMIN_DSPEVE_2 */ 283#define STD_FUSE_OPP_VMIN_DSPEVE_NOM (DRA752_EFUSE_BASE + 0x05E0) 284/* STD_FUSE_OPP_VMIN_DSPEVE_3 */ 285#define STD_FUSE_OPP_VMIN_DSPEVE_OD (DRA752_EFUSE_BASE + 0x05E4) 286/* STD_FUSE_OPP_VMIN_DSPEVE_4 */ 287#define STD_FUSE_OPP_VMIN_DSPEVE_HIGH (DRA752_EFUSE_BASE + 0x05E8) 288/* STD_FUSE_OPP_VMIN_CORE_2 */ 289#define STD_FUSE_OPP_VMIN_CORE_NOM (DRA752_EFUSE_BASE + 0x05F4) 290/* STD_FUSE_OPP_VMIN_GPU_2 */ 291#define STD_FUSE_OPP_VMIN_GPU_NOM (DRA752_EFUSE_BASE + 0x1B08) 292/* STD_FUSE_OPP_VMIN_GPU_3 */ 293#define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C) 294/* STD_FUSE_OPP_VMIN_GPU_4 */ 295#define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10) 296/* STD_FUSE_OPP_VMIN_MPU_2 */ 297#define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20) 298/* STD_FUSE_OPP_VMIN_MPU_3 */ 299#define STD_FUSE_OPP_VMIN_MPU_OD (DRA752_EFUSE_BASE + 0x1B24) 300/* STD_FUSE_OPP_VMIN_MPU_4 */ 301#define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28) 302 303#if defined(CONFIG_DRA7_MPU_OPP_HIGH) 304#define DRA7_MPU_OPP OPP_HIGH 305#elif defined(CONFIG_DRA7_MPU_OPP_OD) 306#define DRA7_MPU_OPP OPP_OD 307#else /* OPP_NOM default */ 308#define DRA7_MPU_OPP OPP_NOM 309#endif 310 311/* OPP_NOM only available option for CORE */ 312#define DRA7_CORE_OPP OPP_NOM 313 314#if defined(CONFIG_DRA7_DSPEVE_OPP_HIGH) 315#define DRA7_DSPEVE_OPP OPP_HIGH 316#elif defined(CONFIG_DRA7_DSPEVE_OPP_OD) 317#define DRA7_DSPEVE_OPP OPP_OD 318#else /* OPP_NOM default */ 319#define DRA7_DSPEVE_OPP OPP_NOM 320#endif 321 322#if defined(CONFIG_DRA7_IVA_OPP_HIGH) 323#define DRA7_IVA_OPP OPP_HIGH 324#elif defined(CONFIG_DRA7_IVA_OPP_OD) 325#define DRA7_IVA_OPP OPP_OD 326#else /* OPP_NOM default */ 327#define DRA7_IVA_OPP OPP_NOM 328#endif 329 330#if defined(CONFIG_DRA7_GPU_OPP_HIGH) 331#define DRA7_GPU_OPP OPP_HIGH 332#elif defined(CONFIG_DRA7_GPU_OPP_OD) 333#define DRA7_GPU_OPP OPP_OD 334#else /* OPP_NOM default */ 335#define DRA7_GPU_OPP OPP_NOM 336#endif 337 338/* Standard offset is 0.5v expressed in uv */ 339#define PALMAS_SMPS_BASE_VOLT_UV 500000 340 341/* Offset is 0.73V for LP873x */ 342#define LP873X_BUCK_BASE_VOLT_UV 730000 343 344/* Offset is 0.73V for LP87565 */ 345#define LP87565_BUCK_BASE_VOLT_UV 730000 346 347/* TPS659038 */ 348#define TPS659038_I2C_SLAVE_ADDR 0x58 349#define TPS659038_REG_ADDR_SMPS12 0x23 350#define TPS659038_REG_ADDR_SMPS45 0x2B 351#define TPS659038_REG_ADDR_SMPS6 0x2F 352#define TPS659038_REG_ADDR_SMPS7 0x33 353#define TPS659038_REG_ADDR_SMPS8 0x37 354 355/* TPS65917 */ 356#define TPS65917_I2C_SLAVE_ADDR 0x58 357#define TPS65917_REG_ADDR_SMPS1 0x23 358#define TPS65917_REG_ADDR_SMPS2 0x27 359#define TPS65917_REG_ADDR_SMPS3 0x2F 360#define TPS65917_REG_ADDR_SMPS4 0x33 361 362/* LP873X */ 363#define LP873X_I2C_SLAVE_ADDR 0x60 364#define LP873X_REG_ADDR_BUCK0 0x6 365#define LP873X_REG_ADDR_BUCK1 0x7 366#define LP873X_REG_ADDR_LDO1 0xA 367 368/* LP87565 */ 369#define LP87565_I2C_SLAVE_ADDR 0x61 370#define LP87565_REG_ADDR_BUCK01 0xA 371#define LP87565_REG_ADDR_BUCK23 0xE 372 373/* TPS */ 374#define TPS62361_I2C_SLAVE_ADDR 0x60 375#define TPS62361_REG_ADDR_SET0 0x0 376#define TPS62361_REG_ADDR_SET1 0x1 377#define TPS62361_REG_ADDR_SET2 0x2 378#define TPS62361_REG_ADDR_SET3 0x3 379#define TPS62361_REG_ADDR_CTRL 0x4 380#define TPS62361_REG_ADDR_TEMP 0x5 381#define TPS62361_REG_ADDR_RMP_CTRL 0x6 382#define TPS62361_REG_ADDR_CHIP_ID 0x8 383#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 384 385#define TPS62361_BASE_VOLT_MV 500 386#define TPS62361_VSEL0_GPIO 7 387 388/* Defines for DPLL setup */ 389#define DPLL_LOCKED_FREQ_TOLERANCE_0 0 390#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 391#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 392 393#define DPLL_NO_LOCK 0 394#define DPLL_LOCK 1 395 396#if defined(CONFIG_DRA7XX) 397#define V_OSCK 20000000 /* Clock output from T2 */ 398#else 399#define V_OSCK 19200000 /* Clock output from T2 */ 400#endif 401 402#define V_SCLK V_OSCK 403 404/* CKO buffer control */ 405#define CKOBUFFER_CLK_ENABLE_MASK (1 << 28) 406 407/* AUXCLKx reg fields */ 408#define AUXCLK_ENABLE_MASK (1 << 8) 409#define AUXCLK_SRCSELECT_SHIFT 1 410#define AUXCLK_SRCSELECT_MASK (3 << 1) 411#define AUXCLK_CLKDIV_SHIFT 16 412#define AUXCLK_CLKDIV_MASK (0xF << 16) 413 414#define AUXCLK_SRCSELECT_SYS_CLK 0 415#define AUXCLK_SRCSELECT_CORE_DPLL 1 416#define AUXCLK_SRCSELECT_PER_DPLL 2 417#define AUXCLK_SRCSELECT_ALTERNATE 3 418 419#endif /* _CLOCKS_OMAP5_H_ */ 420