1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2015 4 * Toradex, Inc. 5 * 6 * Authors: Stefan Agner 7 * Sanchayan Maity 8 */ 9 10#ifndef __ASM_ARCH_VF610_DDRMC_H 11#define __ASM_ARCH_VF610_DDRMC_H 12 13#include <asm/arch/iomux-vf610.h> 14 15struct ddr3_jedec_timings { 16 u8 tinit; 17 u32 trst_pwron; 18 u32 cke_inactive; 19 u8 wrlat; 20 u8 caslat_lin; 21 u8 trc; 22 u8 trrd; 23 u8 tccd; 24 u8 tbst_int_interval; 25 u8 tfaw; 26 u8 trp; 27 u8 twtr; 28 u8 tras_min; 29 u8 tmrd; 30 u8 trtp; 31 u32 tras_max; 32 u8 tmod; 33 u8 tckesr; 34 u8 tcke; 35 u8 trcd_int; 36 u8 tras_lockout; 37 u8 tdal; 38 u8 bstlen; 39 u16 tdll; 40 u8 trp_ab; 41 u16 tref; 42 u8 trfc; 43 u16 tref_int; 44 u8 tpdex; 45 u8 txpdll; 46 u8 txsnr; 47 u16 txsr; 48 u8 cksrx; 49 u8 cksre; 50 u8 freq_chg_en; 51 u16 zqcl; 52 u16 zqinit; 53 u8 zqcs; 54 u8 ref_per_zq; 55 u8 zqcs_rotate; 56 u8 aprebit; 57 u8 cmd_age_cnt; 58 u8 age_cnt; 59 u8 q_fullness; 60 u8 odt_rd_mapcs0; 61 u8 odt_wr_mapcs0; 62 u8 wlmrd; 63 u8 wldqsen; 64}; 65 66struct ddrmc_cr_setting { 67 u32 setting; 68 int cr_rnum; /* CR register ; -1 for last entry */ 69}; 70 71struct ddrmc_phy_setting { 72 u32 setting; 73 int phy_rnum; /* PHY register ; -1 for last entry */ 74}; 75 76void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count); 77void ddrmc_phy_init(void); 78void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, 79 struct ddrmc_cr_setting *board_cr_settings, 80 struct ddrmc_phy_setting *board_phy_settings, 81 int col_diff, int row_diff); 82 83#endif 84