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8#ifndef _OMAP_COMMON_H_
9#define _OMAP_COMMON_H_
10
11#ifndef __ASSEMBLY__
12
13#include <linux/types.h>
14
15#define NUM_SYS_CLKS 7
16
17struct bd_info;
18
19struct prcm_regs {
20
21 u32 cm_clksel_core;
22 u32 cm_clksel_abe;
23 u32 cm_dll_ctrl;
24 u32 cm_clkmode_dpll_core;
25 u32 cm_idlest_dpll_core;
26 u32 cm_autoidle_dpll_core;
27 u32 cm_clksel_dpll_core;
28 u32 cm_div_m2_dpll_core;
29 u32 cm_div_m3_dpll_core;
30 u32 cm_div_h11_dpll_core;
31 u32 cm_div_h12_dpll_core;
32 u32 cm_div_h13_dpll_core;
33 u32 cm_div_h14_dpll_core;
34 u32 cm_div_h21_dpll_core;
35 u32 cm_div_h24_dpll_core;
36 u32 cm_ssc_deltamstep_dpll_core;
37 u32 cm_ssc_modfreqdiv_dpll_core;
38 u32 cm_emu_override_dpll_core;
39 u32 cm_div_h22_dpllcore;
40 u32 cm_div_h23_dpll_core;
41 u32 cm_clkmode_dpll_mpu;
42 u32 cm_idlest_dpll_mpu;
43 u32 cm_autoidle_dpll_mpu;
44 u32 cm_clksel_dpll_mpu;
45 u32 cm_div_m2_dpll_mpu;
46 u32 cm_ssc_deltamstep_dpll_mpu;
47 u32 cm_ssc_modfreqdiv_dpll_mpu;
48 u32 cm_bypclk_dpll_mpu;
49 u32 cm_clkmode_dpll_iva;
50 u32 cm_idlest_dpll_iva;
51 u32 cm_autoidle_dpll_iva;
52 u32 cm_clksel_dpll_iva;
53 u32 cm_div_h11_dpll_iva;
54 u32 cm_div_h12_dpll_iva;
55 u32 cm_ssc_deltamstep_dpll_iva;
56 u32 cm_ssc_modfreqdiv_dpll_iva;
57 u32 cm_bypclk_dpll_iva;
58 u32 cm_clkmode_dpll_abe;
59 u32 cm_idlest_dpll_abe;
60 u32 cm_autoidle_dpll_abe;
61 u32 cm_clksel_dpll_abe;
62 u32 cm_div_m2_dpll_abe;
63 u32 cm_div_m3_dpll_abe;
64 u32 cm_ssc_deltamstep_dpll_abe;
65 u32 cm_ssc_modfreqdiv_dpll_abe;
66 u32 cm_clkmode_dpll_ddrphy;
67 u32 cm_idlest_dpll_ddrphy;
68 u32 cm_autoidle_dpll_ddrphy;
69 u32 cm_clksel_dpll_ddrphy;
70 u32 cm_div_m2_dpll_ddrphy;
71 u32 cm_div_h11_dpll_ddrphy;
72 u32 cm_div_h12_dpll_ddrphy;
73 u32 cm_div_h13_dpll_ddrphy;
74 u32 cm_ssc_deltamstep_dpll_ddrphy;
75 u32 cm_clkmode_dpll_dsp;
76 u32 cm_shadow_freq_config1;
77 u32 cm_clkmode_dpll_gmac;
78 u32 cm_mpu_mpu_clkctrl;
79
80
81 u32 cm_dsp_clkstctrl;
82 u32 cm_dsp_dsp_clkctrl;
83
84
85 u32 cm1_abe_clkstctrl;
86 u32 cm1_abe_l4abe_clkctrl;
87 u32 cm1_abe_aess_clkctrl;
88 u32 cm1_abe_pdm_clkctrl;
89 u32 cm1_abe_dmic_clkctrl;
90 u32 cm1_abe_mcasp_clkctrl;
91 u32 cm1_abe_mcbsp1_clkctrl;
92 u32 cm1_abe_mcbsp2_clkctrl;
93 u32 cm1_abe_mcbsp3_clkctrl;
94 u32 cm1_abe_slimbus_clkctrl;
95 u32 cm1_abe_timer5_clkctrl;
96 u32 cm1_abe_timer6_clkctrl;
97 u32 cm1_abe_timer7_clkctrl;
98 u32 cm1_abe_timer8_clkctrl;
99 u32 cm1_abe_wdt3_clkctrl;
100
101
102 u32 cm_clksel_mpu_m3_iss_root;
103 u32 cm_clksel_usb_60mhz;
104 u32 cm_scale_fclk;
105 u32 cm_core_dvfs_perf1;
106 u32 cm_core_dvfs_perf2;
107 u32 cm_core_dvfs_perf3;
108 u32 cm_core_dvfs_perf4;
109 u32 cm_core_dvfs_current;
110 u32 cm_iva_dvfs_perf_tesla;
111 u32 cm_iva_dvfs_perf_ivahd;
112 u32 cm_iva_dvfs_perf_abe;
113 u32 cm_iva_dvfs_current;
114 u32 cm_clkmode_dpll_per;
115 u32 cm_idlest_dpll_per;
116 u32 cm_autoidle_dpll_per;
117 u32 cm_clksel_dpll_per;
118 u32 cm_div_m2_dpll_per;
119 u32 cm_div_m3_dpll_per;
120 u32 cm_div_h11_dpll_per;
121 u32 cm_div_h12_dpll_per;
122 u32 cm_div_h13_dpll_per;
123 u32 cm_div_h14_dpll_per;
124 u32 cm_ssc_deltamstep_dpll_per;
125 u32 cm_ssc_modfreqdiv_dpll_per;
126 u32 cm_emu_override_dpll_per;
127 u32 cm_clkmode_dpll_usb;
128 u32 cm_idlest_dpll_usb;
129 u32 cm_autoidle_dpll_usb;
130 u32 cm_clksel_dpll_usb;
131 u32 cm_div_m2_dpll_usb;
132 u32 cm_ssc_deltamstep_dpll_usb;
133 u32 cm_ssc_modfreqdiv_dpll_usb;
134 u32 cm_clkdcoldo_dpll_usb;
135 u32 cm_clkmode_dpll_pcie_ref;
136 u32 cm_clkmode_apll_pcie;
137 u32 cm_idlest_apll_pcie;
138 u32 cm_div_m2_apll_pcie;
139 u32 cm_clkvcoldo_apll_pcie;
140 u32 cm_clkmode_dpll_unipro;
141 u32 cm_idlest_dpll_unipro;
142 u32 cm_autoidle_dpll_unipro;
143 u32 cm_clksel_dpll_unipro;
144 u32 cm_div_m2_dpll_unipro;
145 u32 cm_ssc_deltamstep_dpll_unipro;
146 u32 cm_ssc_modfreqdiv_dpll_unipro;
147 u32 cm_coreaon_usb_phy1_core_clkctrl;
148 u32 cm_coreaon_usb_phy2_core_clkctrl;
149 u32 cm_coreaon_usb_phy3_core_clkctrl;
150 u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
151
152
153 u32 cm_coreaon_bandgap_clkctrl;
154 u32 cm_coreaon_io_srcomp_clkctrl;
155 u32 cm_l3_1_clkstctrl;
156 u32 cm_l3_1_dynamicdep;
157 u32 cm_l3_1_l3_1_clkctrl;
158 u32 cm_l3_2_clkstctrl;
159 u32 cm_l3_2_dynamicdep;
160 u32 cm_l3_2_l3_2_clkctrl;
161 u32 cm_l3_gpmc_clkctrl;
162 u32 cm_l3_2_ocmc_ram_clkctrl;
163 u32 cm_mpu_m3_clkstctrl;
164 u32 cm_mpu_m3_staticdep;
165 u32 cm_mpu_m3_dynamicdep;
166 u32 cm_mpu_m3_mpu_m3_clkctrl;
167 u32 cm_sdma_clkstctrl;
168 u32 cm_sdma_staticdep;
169 u32 cm_sdma_dynamicdep;
170 u32 cm_sdma_sdma_clkctrl;
171 u32 cm_memif_clkstctrl;
172 u32 cm_memif_dmm_clkctrl;
173 u32 cm_memif_emif_fw_clkctrl;
174 u32 cm_memif_emif_1_clkctrl;
175 u32 cm_memif_emif_2_clkctrl;
176 u32 cm_memif_dll_clkctrl;
177 u32 cm_memif_emif_h1_clkctrl;
178 u32 cm_memif_emif_h2_clkctrl;
179 u32 cm_memif_dll_h_clkctrl;
180 u32 cm_c2c_clkstctrl;
181 u32 cm_c2c_staticdep;
182 u32 cm_c2c_dynamicdep;
183 u32 cm_c2c_sad2d_clkctrl;
184 u32 cm_c2c_modem_icr_clkctrl;
185 u32 cm_c2c_sad2d_fw_clkctrl;
186 u32 cm_l4cfg_clkstctrl;
187 u32 cm_l4cfg_dynamicdep;
188 u32 cm_l4cfg_l4_cfg_clkctrl;
189 u32 cm_l4cfg_hw_sem_clkctrl;
190 u32 cm_l4cfg_mailbox_clkctrl;
191 u32 cm_l4cfg_sar_rom_clkctrl;
192 u32 cm_l3instr_clkstctrl;
193 u32 cm_l3instr_l3_3_clkctrl;
194 u32 cm_l3instr_l3_instr_clkctrl;
195 u32 cm_l3instr_intrconn_wp1_clkctrl;
196
197
198 u32 cm_ivahd_clkstctrl;
199 u32 cm_ivahd_ivahd_clkctrl;
200 u32 cm_ivahd_sl2_clkctrl;
201
202
203 u32 cm_cam_clkstctrl;
204 u32 cm_cam_iss_clkctrl;
205 u32 cm_cam_fdif_clkctrl;
206 u32 cm_cam_vip1_clkctrl;
207 u32 cm_cam_vip2_clkctrl;
208 u32 cm_cam_vip3_clkctrl;
209 u32 cm_cam_lvdsrx_clkctrl;
210 u32 cm_cam_csi1_clkctrl;
211 u32 cm_cam_csi2_clkctrl;
212
213
214 u32 cm_dss_clkstctrl;
215 u32 cm_dss_dss_clkctrl;
216
217
218 u32 cm_sgx_clkstctrl;
219 u32 cm_sgx_sgx_clkctrl;
220
221
222 u32 cm_l3init_clkstctrl;
223
224
225 u32 cm_l3init_hsmmc1_clkctrl;
226 u32 cm_l3init_hsmmc2_clkctrl;
227 u32 cm_l3init_hsi_clkctrl;
228 u32 cm_l3init_hsusbhost_clkctrl;
229 u32 cm_l3init_hsusbotg_clkctrl;
230 u32 cm_l3init_hsusbtll_clkctrl;
231 u32 cm_l3init_p1500_clkctrl;
232 u32 cm_l3init_sata_clkctrl;
233 u32 cm_l3init_fsusb_clkctrl;
234 u32 cm_l3init_ocp2scp1_clkctrl;
235 u32 cm_l3init_ocp2scp3_clkctrl;
236 u32 cm_l3init_usb_otg_ss1_clkctrl;
237 u32 cm_l3init_usb_otg_ss2_clkctrl;
238
239 u32 prm_irqstatus_mpu;
240 u32 prm_irqstatus_mpu_2;
241
242
243 u32 cm_l4per_clkstctrl;
244 u32 cm_l4per_dynamicdep;
245 u32 cm_l4per_adc_clkctrl;
246 u32 cm_l4per_gptimer10_clkctrl;
247 u32 cm_l4per_gptimer11_clkctrl;
248 u32 cm_l4per_gptimer2_clkctrl;
249 u32 cm_l4per_gptimer3_clkctrl;
250 u32 cm_l4per_gptimer4_clkctrl;
251 u32 cm_l4per_gptimer9_clkctrl;
252 u32 cm_l4per_elm_clkctrl;
253 u32 cm_l4per_gpio2_clkctrl;
254 u32 cm_l4per_gpio3_clkctrl;
255 u32 cm_l4per_gpio4_clkctrl;
256 u32 cm_l4per_gpio5_clkctrl;
257 u32 cm_l4per_gpio6_clkctrl;
258 u32 cm_l4per_hdq1w_clkctrl;
259 u32 cm_l4per_hecc1_clkctrl;
260 u32 cm_l4per_hecc2_clkctrl;
261 u32 cm_l4per_i2c1_clkctrl;
262 u32 cm_l4per_i2c2_clkctrl;
263 u32 cm_l4per_i2c3_clkctrl;
264 u32 cm_l4per_i2c4_clkctrl;
265 u32 cm_l4per_l4per_clkctrl;
266 u32 cm_l4per_mcasp2_clkctrl;
267 u32 cm_l4per_mcasp3_clkctrl;
268 u32 cm_l4per_mgate_clkctrl;
269 u32 cm_l4per_mcspi1_clkctrl;
270 u32 cm_l4per_mcspi2_clkctrl;
271 u32 cm_l4per_mcspi3_clkctrl;
272 u32 cm_l4per_mcspi4_clkctrl;
273 u32 cm_l4per_gpio7_clkctrl;
274 u32 cm_l4per_gpio8_clkctrl;
275 u32 cm_l4per_mmcsd3_clkctrl;
276 u32 cm_l4per_mmcsd4_clkctrl;
277 u32 cm_l4per_msprohg_clkctrl;
278 u32 cm_l4per_slimbus2_clkctrl;
279 u32 cm_l4per_qspi_clkctrl;
280 u32 cm_l4per_uart1_clkctrl;
281 u32 cm_l4per_uart2_clkctrl;
282 u32 cm_l4per_uart3_clkctrl;
283 u32 cm_l4per_uart4_clkctrl;
284 u32 cm_l4per_mmcsd5_clkctrl;
285 u32 cm_l4per_i2c5_clkctrl;
286 u32 cm_l4per_uart5_clkctrl;
287 u32 cm_l4per_uart6_clkctrl;
288 u32 cm_l4sec_clkstctrl;
289 u32 cm_l4sec_staticdep;
290 u32 cm_l4sec_dynamicdep;
291 u32 cm_l4sec_aes1_clkctrl;
292 u32 cm_l4sec_aes2_clkctrl;
293 u32 cm_l4sec_des3des_clkctrl;
294 u32 cm_l4sec_pkaeip29_clkctrl;
295 u32 cm_l4sec_rng_clkctrl;
296 u32 cm_l4sec_sha2md51_clkctrl;
297 u32 cm_l4sec_cryptodma_clkctrl;
298
299
300 u32 cm_abe_pll_ref_clksel;
301 u32 cm_sys_clksel;
302 u32 cm_abe_pll_sys_clksel;
303 u32 cm_wkup_clkstctrl;
304 u32 cm_wkup_l4wkup_clkctrl;
305 u32 cm_wkup_wdtimer1_clkctrl;
306 u32 cm_wkup_wdtimer2_clkctrl;
307 u32 cm_wkup_gpio1_clkctrl;
308 u32 cm_wkup_gptimer1_clkctrl;
309 u32 cm_wkup_gptimer12_clkctrl;
310 u32 cm_wkup_synctimer_clkctrl;
311 u32 cm_wkup_usim_clkctrl;
312 u32 cm_wkup_sarram_clkctrl;
313 u32 cm_wkup_keyboard_clkctrl;
314 u32 cm_wkup_rtc_clkctrl;
315 u32 cm_wkup_bandgap_clkctrl;
316 u32 cm_wkupaon_scrm_clkctrl;
317 u32 cm_wkupaon_io_srcomp_clkctrl;
318 u32 prm_rstctrl;
319 u32 prm_rstst;
320 u32 prm_rsttime;
321 u32 prm_io_pmctrl;
322 u32 prm_vc_val_bypass;
323 u32 prm_vc_cfg_i2c_mode;
324 u32 prm_vc_cfg_i2c_clk;
325 u32 prm_abbldo_mpu_setup;
326 u32 prm_abbldo_mpu_ctrl;
327 u32 prm_abbldo_mm_setup;
328 u32 prm_abbldo_mm_ctrl;
329 u32 prm_abbldo_iva_setup;
330 u32 prm_abbldo_iva_ctrl;
331 u32 prm_abbldo_eve_setup;
332 u32 prm_abbldo_eve_ctrl;
333 u32 prm_abbldo_gpu_setup;
334 u32 prm_abbldo_gpu_ctrl;
335
336 u32 cm_div_m4_dpll_core;
337 u32 cm_div_m5_dpll_core;
338 u32 cm_div_m6_dpll_core;
339 u32 cm_div_m7_dpll_core;
340 u32 cm_div_m4_dpll_iva;
341 u32 cm_div_m5_dpll_iva;
342 u32 cm_div_m4_dpll_ddrphy;
343 u32 cm_div_m5_dpll_ddrphy;
344 u32 cm_div_m6_dpll_ddrphy;
345 u32 cm_div_m4_dpll_per;
346 u32 cm_div_m5_dpll_per;
347 u32 cm_div_m6_dpll_per;
348 u32 cm_div_m7_dpll_per;
349 u32 cm_l3instr_intrconn_wp1_clkct;
350 u32 cm_l3init_usbphy_clkctrl;
351 u32 cm_l4per_mcbsp4_clkctrl;
352 u32 prm_vc_cfg_channel;
353
354
355 u32 scrm_auxclk0;
356 u32 scrm_auxclk1;
357
358
359 u32 cm_gmac_gmac_clkctrl;
360 u32 cm_gmac_clkstctrl;
361
362
363 u32 cm_ipu_clkstctrl;
364 u32 cm_ipu_i2c5_clkctrl;
365 u32 cm_ipu1_clkstctrl;
366 u32 cm_ipu1_ipu1_clkctrl;
367 u32 cm_ipu2_clkstctrl;
368 u32 cm_ipu2_ipu2_clkctrl;
369
370
371 u32 cm_l3main1_tptc1_clkctrl;
372 u32 cm_l3main1_tptc2_clkctrl;
373};
374
375struct omap_sys_ctrl_regs {
376 u32 control_status;
377 u32 control_core_mac_id_0_lo;
378 u32 control_core_mac_id_0_hi;
379 u32 control_core_mac_id_1_lo;
380 u32 control_core_mac_id_1_hi;
381 u32 control_phy_power_usb;
382 u32 control_core_mmr_lock1;
383 u32 control_core_mmr_lock2;
384 u32 control_core_mmr_lock3;
385 u32 control_core_mmr_lock4;
386 u32 control_core_mmr_lock5;
387 u32 control_core_control_io1;
388 u32 control_core_control_io2;
389 u32 control_id_code;
390 u32 control_std_fuse_die_id_0;
391 u32 control_std_fuse_die_id_1;
392 u32 control_std_fuse_die_id_2;
393 u32 control_std_fuse_die_id_3;
394 u32 control_std_fuse_opp_bgap;
395 u32 control_ldosram_iva_voltage_ctrl;
396 u32 control_ldosram_mpu_voltage_ctrl;
397 u32 control_ldosram_core_voltage_ctrl;
398 u32 control_usbotghs_ctrl;
399 u32 control_phy_power_sata;
400 u32 control_padconf_core_base;
401 u32 control_paconf_global;
402 u32 control_paconf_mode;
403 u32 control_smart1io_padconf_0;
404 u32 control_smart1io_padconf_1;
405 u32 control_smart1io_padconf_2;
406 u32 control_smart2io_padconf_0;
407 u32 control_smart2io_padconf_1;
408 u32 control_smart2io_padconf_2;
409 u32 control_smart3io_padconf_0;
410 u32 control_smart3io_padconf_1;
411 u32 control_pbias;
412 u32 control_i2c_0;
413 u32 control_camera_rx;
414 u32 control_hdmi_tx_phy;
415 u32 control_uniportm;
416 u32 control_dsiphy;
417 u32 control_mcbsplp;
418 u32 control_usb2phycore;
419 u32 control_hdmi_1;
420 u32 control_hsi;
421 u32 control_ddr3ch1_0;
422 u32 control_ddr3ch2_0;
423 u32 control_ddrch1_0;
424 u32 control_ddrch1_1;
425 u32 control_ddrch2_0;
426 u32 control_ddrch2_1;
427 u32 control_lpddr2ch1_0;
428 u32 control_lpddr2ch1_1;
429 u32 control_ddrio_0;
430 u32 control_ddrio_1;
431 u32 control_ddrio_2;
432 u32 control_ddr_control_ext_0;
433 u32 control_lpddr2io1_0;
434 u32 control_lpddr2io1_1;
435 u32 control_lpddr2io1_2;
436 u32 control_lpddr2io1_3;
437 u32 control_lpddr2io2_0;
438 u32 control_lpddr2io2_1;
439 u32 control_lpddr2io2_2;
440 u32 control_lpddr2io2_3;
441 u32 control_hyst_1;
442 u32 control_usbb_hsic_control;
443 u32 control_c2c;
444 u32 control_core_control_spare_rw;
445 u32 control_core_control_spare_r;
446 u32 control_core_control_spare_r_c0;
447 u32 control_srcomp_north_side;
448 u32 control_srcomp_south_side;
449 u32 control_srcomp_east_side;
450 u32 control_srcomp_west_side;
451 u32 control_srcomp_code_latch;
452 u32 control_pbiaslite;
453 u32 control_port_emif1_sdram_config;
454 u32 control_port_emif1_lpddr2_nvm_config;
455 u32 control_port_emif2_sdram_config;
456 u32 control_emif1_sdram_config_ext;
457 u32 control_emif2_sdram_config_ext;
458 u32 control_wkup_ldovbb_mpu_voltage_ctrl;
459 u32 control_wkup_ldovbb_mm_voltage_ctrl;
460 u32 control_wkup_ldovbb_iva_voltage_ctrl;
461 u32 control_wkup_ldovbb_eve_voltage_ctrl;
462 u32 control_wkup_ldovbb_gpu_voltage_ctrl;
463 u32 control_smart1nopmio_padconf_0;
464 u32 control_smart1nopmio_padconf_1;
465 u32 control_padconf_mode;
466 u32 control_xtal_oscillator;
467 u32 control_i2c_2;
468 u32 control_ckobuffer;
469 u32 control_wkup_control_spare_rw;
470 u32 control_wkup_control_spare_r;
471 u32 control_wkup_control_spare_r_c0;
472 u32 control_srcomp_east_side_wkup;
473 u32 control_efuse_1;
474 u32 control_efuse_2;
475 u32 control_efuse_3;
476 u32 control_efuse_4;
477 u32 control_efuse_5;
478 u32 control_efuse_6;
479 u32 control_efuse_7;
480 u32 control_efuse_8;
481 u32 control_efuse_9;
482 u32 control_efuse_10;
483 u32 control_efuse_11;
484 u32 control_efuse_12;
485 u32 control_efuse_13;
486 u32 control_padconf_wkup_base;
487 u32 iodelay_config_base;
488 u32 ctrl_core_sma_sw_0;
489 u32 ctrl_core_sma_sw_1;
490};
491
492#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
493struct dpll_params {
494 u32 m;
495 u32 n;
496 s8 m2;
497 s8 m3;
498 s8 m4_h11;
499 s8 m5_h12;
500 s8 m6_h13;
501 s8 m7_h14;
502 s8 h21;
503 s8 h22;
504 s8 h23;
505 s8 h24;
506};
507
508struct dpll_regs {
509 u32 cm_clkmode_dpll;
510 u32 cm_idlest_dpll;
511 u32 cm_autoidle_dpll;
512 u32 cm_clksel_dpll;
513 u32 cm_div_m2_dpll;
514 u32 cm_div_m3_dpll;
515 u32 cm_div_m4_h11_dpll;
516 u32 cm_div_m5_h12_dpll;
517 u32 cm_div_m6_h13_dpll;
518 u32 cm_div_m7_h14_dpll;
519 u32 reserved[2];
520 u32 cm_div_h21_dpll;
521 u32 cm_div_h22_dpll;
522 u32 cm_div_h23_dpll;
523 u32 cm_div_h24_dpll;
524};
525#endif
526
527struct dplls {
528 const struct dpll_params *mpu;
529 const struct dpll_params *core;
530 const struct dpll_params *per;
531 const struct dpll_params *abe;
532 const struct dpll_params *iva;
533 const struct dpll_params *usb;
534 const struct dpll_params *ddr;
535 const struct dpll_params *gmac;
536};
537
538struct pmic_data {
539 u32 base_offset;
540 u32 step;
541 u32 start_code;
542 unsigned gpio;
543 int gpio_en;
544 u32 i2c_slave_addr;
545 void (*pmic_bus_init)(void);
546 int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
547};
548
549#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
550enum {
551 OPP_LOW,
552 OPP_NOM,
553 OPP_OD,
554 OPP_HIGH,
555 NUM_OPPS,
556};
557
558
559
560
561
562
563struct volts_efuse_data {
564 u32 reg[NUM_OPPS];
565 u8 reg_bits;
566};
567
568struct volts {
569 u32 value[NUM_OPPS];
570 u32 addr;
571 struct volts_efuse_data efuse;
572 struct pmic_data *pmic;
573
574 u32 abb_tx_done_mask;
575};
576
577enum {
578 VOLT_MPU,
579 VOLT_CORE,
580 VOLT_MM,
581 VOLT_GPU,
582 VOLT_EVE,
583 VOLT_IVA,
584 NUM_VOLT_RAILS,
585};
586
587struct vcores_data {
588 struct volts mpu;
589 struct volts core;
590 struct volts mm;
591 struct volts gpu;
592 struct volts eve;
593 struct volts iva;
594};
595#endif
596
597extern struct prcm_regs const **prcm;
598extern struct prcm_regs const omap5_es1_prcm;
599extern struct prcm_regs const omap5_es2_prcm;
600extern struct prcm_regs const omap4_prcm;
601extern struct prcm_regs const dra7xx_prcm;
602extern struct dplls const **dplls_data;
603extern struct dplls dra7xx_dplls;
604extern struct dplls dra72x_dplls;
605extern struct dplls dra76x_dplls;
606extern struct vcores_data const **omap_vcores;
607extern const u32 sys_clk_array[8];
608extern struct omap_sys_ctrl_regs const **ctrl;
609extern struct omap_sys_ctrl_regs const am33xx_ctrl;
610extern struct omap_sys_ctrl_regs const omap3_ctrl;
611extern struct omap_sys_ctrl_regs const omap4_ctrl;
612extern struct omap_sys_ctrl_regs const omap5_ctrl;
613extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
614
615extern struct pmic_data tps659038;
616extern struct pmic_data lp8733;
617extern struct pmic_data lp87565;
618
619void hw_data_init(void);
620
621const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
622const struct dpll_params *get_core_dpll_params(struct dplls const *);
623const struct dpll_params *get_per_dpll_params(struct dplls const *);
624const struct dpll_params *get_iva_dpll_params(struct dplls const *);
625const struct dpll_params *get_usb_dpll_params(struct dplls const *);
626const struct dpll_params *get_abe_dpll_params(struct dplls const *);
627
628#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
629void do_enable_clocks(u32 const *clk_domains,
630 u32 const *clk_modules_hw_auto,
631 u32 const *clk_modules_explicit_en,
632 u8 wait_for_enable);
633
634void do_disable_clocks(u32 const *clk_domains,
635 u32 const *clk_modules_disable,
636 u8 wait_for_disable);
637#endif
638
639void do_enable_ipu_clocks(u32 const *clk_domains,
640 u32 const *clk_modules_hw_auto,
641 u32 const *clk_modules_explicit_en,
642 u8 wait_for_enable);
643void enable_ipu1_clocks(void);
644void enable_ipu2_clocks(void);
645void setup_post_dividers(u32 const base,
646 const struct dpll_params *params);
647u32 omap_ddr_clk(void);
648u32 get_sys_clk_index(void);
649void enable_basic_clocks(void);
650void enable_basic_uboot_clocks(void);
651
652void enable_usb_clocks(int index);
653void disable_usb_clocks(int index);
654
655#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
656void scale_vcores(struct vcores_data const *);
657#endif
658int get_voltrail_opp(int rail_offset);
659u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
660void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
661void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
662 u32 txdone, u32 txdone_mask, u32 opp);
663s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
664
665struct tag_serialnr;
666
667void omap_die_id_serial(void);
668void omap_die_id_get_board_serial(struct tag_serialnr *serialnr);
669void omap_die_id_usbethaddr(void);
670void omap_die_id_display(void);
671
672#ifdef CONFIG_FASTBOOT_FLASH
673void omap_set_fastboot_vars(void);
674#else
675static inline void omap_set_fastboot_vars(void) { }
676#endif
677
678void recalibrate_iodelay(void);
679
680void omap_smc1(u32 service, u32 val);
681
682
683
684
685
686u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params);
687u32 omap_smc_sec_cpu1(u32 service, u32 proc_id, u32 flag, u32 *params);
688
689void enable_edma3_clocks(void);
690void disable_edma3_clocks(void);
691
692void omap_die_id(unsigned int *die_id);
693
694
695void gpi2c_init(void);
696
697
698int ft_hs_disable_rng(void *fdt, struct bd_info *bd);
699int ft_hs_fixup_dram(void *fdt, struct bd_info *bd);
700int ft_hs_add_tee(void *fdt, struct bd_info *bd);
701
702
703#define OMAP_ABB_NOMINAL_OPP 0
704#define OMAP_ABB_FAST_OPP 1
705#define OMAP_ABB_SLOW_OPP 3
706#define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK (0x1 << 0)
707#define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK (0x1 << 1)
708#define OMAP_ABB_CONTROL_OPP_CHANGE_MASK (0x1 << 2)
709#define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK (0x1 << 6)
710#define OMAP_ABB_SETUP_SR2EN_MASK (0x1 << 0)
711#define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK (0x1 << 2)
712#define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK (0x1 << 1)
713#define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK (0xff << 8)
714
715static inline u32 omap_revision(void)
716{
717 extern u32 *const omap_si_rev;
718 return *omap_si_rev;
719}
720
721#define OMAP44xx 0x44000000
722
723static inline u8 is_omap44xx(void)
724{
725 extern u32 *const omap_si_rev;
726 return (*omap_si_rev & 0xFF000000) == OMAP44xx;
727};
728
729#define OMAP54xx 0x54000000
730
731static inline u8 is_omap54xx(void)
732{
733 extern u32 *const omap_si_rev;
734 return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
735}
736
737#define DRA7XX 0x07000000
738#define DRA72X 0x07200000
739#define DRA76X 0x07600000
740
741static inline u8 is_dra7xx(void)
742{
743 extern u32 *const omap_si_rev;
744 return ((*omap_si_rev & 0xFF000000) == DRA7XX);
745}
746
747static inline u8 is_dra72x(void)
748{
749 extern u32 *const omap_si_rev;
750 return (*omap_si_rev & 0xFFF00000) == DRA72X;
751}
752
753static inline u8 is_dra76x(void)
754{
755 extern u32 *const omap_si_rev;
756 return (*omap_si_rev & 0xFFF00000) == DRA76X;
757}
758
759static inline u8 is_dra76x_abz(void)
760{
761 extern u32 *const omap_si_rev;
762 return (*omap_si_rev & 0xF) == 2;
763}
764
765static inline u8 is_dra76x_acd(void)
766{
767 extern u32 *const omap_si_rev;
768 return (*omap_si_rev & 0xF) == 3;
769}
770#endif
771
772
773
774
775
776
777
778
779#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
780#define OMAP4430_ES1_0 0x44300100
781#define OMAP4430_ES2_0 0x44300200
782#define OMAP4430_ES2_1 0x44300210
783#define OMAP4430_ES2_2 0x44300220
784#define OMAP4430_ES2_3 0x44300230
785#define OMAP4460_ES1_0 0x44600100
786#define OMAP4460_ES1_1 0x44600110
787#define OMAP4470_ES1_0 0x44700100
788
789
790#define OMAP5430_SILICON_ID_INVALID 0
791#define OMAP5430_ES1_0 0x54300100
792#define OMAP5432_ES1_0 0x54320100
793#define OMAP5430_ES2_0 0x54300200
794#define OMAP5432_ES2_0 0x54320200
795
796
797#define DRA762_ES1_0 0x07620100
798#define DRA752_ES1_0 0x07520100
799#define DRA752_ES1_1 0x07520110
800#define DRA752_ES2_0 0x07520200
801#define DRA722_ES1_0 0x07220100
802#define DRA722_ES2_0 0x07220200
803#define DRA722_ES2_1 0x07220210
804
805#define DRA762_ABZ_ES1_0 0x07620102
806#define DRA762_ACD_ES1_0 0x07620103
807
808
809
810
811#define TST_DEVICE 0x0
812#define EMU_DEVICE 0x1
813#define HS_DEVICE 0x2
814#define GP_DEVICE 0x3
815
816
817
818
819
820#define OMAP_SRAM_SCRATCH_OMAP_REV SRAM_SCRATCH_SPACE_ADDR
821#define OMAP_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
822#define OMAP_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
823#define OMAP_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
824#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
825#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
826#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
827#define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
828#define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24)
829#ifndef TI_SRAM_SCRATCH_BOARD_EEPROM_START
830#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
831#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
832#endif
833#define OMAP_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END)
834
835
836#define DEVICE_DATA_OFFSET 0x18
837#define BOOT_MODE_OFFSET 0x8
838
839#define CH_FLAGS_CHSETTINGS (1 << 0)
840#define CH_FLAGS_CHRAM (1 << 1)
841#define CH_FLAGS_CHFLASH (1 << 2)
842#define CH_FLAGS_CHMMCSD (1 << 3)
843
844#ifndef __ASSEMBLY__
845u32 omap_sys_boot_device(void);
846#endif
847
848#endif
849
