LXR uboot/arch/arm/mach-mediatek/mt8512/init.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Configuration for MediaTek MT8512 SoC
   4 *
   5 * Copyright (C) 2019 MediaTek Inc.
   6 * Author: Mingming Lee <mingming.lee@mediatek.com>
   7 */
   8
   9#include <clk.h>
  10#include <common.h>
  11#include <dm.h>
  12#include <fdtdec.h>
  13#include <init.h>
  14#include <log.h>
  15#include <ram.h>
  16#include <wdt.h>
  17#include <asm/arch/misc.h>
  18#include <asm/armv8/mmu.h>
  19#include <asm/cache.h>
  20#include <asm/global_data.h>
  21#include <asm/sections.h>
  22#include <dm/uclass.h>
  23#include <dt-bindings/clock/mt8512-clk.h>
  24
  25DECLARE_GLOBAL_DATA_PTR;
  26
  27int dram_init(void)
  28{
  29        return fdtdec_setup_mem_size_base();
  30}
  31
  32phys_size_t  get_effective_memsize(void)
  33{
  34        /* limit stack below tee reserve memory */
  35        return gd->ram_size - 6 * SZ_1M;
  36}
  37
  38int dram_init_banksize(void)
  39{
  40        gd->bd->bi_dram[0].start = gd->ram_base;
  41        gd->bd->bi_dram[0].size = get_effective_memsize();
  42
  43        return 0;
  44}
  45
  46void reset_cpu(void)
  47{
  48        struct udevice *watchdog_dev = NULL;
  49
  50        if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev))
  51                if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev))
  52                        psci_system_reset();
  53
  54        wdt_expire_now(watchdog_dev, 0);
  55}
  56
  57int print_cpuinfo(void)
  58{
  59        debug("CPU:   MediaTek MT8512\n");
  60        return 0;
  61}
  62
  63static struct mm_region mt8512_mem_map[] = {
  64        {
  65                /* DDR */
  66                .virt = 0x40000000UL,
  67                .phys = 0x40000000UL,
  68                .size = 0x40000000UL,
  69                .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
  70        }, {
  71                .virt = 0x00000000UL,
  72                .phys = 0x00000000UL,
  73                .size = 0x40000000UL,
  74                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  75                         PTE_BLOCK_NON_SHARE |
  76                         PTE_BLOCK_PXN | PTE_BLOCK_UXN
  77        }, {
  78                0,
  79        }
  80};
  81
  82struct mm_region *mem_map = mt8512_mem_map;
  83