LXR uboot/arch/arm/mach-omap2/am33xx/ddr.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * DDR Configuration for AM33xx devices.
   4 *
   5 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   6 */
   7
   8#include <common.h>
   9#include <log.h>
  10#include <asm/arch/cpu.h>
  11#include <asm/arch/ddr_defs.h>
  12#include <asm/arch/sys_proto.h>
  13#include <asm/io.h>
  14#include <asm/emif.h>
  15#include <linux/delay.h>
  16
  17/**
  18 * Base address for EMIF instances
  19 */
  20static struct emif_reg_struct *emif_reg[2] = {
  21                                (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
  22                                (struct emif_reg_struct *)EMIF4_1_CFG_BASE};
  23
  24/**
  25 * Base addresses for DDR PHY cmd/data regs
  26 */
  27static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
  28                                (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
  29                                (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
  30
  31static struct ddr_data_regs *ddr_data_reg[2] = {
  32                                (struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
  33                                (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
  34
  35/**
  36 * Base address for ddr io control instances
  37 */
  38static struct ddr_cmdtctrl *ioctrl_reg = {
  39                        (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
  40
  41static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
  42{
  43        u32 mr;
  44
  45        mr_addr |= cs << EMIF_REG_CS_SHIFT;
  46        writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
  47
  48        mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
  49        debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
  50        if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
  51            ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  52            ((mr & 0xff000000) >> 24) == (mr & 0xff))
  53                return mr & 0xff;
  54        else
  55                return mr;
  56}
  57
  58static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
  59{
  60        mr_addr |= cs << EMIF_REG_CS_SHIFT;
  61        writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
  62        writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
  63}
  64
  65static void configure_mr(int nr, u32 cs)
  66{
  67        u32 mr_addr;
  68
  69        while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
  70                ;
  71        set_mr(nr, cs, LPDDR2_MR10, 0x56);
  72
  73        set_mr(nr, cs, LPDDR2_MR1, 0x43);
  74        set_mr(nr, cs, LPDDR2_MR2, 0x2);
  75
  76        mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
  77        set_mr(nr, cs, mr_addr, 0x2);
  78}
  79
  80/*
  81 * Configure EMIF4D5 registers and MR registers For details about these magic
  82 * values please see the EMIF registers section of the TRM.
  83 */
  84void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
  85{
  86#ifdef CONFIG_AM43XX
  87        struct prm_device_inst *prm_device =
  88                        (struct prm_device_inst *)PRM_DEVICE_INST;
  89#endif
  90
  91        writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
  92        writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
  93        writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
  94
  95        writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
  96        writel(regs->emif_rd_wr_lvl_rmp_win,
  97               &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
  98        writel(regs->emif_rd_wr_lvl_rmp_ctl,
  99               &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
 100        writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
 101        writel(regs->emif_rd_wr_exec_thresh,
 102               &emif_reg[nr]->emif_rd_wr_exec_thresh);
 103
 104        /*
 105         * for most SOCs these registers won't need to be changed so only
 106         * write to these registers if someone explicitly has set the
 107         * register's value.
 108         */
 109        if(regs->emif_cos_config) {
 110                writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
 111                writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
 112                writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
 113                writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
 114        }
 115
 116        /*
 117         * Sequence to ensure that the PHY is in a known state prior to
 118         * startting hardware leveling.  Also acts as to latch some state from
 119         * the EMIF into the PHY.
 120         */
 121        writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 122        writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
 123        writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 124
 125        clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
 126                        EMIF_REG_INITREF_DIS_MASK);
 127
 128        writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 129        writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
 130
 131        /* Wait 1ms because of L3 timeout error */
 132        udelay(1000);
 133
 134        writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 135        writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 136
 137#ifdef CONFIG_AM43XX
 138        /*
 139         * Disable EMIF_DEVOFF
 140         * -> Cold Boot: This is just rewriting the default register value.
 141         * -> RTC Resume: Must disable DEVOFF before leveling.
 142         */
 143        writel(0, &prm_device->emif_ctrl);
 144#endif
 145
 146        /* Perform hardware leveling for DDR3 */
 147        if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
 148                writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
 149                       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
 150                writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
 151                       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
 152
 153                writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
 154
 155                /* Enable read leveling */
 156                writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
 157
 158                /* Wait 1ms because of L3 timeout error */
 159                udelay(1000);
 160
 161                /*
 162                 * Enable full read and write leveling.  Wait for read and write
 163                 * leveling bit to clear RDWRLVLFULL_START bit 31
 164                 */
 165                while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000)
 166                      != 0)
 167                        ;
 168
 169                /* Check the timeout register to see if leveling is complete */
 170                if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
 171                        puts("DDR3 H/W leveling incomplete with errors\n");
 172
 173        } else {
 174                /* DDR2 */
 175                configure_mr(nr, 0);
 176                configure_mr(nr, 1);
 177        }
 178}
 179
 180/**
 181 * Configure SDRAM
 182 */
 183void config_sdram(const struct emif_regs *regs, int nr)
 184{
 185#ifdef CONFIG_TI816X
 186        writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 187        writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1);
 188        writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
 189        writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl);   /* initially a large refresh period */
 190        writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl);   /* trigger initialization           */
 191        writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 192#else
 193        if (regs->zq_config) {
 194                writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
 195                writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
 196                writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 197
 198                /* Trigger initialization */
 199                writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
 200                /* Wait 1ms because of L3 timeout error */
 201                udelay(1000);
 202
 203                /* Write proper sdram_ref_cref_ctrl value */
 204                writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 205                writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 206        }
 207        writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 208        writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 209        writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 210
 211        /* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
 212        if (regs->ocp_config)
 213                writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
 214#endif
 215}
 216
 217/**
 218 * Set SDRAM timings
 219 */
 220void set_sdram_timings(const struct emif_regs *regs, int nr)
 221{
 222        writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
 223        writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
 224        writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
 225        writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
 226        writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
 227        writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
 228}
 229
 230/*
 231 * Configure EXT PHY registers for software leveling
 232 */
 233static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
 234{
 235        u32 *ext_phy_ctrl_base = 0;
 236        u32 *emif_ext_phy_ctrl_base = 0;
 237        __maybe_unused const u32 *ext_phy_ctrl_const_regs;
 238        u32 i = 0;
 239        __maybe_unused u32 size;
 240
 241        ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
 242        emif_ext_phy_ctrl_base =
 243                        (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
 244
 245        /* Configure external phy control timing registers */
 246        for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
 247                writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
 248                /* Update shadow registers */
 249                writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
 250        }
 251
 252#ifdef CONFIG_AM43XX
 253        /*
 254         * External phy 6-24 registers do not change with ddr frequency.
 255         * These only need to be set on DDR2 on AM43xx.
 256         */
 257        emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
 258
 259        if (!size)
 260                return;
 261
 262        for (i = 0; i < size; i++) {
 263                writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
 264                /* Update shadow registers */
 265                writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
 266        }
 267#endif
 268}
 269
 270/*
 271 * Configure EXT PHY registers for hardware leveling
 272 */
 273static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
 274{
 275        /*
 276         * Enable hardware leveling on the EMIF.  For details about these
 277         * magic values please see the EMIF registers section of the TRM.
 278         */
 279        if (regs->emif_ddr_phy_ctlr_1 & 0x00040000) {
 280                /* PHY_INVERT_CLKOUT = 1 */
 281                writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
 282                writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
 283        } else {
 284                /* PHY_INVERT_CLKOUT = 0 */
 285                writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
 286                writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
 287        }
 288
 289        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
 290        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
 291        writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
 292        writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
 293        writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
 294        writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
 295        writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
 296        writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
 297        writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
 298        writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
 299        writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
 300        writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
 301        writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
 302        writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
 303        writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
 304        writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
 305        writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
 306        writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
 307        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
 308        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
 309        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
 310        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
 311        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
 312        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
 313        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
 314        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
 315        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
 316        writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
 317        writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
 318        writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
 319
 320        /*
 321         * Sequence to ensure that the PHY is again in a known state after
 322         * hardware leveling.
 323         */
 324        writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 325        writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
 326        writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 327}
 328
 329/**
 330 * Configure DDR PHY
 331 */
 332void config_ddr_phy(const struct emif_regs *regs, int nr)
 333{
 334        /*
 335         * Disable initialization and refreshes for now until we finish
 336         * programming EMIF regs and set time between rising edge of
 337         * DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec.
 338         * We currently hardcode a value based on a max expected frequency
 339         * of 400MHz.
 340         */
 341        writel(EMIF_REG_INITREF_DIS_MASK | 0x3100,
 342                &emif_reg[nr]->emif_sdram_ref_ctrl);
 343
 344        writel(regs->emif_ddr_phy_ctlr_1,
 345                &emif_reg[nr]->emif_ddr_phy_ctrl_1);
 346        writel(regs->emif_ddr_phy_ctlr_1,
 347                &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
 348
 349        if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) {
 350                if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
 351                        ext_phy_settings_hwlvl(regs, nr);
 352                else
 353                        ext_phy_settings_swlvl(regs, nr);
 354        }
 355}
 356
 357/**
 358 * Configure DDR CMD control registers
 359 */
 360void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
 361{
 362        if (!cmd)
 363                return;
 364
 365        writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
 366        writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
 367
 368        writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
 369        writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
 370
 371        writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
 372        writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
 373}
 374
 375/**
 376 * Configure DDR DATA registers
 377 */
 378void config_ddr_data(const struct ddr_data *data, int nr)
 379{
 380        int i;
 381
 382        if (!data)
 383                return;
 384
 385        for (i = 0; i < DDR_DATA_REGS_NR; i++) {
 386                writel(data->datardsratio0,
 387                        &(ddr_data_reg[nr]+i)->dt0rdsratio0);
 388                writel(data->datawdsratio0,
 389                        &(ddr_data_reg[nr]+i)->dt0wdsratio0);
 390                writel(data->datawiratio0,
 391                        &(ddr_data_reg[nr]+i)->dt0wiratio0);
 392                writel(data->datagiratio0,
 393                        &(ddr_data_reg[nr]+i)->dt0giratio0);
 394                writel(data->datafwsratio0,
 395                        &(ddr_data_reg[nr]+i)->dt0fwsratio0);
 396                writel(data->datawrsratio0,
 397                        &(ddr_data_reg[nr]+i)->dt0wrsratio0);
 398        }
 399}
 400
 401void config_io_ctrl(const struct ctrl_ioregs *ioregs)
 402{
 403        if (!ioregs)
 404                return;
 405
 406        writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
 407        writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
 408        writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
 409        writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
 410        writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
 411#ifdef CONFIG_AM43XX
 412        writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
 413        writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
 414        writel(ioregs->emif_sdram_config_ext,
 415               &ioctrl_reg->emif_sdram_config_ext);
 416#endif
 417}
 418