LXR uboot/arch/arm/mach-sunxi/clock_sun50i

   1#include <common.h>
   2#include <asm/io.h>
   3#include <asm/arch/cpu.h>
   4#include <asm/arch/clock.h>
   5#include <asm/arch/prcm.h>
   6
   7#ifdef CONFIG_SPL_BUILD
   8void clock_init_safe(void)
   9{
  10        struct sunxi_ccm_reg *const ccm =
  11                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  12
  13        /* this seems to enable PLLs on H616 */
  14        if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
  15                setbits_le32(SUNXI_PRCM_BASE + 0x250, 0x10);
  16
  17        clock_set_pll1(408000000);
  18
  19        writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg);
  20        while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_LOCK))
  21                ;
  22
  23        clrsetbits_le32(&ccm->cpu_axi_cfg, CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK,
  24                        CCM_CPU_AXI_DEFAULT_FACTORS);
  25
  26        writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg);
  27        writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg);
  28        writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg);
  29
  30        /*
  31         * The mux and factor are set, but the clock will be enabled in
  32         * DRAM initialization code.
  33         */
  34        writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg);
  35}
  36#endif
  37
  38void clock_init_uart(void)
  39{
  40        struct sunxi_ccm_reg *const ccm =
  41                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  42
  43        /* uart clock source is apb2 */
  44        writel(APB2_CLK_SRC_OSC24M|
  45               APB2_CLK_RATE_N_1|
  46               APB2_CLK_RATE_M(1),
  47               &ccm->apb2_cfg);
  48
  49        /* open the clock for uart */
  50        setbits_le32(&ccm->uart_gate_reset,
  51                     1 << (CONFIG_CONS_INDEX - 1));
  52
  53        /* deassert uart reset */
  54        setbits_le32(&ccm->uart_gate_reset,
  55                     1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1));
  56}
  57
  58#ifdef CONFIG_SPL_BUILD
  59void clock_set_pll1(unsigned int clk)
  60{
  61        struct sunxi_ccm_reg * const ccm =
  62                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  63        u32 val;
  64
  65        /* Do not support clocks < 288MHz as they need factor P */
  66        if (clk < 288000000) clk = 288000000;
  67
  68        /* Switch to 24MHz clock while changing PLL1 */
  69        val = readl(&ccm->cpu_axi_cfg);
  70        val &= ~CCM_CPU_AXI_MUX_MASK;
  71        val |= CCM_CPU_AXI_MUX_OSC24M;
  72        writel(val, &ccm->cpu_axi_cfg);
  73
  74        /* clk = 24*n/p, p is ignored if clock is >288MHz */
  75        writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 |
  76#ifdef CONFIG_MACH_SUN50I_H616
  77               CCM_PLL1_OUT_EN |
  78#endif
  79               CCM_PLL1_CTRL_N(clk / 24000000), &ccm->pll1_cfg);
  80        while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {}
  81
  82        /* Switch CPU to PLL1 */
  83        val = readl(&ccm->cpu_axi_cfg);
  84        val &= ~CCM_CPU_AXI_MUX_MASK;
  85        val |= CCM_CPU_AXI_MUX_PLL_CPUX;
  86        writel(val, &ccm->cpu_axi_cfg);
  87}
  88#endif
  89
  90unsigned int clock_get_pll6(void)
  91{
  92        struct sunxi_ccm_reg *const ccm =
  93                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  94        int m = IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? 4 : 2;
  95
  96        uint32_t rval = readl(&ccm->pll6_cfg);
  97        int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
  98        int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
  99                        CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
 100        int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
 101                        CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
 102        /* The register defines PLL6-2X or PLL6-4X, not plain PLL6 */
 103        return 24000000 / m * n / div1 / div2;
 104}
 105
 106int clock_twi_onoff(int port, int state)
 107{
 108        struct sunxi_ccm_reg *const ccm =
 109                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 110        struct sunxi_prcm_reg *const prcm =
 111                (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
 112        u32 value, *ptr;
 113        int shift;
 114
 115        value = BIT(GATE_SHIFT) | BIT (RESET_SHIFT);
 116
 117        if (port == 5) {
 118                shift = 0;
 119                ptr = &prcm->twi_gate_reset;
 120        } else {
 121                shift = port;
 122                ptr = &ccm->twi_gate_reset;
 123        }
 124
 125        /* set the apb clock gate and reset for twi */
 126        if (state)
 127                setbits_le32(ptr, value << shift);
 128        else
 129                clrbits_le32(ptr, value << shift);
 130
 131        return 0;
 132}
 133