uboot/arch/arm/mach-zynq/Kconfig
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Prefs
   1if ARCH_ZYNQ
   2
   3config SPL_LDSCRIPT
   4        default "arch/arm/mach-zynq/u-boot-spl.lds"
   5
   6config SPL_FS_FAT
   7        default y
   8
   9config SPL_LIBCOMMON_SUPPORT
  10        default y
  11
  12config SPL_LIBDISK_SUPPORT
  13        default y
  14
  15config SPL_LIBGENERIC_SUPPORT
  16        default y
  17
  18config SPL_MMC
  19        default y if MMC_SDHCI_ZYNQ
  20
  21config SPL_SERIAL
  22        default y
  23
  24config SPL_SPI_FLASH_SUPPORT
  25        default y if ZYNQ_QSPI
  26
  27config SPL_SPI
  28        default y if ZYNQ_QSPI
  29
  30config ZYNQ_DDRC_INIT
  31        bool "Zynq DDRC initialization"
  32        default y
  33        help
  34          This option used to perform DDR specific initialization
  35          if required. There might be cases like ddr less where we
  36          want to skip ddr init and this option is useful for it.
  37
  38config SYS_BOARD
  39        string "Board name"
  40        default "zynq"
  41
  42config SYS_VENDOR
  43        string "Vendor name"
  44        default "xilinx"
  45
  46config SYS_SOC
  47        default "zynq"
  48
  49config SYS_CONFIG_NAME
  50        string "Board configuration name"
  51        default "zynq-common"
  52        help
  53          This option contains information about board configuration name.
  54          Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
  55          will be used for board configuration.
  56
  57config SYS_MALLOC_F_LEN
  58        default 0x800
  59
  60config SYS_MALLOC_LEN
  61        default 0x1400000
  62
  63config BOOT_INIT_FILE
  64        string "boot.bin init register filename"
  65        default ""
  66        help
  67          Add register writes to boot.bin format (max 256 pairs).
  68          Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
  69
  70config ZYNQ_SDHCI_MAX_FREQ
  71        default 52000000
  72
  73source "board/xilinx/Kconfig"
  74source "board/xilinx/zynq/Kconfig"
  75
  76endif
  77