LXR uboot/arch/m68k/cpu/mcf5445x/cpu

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 *
   4 * (C) Copyright 2000-2003
   5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6 *
   7 * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
   8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   9 */
  10
  11#include <common.h>
  12#include <cpu_func.h>
  13#include <init.h>
  14#include <watchdog.h>
  15#include <asm/immap.h>
  16#include <asm/processor.h>
  17#include <asm/rtc.h>
  18#include <asm/io.h>
  19#include <linux/compiler.h>
  20
  21#if defined(CONFIG_CMD_NET)
  22#include <config.h>
  23#include <net.h>
  24#include <asm/fec.h>
  25#endif
  26
  27void init_fbcs(void)
  28{
  29        fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
  30
  31#if !defined(CONFIG_SERIAL_BOOT)
  32#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
  33        out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  34        out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  35        out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
  36#endif
  37#endif
  38
  39#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
  40        /* Latch chipselect */
  41        out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  42        out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  43        out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
  44#endif
  45
  46#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
  47        out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  48        out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  49        out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
  50#endif
  51
  52#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
  53        out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  54        out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  55        out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
  56#endif
  57
  58#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
  59        out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  60        out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  61        out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
  62#endif
  63
  64#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
  65        out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  66        out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  67        out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
  68#endif
  69}
  70
  71#ifdef CONFIG_CF_DSPI
  72void cfspi_port_conf(void)
  73{
  74        gpio_t *gpio = (gpio_t *)MMAP_GPIO;
  75
  76#ifdef CONFIG_MCF5441x
  77        pm_t *pm = (pm_t *)MMAP_PM;
  78
  79        out_8(&gpio->par_dspi0,
  80              GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
  81              GPIO_PAR_DSPI0_SCK_DSPI0SCK);
  82        out_8(&gpio->srcr_dspiow, 3);
  83
  84        /* DSPI0 */
  85        out_8(&pm->pmcr0, 23);
  86#endif
  87}
  88#endif
  89
  90/*
  91 * Breath some life into the CPU...
  92 *
  93 * Set up the memory map,
  94 * initialize a bunch of registers,
  95 * initialize the UPM's
  96 */
  97void cpu_init_f(void)
  98{
  99        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 100
 101#ifdef CONFIG_MCF5441x
 102        scm_t *scm = (scm_t *) MMAP_SCM;
 103        pm_t *pm = (pm_t *) MMAP_PM;
 104
 105        /* Disable Switch */
 106        *(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0;
 107
 108        /* Disable core watchdog */
 109        out_be16(&scm->cwcr, 0);
 110        out_8(&gpio->par_fbctl,
 111                GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE |
 112                GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
 113                GPIO_PAR_FBCTL_TA_TA);
 114        out_8(&gpio->par_be,
 115                GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
 116                GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
 117
 118        /* eDMA */
 119        out_8(&pm->pmcr0, 17);
 120
 121        /* INTR0 - INTR2 */
 122        out_8(&pm->pmcr0, 18);
 123        out_8(&pm->pmcr0, 19);
 124        out_8(&pm->pmcr0, 20);
 125
 126        /* I2C */
 127        out_8(&pm->pmcr0, 22);
 128        out_8(&pm->pmcr1, 4);
 129        out_8(&pm->pmcr1, 7);
 130
 131        /* DTMR0 - DTMR3*/
 132        out_8(&pm->pmcr0, 28);
 133        out_8(&pm->pmcr0, 29);
 134        out_8(&pm->pmcr0, 30);
 135        out_8(&pm->pmcr0, 31);
 136
 137        /* PIT0 - PIT3 */
 138        out_8(&pm->pmcr0, 32);
 139        out_8(&pm->pmcr0, 33);
 140        out_8(&pm->pmcr0, 34);
 141        out_8(&pm->pmcr0, 35);
 142
 143        /* Edge Port */
 144        out_8(&pm->pmcr0, 36);
 145        out_8(&pm->pmcr0, 37);
 146
 147        /* USB OTG */
 148        out_8(&pm->pmcr0, 44);
 149        /* USB Host */
 150        out_8(&pm->pmcr0, 45);
 151
 152        /* ESDHC */
 153        out_8(&pm->pmcr0, 51);
 154
 155        /* ENET0 - ENET1 */
 156        out_8(&pm->pmcr0, 53);
 157        out_8(&pm->pmcr0, 54);
 158
 159        /* NAND */
 160        out_8(&pm->pmcr0, 63);
 161
 162#ifdef CONFIG_SYS_I2C_0
 163        out_8(&gpio->par_cani2c, 0xF0);
 164        /* I2C0 pull up */
 165        out_be16(&gpio->pcr_b, 0x003C);
 166        /* I2C0 max speed */
 167        out_8(&gpio->srcr_cani2c, 0x03);
 168#endif
 169#ifdef CONFIG_SYS_I2C_2
 170        /* I2C2 */
 171        out_8(&gpio->par_ssi0h, 0xA0);
 172        /* I2C2, UART7 */
 173        out_8(&gpio->par_ssi0h, 0xA8);
 174        /* UART7 */
 175        out_8(&gpio->par_ssi0l, 0x2);
 176        /* UART8, UART9 */
 177        out_8(&gpio->par_cani2c, 0xAA);
 178        /* UART4, UART0 */
 179        out_8(&gpio->par_uart0, 0xAF);
 180        /* UART5, UART1 */
 181        out_8(&gpio->par_uart1, 0xAF);
 182        /* UART6, UART2 */
 183        out_8(&gpio->par_uart2, 0xAF);
 184        /* I2C2 pull up */
 185        out_be16(&gpio->pcr_h, 0xF000);
 186#endif
 187#ifdef CONFIG_SYS_I2C_5
 188        /* I2C5 */
 189        out_8(&gpio->par_uart1, 0x0A);
 190        /* I2C5 pull up */
 191        out_be16(&gpio->pcr_e, 0x0003);
 192        out_be16(&gpio->pcr_f, 0xC000);
 193#endif
 194
 195        /* Lowest slew rate for UART0,1,2 */
 196        out_8(&gpio->srcr_uart, 0x00);
 197
 198#ifdef CONFIG_FSL_ESDHC_IMX
 199        /* eSDHC pin as faster speed */
 200        out_8(&gpio->srcr_sdhc, 0x03);
 201
 202        /* All esdhc pins as SD */
 203        out_8(&gpio->par_sdhch, 0xff);
 204        out_8(&gpio->par_sdhcl, 0xff);
 205#endif
 206#endif          /* CONFIG_MCF5441x */
 207
 208        /* FlexBus Chipselect */
 209        init_fbcs();
 210
 211#ifdef CONFIG_SYS_CS0_BASE
 212        /*
 213         * now the flash base address is no longer at 0 (Newer ColdFire family
 214         * boot at address 0 instead of 0xFFnn_nnnn). The vector table must
 215         * also move to the new location.
 216         */
 217        if (CONFIG_SYS_CS0_BASE != 0)
 218                setvbr(CONFIG_SYS_CS0_BASE);
 219#endif
 220
 221        icache_enable();
 222}
 223
 224/*
 225 * initialize higher level parts of CPU like timers
 226 */
 227int cpu_init_r(void)
 228{
 229#ifdef CONFIG_MCFRTC
 230        rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
 231        rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
 232
 233        out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
 234        out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
 235#endif
 236
 237        return (0);
 238}
 239
 240void uart_port_conf(int port)
 241{
 242        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 243#ifdef CONFIG_MCF5441x
 244        pm_t *pm = (pm_t *) MMAP_PM;
 245#endif
 246
 247        /* Setup Ports: */
 248        switch (port) {
 249#ifdef CONFIG_MCF5441x
 250        case 0:
 251                /* UART0 */
 252                out_8(&pm->pmcr0, 24);
 253                clrbits_8(&gpio->par_uart0,
 254                        ~(GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK));
 255                setbits_8(&gpio->par_uart0,
 256                        GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD);
 257                break;
 258        case 1:
 259                /* UART1 */
 260                out_8(&pm->pmcr0, 25);
 261                clrbits_8(&gpio->par_uart1,
 262                        ~(GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK));
 263                setbits_8(&gpio->par_uart1,
 264                        GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD);
 265                break;
 266        case 2:
 267                /* UART2 */
 268                out_8(&pm->pmcr0, 26);
 269                clrbits_8(&gpio->par_uart2,
 270                        ~(GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK));
 271                setbits_8(&gpio->par_uart2,
 272                        GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD);
 273                break;
 274        case 3:
 275                /* UART3 */
 276                out_8(&pm->pmcr0, 27);
 277                clrbits_8(&gpio->par_dspi0,
 278                        ~(GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK));
 279                setbits_8(&gpio->par_dspi0,
 280                        GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD);
 281                break;
 282        case 4:
 283                /* UART4 */
 284                out_8(&pm->pmcr1, 24);
 285                clrbits_8(&gpio->par_uart0,
 286                        ~(GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK));
 287                setbits_8(&gpio->par_uart0,
 288                        GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD);
 289                break;
 290        case 5:
 291                /* UART5 */
 292                out_8(&pm->pmcr1, 25);
 293                clrbits_8(&gpio->par_uart1,
 294                        ~(GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK));
 295                setbits_8(&gpio->par_uart1,
 296                        GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD);
 297                break;
 298        case 6:
 299                /* UART6 */
 300                out_8(&pm->pmcr1, 26);
 301                clrbits_8(&gpio->par_uart2,
 302                        ~(GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK));
 303                setbits_8(&gpio->par_uart2,
 304                        GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD);
 305                break;
 306        case 7:
 307                /* UART7 */
 308                out_8(&pm->pmcr1, 27);
 309                clrbits_8(&gpio->par_ssi0h, ~GPIO_PAR_SSI0H_RXD_MASK);
 310                clrbits_8(&gpio->par_ssi0l, ~GPIO_PAR_SSI0L_BCLK_MASK);
 311                setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD);
 312                setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD);
 313                break;
 314        case 8:
 315                /* UART8 */
 316                out_8(&pm->pmcr0, 28);
 317                clrbits_8(&gpio->par_cani2c,
 318                        ~(GPIO_PAR_CANI2C_I2C0SCL_MASK | GPIO_PAR_CANI2C_I2C0SDA_MASK));
 319                setbits_8(&gpio->par_cani2c,
 320                        GPIO_PAR_CANI2C_I2C0SCL_U8TXD | GPIO_PAR_CANI2C_I2C0SDA_U8RXD);
 321                break;
 322        case 9:
 323                /* UART9 */
 324                out_8(&pm->pmcr1, 29);
 325                clrbits_8(&gpio->par_cani2c,
 326                        ~(GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK));
 327                setbits_8(&gpio->par_cani2c,
 328                        GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
 329                break;
 330#endif
 331        }
 332}
 333
 334#if defined(CONFIG_CMD_NET)
 335int fecpin_setclear(fec_info_t *info, int setclear)
 336{
 337        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 338        u32 fec0_base;
 339
 340        if (fec_get_base_addr(0, &fec0_base))
 341                return -1;
 342
 343#ifdef CONFIG_MCF5441x
 344        if (setclear) {
 345                out_8(&gpio->par_fec, 0x03);
 346                out_8(&gpio->srcr_fec, 0x0F);
 347                clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK,
 348                        GPIO_PAR_SIMP0H_DAT_GPIO);
 349                clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK,
 350                        GPIO_PDDR_G4_OUTPUT);
 351                clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK);
 352
 353        } else
 354                clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK);
 355#endif
 356        return 0;
 357}
 358#endif
 359