1
2
3
4
5
6#include <common.h>
7#include <init.h>
8#include <asm/io.h>
9#include <asm/addrspace.h>
10#include <asm/global_data.h>
11#include <asm/types.h>
12#include <mach/ath79.h>
13#include <mach/ar71xx_regs.h>
14
15struct ath79_soc_desc {
16 const enum ath79_soc_type soc;
17 const char *chip;
18 const int major;
19 const int minor;
20};
21
22static const struct ath79_soc_desc desc[] = {
23 {ATH79_SOC_AR7130, "7130",
24 REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7130},
25 {ATH79_SOC_AR7141, "7141",
26 REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7141},
27 {ATH79_SOC_AR7161, "7161",
28 REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7161},
29 {ATH79_SOC_AR7240, "7240", REV_ID_MAJOR_AR7240, 0},
30 {ATH79_SOC_AR7241, "7241", REV_ID_MAJOR_AR7241, 0},
31 {ATH79_SOC_AR7242, "7242", REV_ID_MAJOR_AR7242, 0},
32 {ATH79_SOC_AR9130, "9130",
33 REV_ID_MAJOR_AR913X, AR913X_REV_ID_MINOR_AR9130},
34 {ATH79_SOC_AR9132, "9132",
35 REV_ID_MAJOR_AR913X, AR913X_REV_ID_MINOR_AR9132},
36 {ATH79_SOC_AR9330, "9330", REV_ID_MAJOR_AR9330, 0},
37 {ATH79_SOC_AR9331, "9331", REV_ID_MAJOR_AR9331, 0},
38 {ATH79_SOC_AR9341, "9341", REV_ID_MAJOR_AR9341, 0},
39 {ATH79_SOC_AR9342, "9342", REV_ID_MAJOR_AR9342, 0},
40 {ATH79_SOC_AR9344, "9344", REV_ID_MAJOR_AR9344, 0},
41 {ATH79_SOC_QCA9533, "9533", REV_ID_MAJOR_QCA9533, 0},
42 {ATH79_SOC_QCA9533, "9533",
43 REV_ID_MAJOR_QCA9533_V2, 0},
44 {ATH79_SOC_QCA9556, "9556", REV_ID_MAJOR_QCA9556, 0},
45 {ATH79_SOC_QCA9558, "9558", REV_ID_MAJOR_QCA9558, 0},
46 {ATH79_SOC_TP9343, "9343", REV_ID_MAJOR_TP9343, 0},
47 {ATH79_SOC_QCA9561, "9561", REV_ID_MAJOR_QCA9561, 0},
48};
49
50int mach_cpu_init(void)
51{
52 void __iomem *base;
53 enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
54 u32 id, major, minor = 0;
55 u32 rev = 0, ver = 1;
56 int i;
57
58 base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
59 MAP_NOCACHE);
60
61 id = readl(base + AR71XX_RESET_REG_REV_ID);
62 major = id & REV_ID_MAJOR_MASK;
63 switch (major) {
64 case REV_ID_MAJOR_AR71XX:
65 case REV_ID_MAJOR_AR913X:
66 minor = id & AR71XX_REV_ID_MINOR_MASK;
67 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
68 rev &= AR71XX_REV_ID_REVISION_MASK;
69 break;
70
71 case REV_ID_MAJOR_QCA9533_V2:
72 ver = 2;
73
74
75 case REV_ID_MAJOR_AR9341:
76 case REV_ID_MAJOR_AR9342:
77 case REV_ID_MAJOR_AR9344:
78 case REV_ID_MAJOR_QCA9533:
79 case REV_ID_MAJOR_QCA9556:
80 case REV_ID_MAJOR_QCA9558:
81 case REV_ID_MAJOR_TP9343:
82 case REV_ID_MAJOR_QCA9561:
83 rev = id & AR71XX_REV_ID_REVISION2_MASK;
84 break;
85 default:
86 rev = id & AR71XX_REV_ID_REVISION_MASK;
87 break;
88 }
89
90 for (i = 0; i < ARRAY_SIZE(desc); i++) {
91 if ((desc[i].major == major) &&
92 (desc[i].minor == minor)) {
93 soc = desc[i].soc;
94 break;
95 }
96 }
97
98 gd->arch.id = id;
99 gd->arch.soc = soc;
100 gd->arch.rev = rev;
101 gd->arch.ver = ver;
102 return 0;
103}
104
105int print_cpuinfo(void)
106{
107 enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
108 const char *chip = "????";
109 u32 id, rev, ver;
110 int i;
111
112 for (i = 0; i < ARRAY_SIZE(desc); i++) {
113 if (desc[i].soc == gd->arch.soc) {
114 chip = desc[i].chip;
115 soc = desc[i].soc;
116 break;
117 }
118 }
119
120 id = gd->arch.id;
121 rev = gd->arch.rev;
122 ver = gd->arch.ver;
123
124 switch (soc) {
125 case ATH79_SOC_QCA9533:
126 case ATH79_SOC_QCA9556:
127 case ATH79_SOC_QCA9558:
128 case ATH79_SOC_QCA9561:
129 printf("Qualcomm Atheros QCA%s ver %u rev %u\n", chip,
130 ver, rev);
131 break;
132 case ATH79_SOC_TP9343:
133 printf("Qualcomm Atheros TP%s rev %u\n", chip, rev);
134 break;
135 case ATH79_SOC_UNKNOWN:
136 printf("ATH79: unknown SoC, id:0x%08x", id);
137 break;
138 default:
139 printf("Atheros AR%s rev %u\n", chip, rev);
140 }
141
142 return 0;
143}
144
