LXR uboot/arch/xtensa/include/asm/arch-dc232b/tie-asm.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * This header file contains assembly-language definitions (assembly
   4 * macros, etc.) for this specific Xtensa processor's TIE extensions
   5 * and options.  It is customized to this Xtensa processor configuration.
   6 * This file is autogenerated, please do not edit.
   7 *
   8 * Copyright (C) 1999-2007 Tensilica Inc.
   9 */
  10
  11#ifndef _XTENSA_CORE_TIE_ASM_H
  12#define _XTENSA_CORE_TIE_ASM_H
  13
  14/*  Selection parameter values for save-area save/restore macros:  */
  15/*  Option vs. TIE:  */
  16#define XTHAL_SAS_TIE   0x0001  /* custom extension or coprocessor */
  17#define XTHAL_SAS_OPT   0x0002  /* optional (and not a coprocessor) */
  18/*  Whether used automatically by compiler:  */
  19#define XTHAL_SAS_NOCC  0x0004  /* not used by compiler w/o special opts/code */
  20#define XTHAL_SAS_CC    0x0008  /* used by compiler without special opts/code */
  21/*  ABI handling across function calls:  */
  22#define XTHAL_SAS_CALR  0x0010  /* caller-saved */
  23#define XTHAL_SAS_CALE  0x0020  /* callee-saved */
  24#define XTHAL_SAS_GLOB  0x0040  /* global across function calls (in thread) */
  25/*  Misc  */
  26#define XTHAL_SAS_ALL   0xFFFF  /* include all default NCP contents */
  27
  28
  29/* Macro to save all non-coprocessor (extra) custom TIE and optional state
  30 * (not including zero-overhead loop registers).
  31 * Save area ptr (clobbered):  ptr  (1 byte aligned)
  32 * Scratch regs  (clobbered):  at1..at4  (only first XCHAL_NCP_NUM_ATMPS needed)
  33 */
  34        .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL
  35        xchal_sa_start  \continue, \ofs
  36        .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
  37        xchal_sa_align  \ptr, 0, 1024-8, 4, 4
  38        rsr     \at1, ACCLO             // MAC16 accumulator
  39        rsr     \at2, ACCHI
  40        s32i    \at1, \ptr, .Lxchal_ofs_ + 0
  41        s32i    \at2, \ptr, .Lxchal_ofs_ + 4
  42        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 8
  43        .endif
  44        .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
  45        xchal_sa_align  \ptr, 0, 1024-16, 4, 4
  46        rsr     \at1, M0                // MAC16 registers
  47        rsr     \at2, M1
  48        s32i    \at1, \ptr, .Lxchal_ofs_ + 0
  49        s32i    \at2, \ptr, .Lxchal_ofs_ + 4
  50        rsr     \at1, M2
  51        rsr     \at2, M3
  52        s32i    \at1, \ptr, .Lxchal_ofs_ + 8
  53        s32i    \at2, \ptr, .Lxchal_ofs_ + 12
  54        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 16
  55        .endif
  56        .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
  57        xchal_sa_align  \ptr, 0, 1024-4, 4, 4
  58        rsr     \at1, SCOMPARE1         // conditional store option
  59        s32i    \at1, \ptr, .Lxchal_ofs_ + 0
  60        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 4
  61        .endif
  62        .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
  63        xchal_sa_align  \ptr, 0, 1024-4, 4, 4
  64        rur     \at1, THREADPTR         // threadptr option
  65        s32i    \at1, \ptr, .Lxchal_ofs_ + 0
  66        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 4
  67        .endif
  68        .endm   // xchal_ncp_store
  69
  70/* Macro to save all non-coprocessor (extra) custom TIE and optional state
  71 * (not including zero-overhead loop registers).
  72 * Save area ptr (clobbered):  ptr  (1 byte aligned)
  73 * Scratch regs  (clobbered):  at1..at4  (only first XCHAL_NCP_NUM_ATMPS needed)
  74 */
  75        .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL
  76        xchal_sa_start  \continue, \ofs
  77        .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
  78        xchal_sa_align  \ptr, 0, 1024-8, 4, 4
  79        l32i    \at1, \ptr, .Lxchal_ofs_ + 0
  80        l32i    \at2, \ptr, .Lxchal_ofs_ + 4
  81        wsr     \at1, ACCLO             // MAC16 accumulator
  82        wsr     \at2, ACCHI
  83        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 8
  84        .endif
  85        .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
  86        xchal_sa_align  \ptr, 0, 1024-16, 4, 4
  87        l32i    \at1, \ptr, .Lxchal_ofs_ + 0
  88        l32i    \at2, \ptr, .Lxchal_ofs_ + 4
  89        wsr     \at1, M0                // MAC16 registers
  90        wsr     \at2, M1
  91        l32i    \at1, \ptr, .Lxchal_ofs_ + 8
  92        l32i    \at2, \ptr, .Lxchal_ofs_ + 12
  93        wsr     \at1, M2
  94        wsr     \at2, M3
  95        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 16
  96        .endif
  97        .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
  98        xchal_sa_align  \ptr, 0, 1024-4, 4, 4
  99        l32i    \at1, \ptr, .Lxchal_ofs_ + 0
 100        wsr     \at1, SCOMPARE1         // conditional store option
 101        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 4
 102        .endif
 103        .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
 104        xchal_sa_align  \ptr, 0, 1024-4, 4, 4
 105        l32i    \at1, \ptr, .Lxchal_ofs_ + 0
 106        wur     \at1, THREADPTR         // threadptr option
 107        .set    .Lxchal_ofs_, .Lxchal_ofs_ + 4
 108        .endif
 109        .endm   // xchal_ncp_load
 110
 111#define XCHAL_NCP_NUM_ATMPS     2
 112
 113#define XCHAL_SA_NUM_ATMPS      2
 114
 115#endif /*_XTENSA_CORE_TIE_ASM_H*/
 116