LXR uboot/board/atmel/sama5d2_icp/sama5d2

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2018 Microchip Technology, Inc.
   4 *                    Eugen Hristev <eugen.hristev@microchip.com>
   5 */
   6
   7#include <common.h>
   8#include <debug_uart.h>
   9#include <init.h>
  10#include <asm/global_data.h>
  11#include <asm/io.h>
  12#include <asm/arch/at91_common.h>
  13#include <asm/arch/atmel_pio4.h>
  14#include <asm/arch/atmel_mpddrc.h>
  15#include <asm/arch/atmel_sdhci.h>
  16#include <asm/arch/clk.h>
  17#include <asm/arch/gpio.h>
  18#include <asm/arch/sama5d2.h>
  19
  20DECLARE_GLOBAL_DATA_PTR;
  21
  22int board_late_init(void)
  23{
  24        return 0;
  25}
  26
  27#ifdef CONFIG_DEBUG_UART_BOARD_INIT
  28static void board_uart0_hw_init(void)
  29{
  30        atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
  31        atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
  32
  33        at91_periph_clk_enable(ATMEL_ID_UART0);
  34}
  35
  36void board_debug_uart_init(void)
  37{
  38        board_uart0_hw_init();
  39}
  40#endif
  41
  42int board_early_init_f(void)
  43{
  44#ifdef CONFIG_DEBUG_UART
  45        debug_uart_init();
  46#endif
  47        return 0;
  48}
  49
  50int board_init(void)
  51{
  52        /* address of boot parameters */
  53        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  54
  55        return 0;
  56}
  57
  58int dram_init(void)
  59{
  60        gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  61                                    CONFIG_SYS_SDRAM_SIZE);
  62        return 0;
  63}
  64
  65#define MAC24AA_MAC_OFFSET      0xfa
  66
  67int misc_init_r(void)
  68{
  69#ifdef CONFIG_I2C_EEPROM
  70        at91_set_ethaddr(MAC24AA_MAC_OFFSET);
  71#endif
  72        return 0;
  73}
  74
  75/* SPL */
  76#ifdef CONFIG_SPL_BUILD
  77
  78/* must set PB25 low to enable the CAN transceivers */
  79static void board_can_stdby_dis(void)
  80{
  81        atmel_pio4_set_pio_output(AT91_PIO_PORTB, 25, 0);
  82}
  83
  84static void board_leds_init(void)
  85{
  86        atmel_pio4_set_pio_output(AT91_PIO_PORTB, 0, 0); /* RED */
  87        atmel_pio4_set_pio_output(AT91_PIO_PORTB, 1, 1); /* GREEN */
  88        atmel_pio4_set_pio_output(AT91_PIO_PORTA, 31, 0); /* BLUE */
  89}
  90
  91/* deassert reset lines for external periph in case of warm reboot */
  92static void board_reset_additional_periph(void)
  93{
  94        atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 0); /* LAN9252_RST */
  95        atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 0); /* HSIC_RST */
  96        atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 0); /* USB2534_RST */
  97        atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 0); /* KSZ8563_RST */
  98}
  99
 100static void board_start_additional_periph(void)
 101{
 102        atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 1); /* LAN9252_RST */
 103        atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 1); /* HSIC_RST */
 104        atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 1); /* USB2534_RST */
 105        atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 1); /* KSZ8563_RST */
 106}
 107
 108#ifdef CONFIG_SD_BOOT
 109void spl_mmc_init(void)
 110{
 111        atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0);  /* CMD */
 112        atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0);  /* DAT0 */
 113        atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0);  /* DAT1 */
 114        atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0);  /* DAT2 */
 115        atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0);  /* DAT3 */
 116        atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0);  /* CK */
 117        atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CD */
 118
 119        at91_periph_clk_enable(ATMEL_ID_SDMMC0);
 120}
 121#endif
 122
 123void spl_board_init(void)
 124{
 125#ifdef CONFIG_SD_BOOT
 126        spl_mmc_init();
 127#endif
 128        board_reset_additional_periph();
 129        board_can_stdby_dis();
 130        board_leds_init();
 131}
 132
 133void spl_display_print(void)
 134{
 135}
 136
 137void spl_board_prepare_for_boot(void)
 138{
 139        board_start_additional_periph();
 140}
 141
 142static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
 143{
 144        ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
 145
 146        ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 147                    ATMEL_MPDDRC_CR_NR_ROW_14 |
 148                    ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
 149                    ATMEL_MPDDRC_CR_DIC_DS |
 150                    ATMEL_MPDDRC_CR_NB_8BANKS |
 151                    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 152                    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 153
 154        ddrc->rtr = 0x298;
 155
 156        ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
 157                      (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
 158                      (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
 159                      (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
 160                      (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
 161                      (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
 162                      (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
 163                      (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
 164
 165        ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
 166                      (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
 167                      (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
 168                      (10 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
 169
 170        ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
 171                      (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
 172                      (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
 173                      (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
 174                      (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
 175}
 176
 177void mem_init(void)
 178{
 179        struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 180        struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
 181        struct atmel_mpddrc_config ddrc_config;
 182        u32 reg;
 183
 184        ddrc_conf(&ddrc_config);
 185
 186        at91_periph_clk_enable(ATMEL_ID_MPDDRC);
 187        writel(AT91_PMC_DDR, &pmc->scer);
 188
 189        reg = readl(&mpddrc->io_calibr);
 190        reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
 191        reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
 192        reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
 193        reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
 194        writel(reg, &mpddrc->io_calibr);
 195
 196        writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
 197               &mpddrc->rd_data_path);
 198
 199        ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
 200
 201        writel(0x5355, &mpddrc->cal_mr4);
 202        writel(64, &mpddrc->tim_cal);
 203}
 204
 205void at91_pmc_init(void)
 206{
 207        u32 tmp;
 208
 209        /*
 210         * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
 211         * so we need to slow down and configure MCKR accordingly.
 212         * This is why we have a special flavor of the switching function.
 213         */
 214        tmp = AT91_PMC_MCKR_PLLADIV_2 |
 215              AT91_PMC_MCKR_MDIV_3 |
 216              AT91_PMC_MCKR_CSS_MAIN;
 217        at91_mck_init_down(tmp);
 218
 219        tmp = AT91_PMC_PLLAR_29 |
 220              AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
 221              AT91_PMC_PLLXR_MUL(82) |
 222              AT91_PMC_PLLXR_DIV(1);
 223        at91_plla_init(tmp);
 224
 225        tmp = AT91_PMC_MCKR_H32MXDIV |
 226              AT91_PMC_MCKR_PLLADIV_2 |
 227              AT91_PMC_MCKR_MDIV_3 |
 228              AT91_PMC_MCKR_CSS_PLLA;
 229        at91_mck_init(tmp);
 230}
 231#endif
 232