LXR uboot/board/freescale/imx8mm_evk/imx8mm

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2018 NXP
   4 */
   5
   6#include <common.h>
   7#include <env.h>
   8#include <init.h>
   9#include <miiphy.h>
  10#include <netdev.h>
  11#include <asm/global_data.h>
  12
  13#include <asm/arch/clock.h>
  14#include <asm/arch/sys_proto.h>
  15#include <asm/io.h>
  16
  17DECLARE_GLOBAL_DATA_PTR;
  18
  19#if IS_ENABLED(CONFIG_FEC_MXC)
  20static int setup_fec(void)
  21{
  22        struct iomuxc_gpr_base_regs *gpr =
  23                (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  24
  25        /* Use 125M anatop REF_CLK1 for ENET1, not from external */
  26        clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
  27
  28        return 0;
  29}
  30
  31int board_phy_config(struct phy_device *phydev)
  32{
  33        /* enable rgmii rxc skew and phy mode select to RGMII copper */
  34        phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  35        phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  36
  37        phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
  38        phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
  39        phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  40        phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  41
  42        if (phydev->drv->config)
  43                phydev->drv->config(phydev);
  44        return 0;
  45}
  46#endif
  47
  48int board_init(void)
  49{
  50        if (IS_ENABLED(CONFIG_FEC_MXC))
  51                setup_fec();
  52
  53        return 0;
  54}
  55
  56int board_mmc_get_env_dev(int devno)
  57{
  58        return devno;
  59}
  60
  61int board_late_init(void)
  62{
  63        if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
  64                env_set("board_name", "EVK");
  65                env_set("board_rev", "iMX8MM");
  66        }
  67
  68        return 0;
  69}
  70